Radio frequency power amplifier circuit

Abstract

This disclosure provides a radio frequency power amplifier circuit. An electronic device may include a wireless circuit comprising a power amplifier having one or more common-source stages. Each stage may include a power transistor and, if desired, a capacitor neutralizing transistor. Each transistor may include a collection of unit cells, each unit cell comprising an elongated drain contact, a first elongated source contact and a second elongated source contact, and a first gate contact and a second gate contact. The source contacts may extend parallel to the drain contact along a first and a second side of the drain contact. The gate contacts may extend orthogonally to the drain contact along a third and a fourth side of the drain contact. The dual-gate connection of each unit cell can be used to reduce the gate resistance of the corresponding transistor. The first power transistor and the second power transistor may be laterally interposed on a substrate between the first capacitor neutralizing transistor and the second capacitor neutralizing transistor. This can be used to reduce area footprint while eliminating differential-mode parasitic effects.

Description

[0001] This application claims priority to U.S. Patent Application No. 19 / 016,217, filed January 10, 2025, which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates in its entirety to electronic devices, including electronic devices having wireless circuitry. Background Technology

[0003] Electronic devices may possess wireless communication capabilities. Electronic devices with wireless communication capabilities have wireless circuitry, which includes one or more antennas. The wireless transceiver circuitry within the wireless circuitry uses the antennas to transmit and receive radio frequency signals.

[0004] The radio frequency signal transmitted by the antenna can be fed through a power amplifier configured to amplify low-power analog signals into high-power signals more suitable for long-distance transmission over air. Designing satisfactory radio frequency amplifier circuits, such as power amplifiers, for electronic devices can be challenging. Summary of the Invention

[0005] The electronic device may include a wireless circuit. The wireless circuit may include a transmission path. The transmission path may include a power amplifier. The power amplifier may include a collection of one or more amplifier stages. Each amplifier stage may include a first power transistor and a second power transistor. If desired, each amplifier stage may also include a first capacitor neutralizing transistor and a second capacitor neutralizing transistor.

[0006] Each transistor in a transistor may comprise a corresponding set of transistor unit cells in a semiconductor substrate. Each set may share the source node, gate node, and drain node of the corresponding transistor. Each unit cell may include an elongated drain contact for the drain node, a first elongated source contact and a second elongated source contact for the source node, and a first gate contact and a second gate contact for the gate node. The elongated source contact may extend parallel to the elongated drain contact along a first and a second side of the drain contact. The gate contact may extend orthogonally to the drain contact along a third and a fourth side of the drain contact. Gate lines may couple the gate contacts together. Source lines may couple the source contacts together. The dual-gate connection of each unit cell can be used to reduce the gate resistance of the corresponding transistor. Furthermore, a first power transistor and a second power transistor may be laterally interposed on the semiconductor substrate between a first capacitor neutralizing transistor and a second capacitor neutralizing transistor. This can be used to reduce the amplifier area and minimize the interconnect length between the source nodes of the power transistors, thereby preventing differential-mode parasitic effects from degrading amplifier performance.

[0007] One aspect of this disclosure provides a radio frequency (RF) amplifier. The RF amplifier may include an input matching network. The RF amplifier may include an output matching network. The RF amplifier may include a semiconductor substrate. The RF amplifier may include an amplifier stage located on the semiconductor substrate and coupled between the input matching network and the output matching network, wherein the amplifier stage includes a first transistor. The first transistor may include a first drain contact communicatively coupled to the output matching network. The first transistor may include a first gate contact communicatively coupled to the input matching network. The first transistor may include a second gate contact communicatively coupled to the input matching network, wherein the first drain contact is laterally interposed on the substrate between the first gate contact and the second gate contact.

[0008] One aspect of this disclosure provides a radio frequency (RF) amplifier. The RF amplifier may include an input network having a first terminal and a second terminal. The RF amplifier may include an output network having a third terminal and a fourth terminal. The RF amplifier may include a substrate. The RF amplifier may include a first transistor located on the substrate and having a first gate terminal coupled to the first terminal, a first source-drain terminal coupled to the third terminal, and a second source-drain terminal coupled to a reference voltage. The RF amplifier may include a second transistor located on the substrate and having a second gate terminal coupled to the second terminal, a third source-drain terminal coupled to the fourth terminal, and a fourth source-drain terminal coupled to the second source-drain terminal and the reference voltage. The RF amplifier may include a third transistor located on the substrate and having a third gate terminal coupled to the first terminal and the first gate terminal, a fifth source-drain terminal coupled to the fourth terminal and the third source-drain terminal, and a sixth source-drain terminal coupled to the reference voltage. The RF amplifier may include a fourth transistor located on the substrate and having a fourth gate terminal coupled to the second terminal and the second gate terminal, a seventh source-drain terminal coupled to the third terminal and the first source-drain terminal, and an eighth source-drain terminal coupled to the reference voltage, wherein the first transistor and the second transistor are laterally interposed on the substrate between the third transistor and the fourth transistor.

[0009] One aspect of this disclosure provides an amplifier. The amplifier may include a first set of transistor cells that share a first gate node, a first source node coupled to a reference voltage, and a first drain node. The transistor cells in the first set may include a first drain contact of the first drain node extending along a longitudinal axis. The transistor cells in the first set may include a first source contact of the first source node extending parallel to the longitudinal axis at a first side of the first drain contact. The transistor cells in the first set may include a second source contact of the first source node extending parallel to the longitudinal axis at a second side of the first drain contact opposite to the first side. The transistor cells in the first set may include a first gate contact of the first gate node extending orthogonally to the longitudinal axis at a third side of the first drain contact. The transistor cells in the first set may include a second gate contact of the first gate node extending orthogonally to the longitudinal axis at a fourth side of the first drain contact opposite to the third side. The transistor units in the first set may include a first plurality of gate lines of the first gate node, the first plurality of gate lines extending parallel to the longitudinal axis and coupling the first gate contact to the second gate contact. The transistor units in the first set may include a first plurality of source lines of the first source node, the first plurality of source lines extending orthogonally to the longitudinal axis and coupling the first source contact to the second source contact. Attached Figure Description

[0010] Figure 1 These are illustrations of exemplary electronic devices with wireless circuitry according to some implementation schemes.

[0011] Figure 2 This is a diagram of an exemplary wireless circuit with a radio frequency amplifier according to some implementation schemes.

[0012] Figure 3 This is a diagram of an exemplary transmitting circuit with an RF amplifier according to some implementation schemes.

[0013] Figure 4 This is a circuit diagram of an exemplary radio frequency amplifier with a power transistor and a capacitor neutralizing transistor, according to some implementation schemes.

[0014] Figure 5 This is a top view of an exemplary transistor unit cell that can be used to form a transistor in a radio frequency amplifier, according to some implementation schemes.

[0015] Figure 6This is a cross-sectional side view of an exemplary transistor unit cell according to some implementation schemes.

[0016] Figure 7 This is a top view of an exemplary radio frequency amplifier with adjacent power transistors laterally interposed in a capacitor and between transistors, according to some implementation schemes.

[0017] Figure 8 This includes graphs showing the gain and stability factors of exemplary RF amplifiers as a function of frequency, based on some implementation schemes.

[0018] Figure 9 This includes graphs showing the load impedance and passive efficiency of exemplary RF amplifiers as a function of frequency, based on some implementation schemes.

[0019] Figure 10 This is a circuit diagram of an exemplary multistage radio frequency amplifier based on some implementation schemes.

[0020] Figure 11 This is a graph showing the scattering parameters of an exemplary multistage RF amplifier as a function of frequency, based on some implementation schemes.

[0021] Figure 12 It is a graph illustrating the additional characteristics of an exemplary multistage RF amplifier based on some implementation schemes.

[0022] Figure 13 This is a graph showing the error vector magnitude (EVM) of an exemplary RF amplifier across different frequency, process angle, and temperature conditions as a function of the output power level, based on some implementation schemes. Detailed Implementation

[0023] Figure 1 The electronic device 10 may be: a computing device, such as a laptop computer, desktop computer, computer monitor containing an embedded computer, tablet computer, cellular phone, media player, or other handheld or portable electronic device; a smaller device, such as a wristwatch, a wristband, a headset or handset, a device embedded in glasses, goggles, a helmet, or other equipment worn on a user's head (e.g., an augmented reality, virtual reality, or mixed reality head-mounted display), or another wearable or micro device; a television set, a computer monitor not containing an embedded computer, a gaming device, a navigation device, an embedded system (such as a system in which electronic equipment with a display is installed in a kiosk or a car), a voice-controlled speaker connected to the wireless Internet, a home entertainment device, a remote control device, a game controller, a peripheral user input device, a wireless base station or access point, equipment that enables the functionality of two or more of these devices; or other electronic equipment.

[0024] like Figure 1As shown in the functional block diagram, device 10 may include components located on or within an electronic device housing, such as housing 12. Housing 12 (sometimes referred to as a shell) may be formed of plastic, glass, ceramic, fiber composite material, metal (e.g., stainless steel, aluminum, metal alloys, etc.), other suitable materials, or combinations of these materials. In some embodiments, housing 12 may be partially or entirely formed of dielectric or other low-conductivity materials (e.g., glass, ceramic, plastic, sapphire, etc.). In other embodiments, housing 12, or at least some of the structures constituting housing 12, may be formed of metallic elements.

[0025] Device 10 may include control circuitry 14. Control circuitry 14 may include storage devices, such as storage device circuitry 16. Storage device circuitry 16 may include hard disk drive storage devices, non-volatile memory (e.g., flash memory configured to form a solid-state drive or other electrically programmable read-only memory), volatile memory (e.g., static random access memory or dynamic random access memory), etc. Storage device circuitry 16 may include storage devices integrated within device 10, and / or removable storage media.

[0026] Control circuitry 14 may include processing circuitry, such as processing circuitry 18. Processing circuitry 18 may be used to control the operation of device 10. Processing circuitry 18 may include one or more processors, such as a microprocessor, microcontroller, digital signal processor, host processor, baseband processor integrated circuit, application-specific integrated circuit, central processing unit (CPU), graphics processing unit (GPU), etc. Control circuitry 14 may be configured to perform operations in device 10 using hardware (e.g., dedicated hardware or circuitry), firmware, and / or software. Software code for performing operations in device 10 may be stored on storage device circuitry 16 (e.g., storage device circuitry 16 may include a non-transitory (tangible) computer-readable storage medium storing software code). This software code may sometimes be referred to as program instructions, software, data, commands, or code. The software code stored on storage device circuitry 16 may be executed by processing circuitry 18.

[0027] Control circuitry 14 can be used to run software on device 10, such as satellite navigation applications, internet browsing applications, Voice over Internet Protocol (VoIP) telephone calling applications, email applications, media playback applications, operating system functions, etc. To support interaction with external equipment, control circuitry 14 can be used to implement communication protocols. Communication protocols that can be implemented using control circuitry 14 include Internet Protocol, Wireless Local Area Network (WLAN) protocols (e.g., IEEE 802.11 protocol—sometimes referred to as Wi-Fi). ® ), such as Bluetooth ®Protocols for other short-range wireless communication links, such as protocols for wireless personal area networks (WPANs) or other wireless personal area network (WPAN) protocols, IEEE 802.11ad protocols (e.g., ultra-wideband protocols), cellular phone protocols (e.g., 3G protocols, 4G (LTE) protocols, 3GPP fifth-generation (5G) new radio (NR) protocols, sixth-generation (6G) protocols, sub-THz protocols, THz protocols, etc.), antenna diversity protocols, satellite navigation system protocols (e.g., Global Positioning System (GPS) protocols, Global Navigation Satellite System (GLONASS) protocols, etc.), satellite communication (SATCOM) protocols, antenna-based spatial ranging protocols, optical communication protocols, or any other desired communication protocols. Each communication protocol may be associated with a corresponding radio access technology (RAT), which specifies the physical connection method used to implement the protocol.

[0028] Device 10 may include input-output circuitry 20. Input-output circuitry 20 may include input-output devices 22. Input-output devices 22 may be used to allow data to be supplied to device 10 and to allow data to be provided from device 10 to external devices. Input-output devices 22 may include user interface devices, data port devices, and other input-output components. For example, input-output devices 22 may include touch sensors, displays (e.g., touch-sensitive displays and / or force-sensitive displays), light-emitting components such as displays without touch sensor capability, buttons (mechanical, capacitive, optical, etc.), scroll wheels, touchpads, keypads, keyboards, microphones, cameras, buttons, speakers, status indicators, audio jacks and other audio port components, digital data port devices, motion sensors (accelerometers, gyroscopes, and / or compasses for detecting motion), capacitive sensors, proximity sensors, magnetic sensors, force sensors (e.g., force sensors coupled to a display to detect pressure applied to the display), etc. In some configurations, keyboards, headphones, displays, pointing devices such as touchpads, mice and joysticks, and other input-output devices may be coupled to device 10 via wired or wireless connections (e.g., some of the input-output devices 22 may be peripherals coupled to the main processing unit or other parts of device 10 via wired or wireless links).

[0029] Input-output circuitry 20 may include wireless circuitry 24 to support or perform radio frequency (RF) signal transmission and / or reception of device 10. Wireless circuitry 24 may be used for wireless communication. Wireless communication performed by wireless circuitry 24 may include or involve wireless data communication (e.g., where wireless data is carried by RF signals transmitted bidirectionally or unidirectionally between wireless circuitry 24 and other communication equipment), RF signal transmission, RF signal reception, and / or radio-based spatial ranging / sensing (e.g., radio detection and ranging (radar) operation, short-range object detection such as object detection based on near-field RF signals, etc.). RF signals transmitted by wireless circuitry 24 may include or carry wireless data (e.g., organized into frames, packets, symbols, datagrams, etc.), radar or other spatial ranging waveforms, continuous wave signals, chirped signals, control signals, management signals, reference signals, beacon signals, tones, impulses, waveforms associated with one or more communication protocols, and / or any other RF waveforms or signals. Wireless circuitry 24 is sometimes referred to herein as wireless communication circuitry 24, communication circuitry 24, or simply circuitry 24. Wireless circuitry 24 may include one or more antennas. Wireless circuit 24 may also include baseband processor circuitry, transceiver circuitry, amplifier circuitry, filter circuitry, switching circuitry, radio frequency transmission lines, and / or any other circuitry for transmitting and / or receiving radio frequency signals using an antenna. Some or all of the components of wireless circuit 24 may be disposed on, mounted to, communicatively coupled to, and / or integrated within the same substrate (e.g., printed circuit board, semiconductor substrate, chip, integrated circuit (IC), IC package, etc.), or distributed between two or more substrates (e.g., printed circuit board, semiconductor substrate, chip, IC, IC package, etc.).

[0030] Wireless circuit 24 can transmit and / or receive radio frequency signals within the corresponding frequency band of a radio frequency (sometimes referred to herein as a communication band or simply a "band"). The frequency band handled by wireless circuit 24 may include: wireless local area network (WLAN) bands (e.g., Wi-Fi). ® (IEEE 802.11) or other WLAN communication bands such as the 2.4 GHz WLAN band (e.g., 2400 MHz to 2480 MHz), the 5 GHz WLAN band (e.g., 5180 MHz to 5825 MHz), Wi-Fi ® 6E band (e.g., 5925MHz to 7125MHz), Wi-Fi ® 7-band and / or other Wi-Fi ® Frequency bands (e.g., 1875MHz to 5160MHz); Wireless Personal Area Network (WPAN) frequency bands such as 2.4GHz Bluetooth. ®Frequency bands or other WPAN communication bands; cellular phone bands (e.g., bands from approximately 600 MHz to approximately 5 GHz, 3G bands, 4G LTE bands, 5G New Radio Frequency Range 1 (FR1) band below 10 GHz, 5G New Radio Frequency Range 2 (FR2) band between 20 GHz and 60 GHz, etc.); other centimeter or millimeter wave bands between 10 GHz and 100 GHz; sub-THz bands between approximately 100 GHz and 10 THz (e.g., 6G bands); near field communication (NFC) bands (e.g., 13.56 MHz); satellite navigation bands (e.g., GPS bands from 1565 MHz to 1610 MHz, Global Navigation Satellite System (GLONASS) bands, BeiDou Navigation Satellite System (BDS) bands, etc.); ultra-wideband (UWB) bands operating under the IEEE 802.15.4 protocol and / or other ultra-wideband communication protocols; satellite communication (satcom) bands (e.g., IEEE...). C-band (4GHz to 8GHz), S-band (2GHz to 4GHz), L-band (1GHz to 2GHz), X-band (8GHz to 12GHz), W-band (75GHz to 110GHz), V-band (40GHz to 75GHz), K-band (18GHz to 27GHz), K a Frequency band (26.5GHz to 40GHz), K u Frequency bands (12GHz to 18GHz, etc.); unlicensed frequency bands; communication bands under the 3GPP wireless communication standard family; communication bands under the IEEE 802.XX standard family; and / or any other desired frequency bands of interest.

[0031] Figure 2 This is a diagram showing exemplary components within wireless circuit 24. (e.g.) Figure 2 As shown, wireless circuitry 24 may include processors such as processor 26, radio frequency (RF) transceiver circuitry such as RF transceiver 28, RF front-end circuitry such as RF front-end module (FEM) 40, and antenna 42. Processor 26 may be a baseband processor, application processor, general-purpose processor, microprocessor, microcontroller, digital signal processor, host processor, dedicated signal processing hardware, or other type of processor. Processor 26 may be coupled to transceiver 28 via path 34. Transceiver 28 may be coupled to antenna 42 via RF transmission line path 36. RF front-end module 40 may be disposed on RF transmission line path 36 between transceiver 28 and antenna 42.

[0032] exist Figure 2In the example, for clarity, wireless circuit 24 is illustrated as including only a single processor 26, a single transceiver 28, a single front-end module 40, and a single antenna 42. Generally, wireless circuit 24 may include any desired number of processors 26, any desired number of transceivers 28, any desired number of front-end modules 40, and any desired number of antennas 42. Each processor 26 may be coupled to one or more transceivers 28 via a corresponding path 34. Each transceiver 28 may include transmitter circuitry 30 configured to output uplink signals to antenna 42, may include receiver circuitry 32 configured to receive downlink signals from antenna 42, and may be coupled to one or more antennas 42 via a corresponding RF transmit line path 36. Each RF transmit line path 36 may have a corresponding front-end module 40 disposed thereon. If desired, two or more front-end modules 40 may be disposed on the same RF transmit line path 36. If desired, one or more RF transmit line paths 36 in wireless circuit 24 may be implemented without any front-end modules disposed thereon.

[0033] The RF transmit line path 36 may be coupled to an antenna feed section on the antenna 42. The antenna feed section may, for example, include a positive antenna feed terminal and a ground antenna feed terminal. The RF transmit line path 36 may have a positive transmit line signal path coupled to the positive antenna feed terminal on the antenna 42. The RF transmit line path 36 may have a ground transmit line signal path coupled to the ground antenna feed terminal on the antenna 42. This example is illustrative, and in general, the antenna 42 may be fed using any desired antenna feeding scheme. If desired, the antenna 42 may have multiple antenna feed sections coupled to one or more RF transmit line paths 36.

[0034] RF transmission path 36 may include a means for communication with device 10 ( Figure 1 The transmitting lines in device 10 route the radio frequency antenna signals within the device. The transmitting lines in device 10 may include coaxial cables, microstrip transmitting lines, stripline transmitting lines, edge-coupled microstrip transmitting lines, edge-coupled stripline transmitting lines, and transmitting lines formed by combinations of these types of transmitting lines. The transmitting lines in device 10 (such as the transmitting lines in radio frequency transmitting line path 36) may be integrated into rigid and / or flexible printed circuit boards.

[0035] During wireless transmission, processor 26 can provide a transmit signal (e.g., a digital or baseband signal) to transceiver 28 via path 34. Transceiver 28 may also include circuitry for converting the transmit (baseband) signal received from processor 26. For example, transceiver circuitry 28 may include mixer circuitry for up-converting (or modulating) the transmit (baseband) signal to radio frequency before transmission via antenna 42. The processor 26 communicates with transceiver 28 in this manner. Figure 2 The examples are illustrative. Generally, transceiver 28 can communicate with a baseband processor, application processor, general-purpose processor, microcontroller, microprocessor, or one or more processors within circuit 18. Transceiver circuit 28 may also include digital-to-analog converter (DAC) circuitry and / or analog-to-digital converter (ADC) circuitry for converting signals between the digital and analog domains. Transceiver 28 can transmit radio frequency (RF) signals via transmitter (TX) 30 through RF transmission line path 36 and front-end module 40 via antenna 42. Antenna 42 can transmit the RF signal to external wireless equipment by radiating the RF signal into free space.

[0036] During wireless reception, antenna 42 can receive radio frequency (RF) signals from external wireless equipment. The received RF signals can be transmitted to transceiver 28 via RF transmission path 36 and front-end module 40. Transceiver 28 may include circuitry, such as receiver (RX) 32, for receiving signals from front-end module 40 and for converting the received RF signals into corresponding baseband signals. For example, transceiver 28 may include mixer circuitry for down-converting (or demodulating) the received RF signals to baseband frequencies before transmitting the received signals via path 34 to processor 26.

[0037] Front-end module (FEM) 40 may include radio frequency front-end circuitry that operates on radio frequency signals transmitted (transmitted and / or received) via radio frequency transmit line path 36. For example, FEM 40 may include front-end module (FEM) components such as radio frequency filter circuitry 44 (e.g., low-pass filter, high-pass filter, notch filter, band-pass filter, multiplexing circuitry, duplexer circuitry, dual-signal circuitry, triplexer circuitry, etc.), switching circuitry 46 (e.g., one or more radio frequency switches), radio frequency amplifier circuitry 48 (e.g., one or more power amplifiers 50 and / or one or more low-noise amplifier circuitry 52), signal attenuators, impedance matching circuitry (e.g., circuitry that helps match the impedance of antenna 42 with the impedance of radio frequency transmit line 36), antenna tuning circuitry (e.g., a network of capacitors, resistors, inductors, and / or switches that adjust the frequency response of antenna 42), radio frequency coupler circuitry, charge pump circuitry, power management circuitry, digital control and interface circuitry, and / or any other desired circuitry that operates on the radio frequency signals transmitted and / or received by antenna 42. Each of the front-end module components can be mounted on a common (shared) substrate, such as a rigid printed circuit board substrate or a flexible printed circuit board substrate. If desired, the various front-end module components can also be integrated into a single integrated circuit chip. If desired, amplifier circuit 48 and / or other components in front-end 40 (such as filter circuit 44) can also be implemented as part of transceiver circuit 28.

[0038] Filter circuit 44, switching circuit 46, amplifier circuit 48, and other circuits may be disposed along RF transmission line path 36, may be incorporated into FEM 40, and / or may be incorporated into antenna 42 (e.g., to support antenna tuning, to support operation in a desired frequency band, etc.). These components (sometimes referred to herein as antenna tuning components) may be adjusted (e.g., using control circuit 14) to adjust the frequency response and wireless performance of antenna 42 over time.

[0039] The transceiver 28 can be separate from the front-end module 40. For example, the transceiver 28 can be formed on another substrate such as the main logic board of device 10, a rigid printed circuit board, or a flexible printed circuit that is not part of the front-end module 40. Although for clarity, in Figure 1In the example, control circuitry 14 is shown separate from wireless circuitry 24, but wireless circuitry 24 may include processing circuitry and / or storage circuitry, the processing circuitry forming part of processing circuitry 18, and the storage circuitry forming part of storage circuitry 16 of control circuitry 14 (e.g., portions of control circuitry 14 may be implemented on wireless circuitry 24). As an example, portions of processor 26 and / or transceiver 28 (e.g., a host processor on transceiver 28) may form part of control circuitry 14. Control circuitry 14 (e.g., portions of control circuitry 14 formed on processor 26, portions of control circuitry 14 formed on transceiver 28, and / or portions of control circuitry 14 separate from wireless circuitry 24) may provide control signals (e.g., via one or more control paths in device 10) to control the operation of front-end module 40.

[0040] Transceiver 28 may include: handling WLAN communication frequency bands (e.g., Wi-Fi) ® (IEEE 802.11) or other WLAN communication bands such as the 2.4 GHz WLAN band (e.g., 2400 MHz to 2480 MHz), the 5 GHz WLAN band (e.g., 5180 MHz to 5825 MHz), Wi-Fi ® 6E band (e.g., 5925MHz to 7125MHz) and / or other Wi-Fi ® Wireless LAN transceiver circuitry covering frequency bands (e.g., 1875MHz to 5160MHz); handling 2.4GHz Bluetooth. ® Wireless personal area network transceiver circuits for frequency bands or other WPAN communication bands; cellular phone transceiver circuits handling cellular phone frequency bands (e.g., bands from approximately 600 MHz to approximately 5 GHz, 3G bands, 4G LTE bands, 5G New Radio Frequency Range 1 (FR1) band below 10 GHz, 5G New Radio Frequency Range 2 (FR2) band between 20 GHz and 60 GHz, 6G bands above 100 GHz, etc.); near field communication (NFC) transceiver circuits handling near field communication frequency bands (e.g., at 13.56 MHz); satellite navigation receiver circuits handling satellite navigation frequency bands (e.g., GPS band from 1565 MHz to 1610 MHz, Global Navigation Satellite System (GLONASS) band, BeiDou Navigation Satellite System (BDS) band, etc.); using IEEE Ultra-wideband (UWB) transceiver circuitry for handling communications using the 802.15.4 protocol and / or other ultra-wideband communication protocols; and / or any other desired radio frequency transceiver circuitry for covering any other desired communication band of interest.

[0041] Wireless circuit 24 may include one or more antennas, such as antenna 42. Antenna 42 can be formed using any desired antenna structure. For example, antenna 42 may be an antenna with a resonant element, formed from a loop antenna structure, patch antenna structure, inverted F-shaped antenna structure, slot antenna structure, planar inverted F-shaped antenna structure, helical antenna structure, monopole antenna, dipole, a combination of these designs, etc. Two or more antennas 42 may be arranged in one or more phased antenna arrays (e.g., for transmitting radio frequency signals at millimeter-wave frequencies). Parasitic elements may be included in antenna 42 to adjust antenna performance. Antenna 42 may be provided with a conductive cavity that supports the antenna resonant element of antenna 42 (e.g., antenna 42 may be a cavity-backed antenna, such as a cavity-backed slot antenna).

[0042] As described above, the front-end module 40 may include one or more power amplifiers (PAs) 50 in the transmit (uplink) path. Power amplifiers 50 (sometimes referred to as RF power amplifiers, transmit amplifiers, or amplifiers) may be configured to amplify RF signals without altering the signal shape, format, or modulation. For example, amplifiers 50 may be used to provide 10dB gain, 20dB gain, 10dB-20dB gain, less than 20dB gain, more than 20dB gain, or other suitable amounts of gain.

[0043] Figure 3 This is a diagram illustrating an exemplary transmission path 58 of wireless circuit 24. Transmission path 58 is sometimes referred to herein as transmission chain 58 or transmission circuit 58. Figure 3 As shown, wireless circuitry 24 may include processing circuitry such as one or more processors 26, digital-to-analog converter (DAC) circuitry such as DAC 54, up-conversion circuitry such as up-converter 56 (e.g., one or more mixers), radio frequency amplifier circuitry such as radio frequency amplifier 50 (e.g., power amplifier), and an antenna 42 configured to radiate the radio frequency signal output by amplifier 50. Additional components (not shown) may also be provided at different locations along the transmission path 58 if desired.

[0044] Amplifier 50 can be set Figure 2 The processor 26 may represent one or more processors, such as a baseband processor, application processor, digital signal processor, microcontroller, microprocessor, central processing unit (CPU), programmable device, combination of these circuits, and / or Figure 1One or more processors are included within circuit 18. Processor 26 may be configured to generate a digital baseband signal Dbb (e.g., a digital data bit stream at baseband). Signal Dbb is sometimes referred to as a digital signal or a transmit signal. As an example, signal Dbb generated by processor 26 may include in-phase (I) and quadrature-phase (Q) signals, radius and phase signals, vector inputs, or other digitally encoded signals.

[0045] DAC 54 converts the signal Dbb from a digital signal to an analog signal (e.g., from the digital domain to the analog domain). Upconverter 56 upconverts (modulates) the signal from baseband to radio frequency (RF). Amplifier 50 amplifies the upconverted signal to the RF signal RFSIG. Antenna 42 radiates the RF signal RFSIG. DAC 54 may be coupled between processor 26 and upconverter 56, or between upconverter 56 and amplifier 50, or, if desired, upconverter 56 and DAC 54 may be integrated into a single RF converter block (e.g., RFDAC) that performs both digital-to-analog and baseband-to-RF conversions. If desired, DAC 54, upconverter 56, and / or RF DAC may include multiple different units (e.g., DAC unit, RF DAC unit, etc.) that operate on signals transmitted via transmit path 58. The input of amplifier 50, configured to receive RF signals from upconverter 56, is also referred to herein or defined as the RF input (port) of amplifier 50. The radio frequency range can range from a few kHz to tens of THz.

[0046] Figure 4 This is a circuit diagram of amplifier 50 (e.g., in an exemplary embodiment where amplifier 50 includes a common-source amplifier). Figure 4 As shown, amplifier 50 may include input impedance matching circuitry such as input matching network 60, and may include output impedance matching circuitry such as output matching network 62. Matching networks 60 and 62 may each include one or more transformers, baluns, filters, signal couplers, coupling lines, resistive components, inductive components, capacitive components, and / or any other desired impedance matching circuitry.

[0047] Amplifier 50 may also have an amplifier core (e.g., a power amplifier core) comprising one or more amplifier stages 82 (e.g., common-source amplifier stages or elements) coupled between input matching network 60 and output matching network 62. Figure 4 In the example, for simplicity, amplifier 50 is illustrated as comprising a single amplifier stage 82 (e.g., a power amplifier stage or power transistor stage, which is sometimes referred to herein as PA stage 82 or power transistor stage 82). In general, amplifier 50 may include two or more stages coupled between an input matching network and an output matching network.

[0048] Amplifier stage 82 may include a pair of power transistors 72, such as a first power transistor 72A and a second power transistor 72B. If desired, amplifier stage 82 may also include a pair of capacitor neutralizing transistors 76 for the power transistors 72, such as a first capacitor neutralizing transistor 76A and a second capacitor neutralizing transistor 76B. As an example, power transistors 72A and 72B, as well as capacitor neutralizing transistors 76A and 76B, may be n-channel metal-oxide-semiconductor (NMOS) transistors. More generally, transistors 72A, 72B, 76A, and 76B may include p-channel metal-oxide-semiconductor (PMOS) transistors, NMOS transistors, and / or other types of transistors.

[0049] The input matching network 60 may have an input port that is communicatively coupled to the up-converter 56. Figure 3 The input matching network 60 may have an output port 66, which is sometimes referred to herein as the input port 66 of the amplifier stage within amplifier 50. The output port 66 of the input matching network 60 may be, for example, a differential signal port comprising a first (positive) terminal 66P and a second (negative) terminal 66N (sometimes referred herein as the output terminal of the input matching network 60 or the input terminal of the amplifier stage of amplifier 50). During signal transmission, the input matching network 60 may receive signals from the upconverter 56 ( Figure 3 It receives radio frequency (RF) signals and can output the RF signals at the output port 66 of the input matching network. The RF signal output by the input matching network 60 can be represented, for example, by the input voltage VIN between input terminals 66P and 66N.

[0050] The output matching network 62 may have an output port that is communicatively coupled to the antenna 42. Figure 3 The output matching network 62 can output the radio frequency signal RFSIG at its output port. Figure 3 The output matching network 62 may also have an input port 68, which is sometimes referred to herein as the output port 68 of the amplifier stage within amplifier 50. The input port 68 of the output matching network 62 may be, for example, a differential signal port comprising a first (positive) terminal 68P and a second (negative) terminal 68N (sometimes referred herein as the input terminal of the output matching network 62 or the output terminal of the amplifier stage of amplifier 50). During signal transmission, the amplifier stage of amplifier 50 (e.g., at least amplifier stage 82) may amplify the radio frequency signal transmitted through input port 66 (e.g., at input voltage VIN) to generate a corresponding amplified output voltage VOUT between terminals 68N and 68P. The output matching network 62 may transmit the output voltage VOUT as... Figure 3The radio frequency signal RFSIG.

[0051] A power transistor 72A of amplifier stage 82 may be coupled between terminal 66P of input matching network 60 and terminal 68N of output matching network 60. A power transistor 72B of amplifier stage 82 may be coupled between terminal 66N of input matching network 60 and terminal 68P of output matching network 60. When referring to the current-conducting terminals or nodes of a metal-oxide-semiconductor (MOS) transistor, the terms "source" and "drain" are sometimes used interchangeably. Thus, the source terminal or node and the drain terminal or node of a MOS transistor are sometimes referred to as "source-drain" terminals or "source-drain" nodes (e.g., a transistor having a gate terminal or node, a first source-drain terminal or node, and a second source-drain terminal or node). The source, drain, and gate terminals of a transistor may also sometimes be referred to interchangeably herein as the source, drain, and gate nodes of a transistor, or more simply as the source, drain, and gate of a transistor.

[0052] Power transistor 72A may have a first source-drain node (e.g., a drain node) coupled to terminal 68N of output matching network 62, and may have a second source-drain node (e.g., a source node) coupled to reference voltage 64. Reference voltage 64 may be ground voltage VSS or another reference potential. Power transistor 72B may have a first source-drain node (e.g., a drain node) coupled to terminal 68P of output matching network 62, and may have a second source-drain node (e.g., a source node) coupled to reference voltage 64. In other words, the second source-drain nodes (e.g., source nodes) of power transistors 72A and 72B may both be coupled to the same circuit node 74 (sometimes referred to herein as reference node 74), and circuit node 74 may be coupled to reference potential 64 (e.g., the source terminals of both power transistors 72A and 72B may be coupled together and coupled to reference voltage 64, thereby configuring power transistors 72A and 72B to form a pair of common-source transistors).

[0053] The gate terminal of power transistor 72A is coupled to terminal 66P of input matching network 60 via signal line 80A. The gate terminal of power transistor 72B is coupled to terminal 66N of input matching network 60 via signal line 80N. Signal lines 80A and 80B are sometimes referred to herein as signal conductors 80A / 80B, input signal lines 80A / 80B, input signal conductors 80A / 80B, input paths 80A / 80B, or signal paths 80A / 80B. During signal transmission, the voltage applied to the gate terminals of power transistors 72A and 72B is given by the input voltage VIN transmitted via terminals 66P and 66N. When the magnitude of the voltage supplied to the gate terminals of power transistors 72A and 72B changes, the amount of current flowing between the source and drain terminals of power transistors 72A and 72B changes, thereby generating a corresponding output voltage VOUT between terminals 68N and 68P of output matching network 62.

[0054] Capacitor neutralizing transistors 76A and 76B may be cross-coupled around power transistors 72A and 72B and may be configured to neutralize the feedback effect (e.g., Miller effect) of the gate-to-drain capacitance Cgd in power transistors 72A and 72B. Capacitor neutralizing transistor 76A may have a gate node coupled to the gate node of power transistor 72A and signal line 80A (e.g., signal line 80A, the gate node of power transistor 72A, and the gate node of capacitor neutralizing transistor 76A may all be coupled to a shared circuit node). The first source-drain node (e.g., drain node) of capacitor neutralizing transistor 76A may be coupled via conductive line 84A to the first source-drain node (e.g., drain node) of power transistor 72B and terminal 68P of output matching network 62 (e.g., conductive line 84A, the drain node of power transistor 72B, and terminal 68P of output matching network 62 may all be coupled to the same shared circuit node 70B).

[0055] Similarly, the capacitor neutralizing transistor 76B may have a gate node coupled to the gate node of the power transistor 72B and the signal line 80B (e.g., the signal line 80B, the gate node of the power transistor 72B, and the gate node of the capacitor neutralizing transistor 76B may all be coupled to a shared circuit node). The first source-drain node (e.g., the drain node) of the capacitor neutralizing transistor 76B may be coupled via a conductive line 84B to the first source-drain node (e.g., the drain node) of the power transistor 72A and the terminal 68N of the output matching network 62 (e.g., the conductive line 84B, the drain node of the power transistor 72A, and the terminal 68N of the output matching network 62 may all be coupled to the same shared circuit node 70A). When coupled to the power transistors 72A and 72B in this manner, the capacitor neutralizing transistors 76A and 76B can neutralize the Miller effect, thereby helping to increase the power gain, reverse isolation, and stability of the amplifier 50 over a relatively wide bandwidth. This specific implementation is illustrative and not limiting, and capacitor neutralizing transistors 76A and 76B may be omitted from amplifier 50 if desired. Other implementations of capacitor neutralizing transistors 76A and 76B are possible, and / or amplifier 50 may be implemented using other amplifier architectures. In some implementations, for example, resistors 78A and 78B may be omitted. In these implementations, if desired, both the source and drain nodes of capacitor neutralizing transistor 76A may be coupled to circuit node 70B, and both the source and drain nodes of capacitor neutralizing transistor 76B may be coupled to circuit node 70A. Amplifier 50 is implemented as a common-source amplifier. Figure 4 The examples are illustrative and not limiting. Amplifier 50 does not need to be implemented as a common-source amplifier, and other amplifier topologies can be used if desired. For example, amplifier 50 may be implemented as a common-source cascode amplifier (e.g., having a common-gate stage fed by a common-source stage, wherein the common-source stage includes...). Figure 4 The stage 82 can be implemented using a stacked topology, and / or any desired amplifier topology with common source elements or stages (e.g., with...). Figure 4 This is achieved using power transistors 72A and 72B, and optional capacitor neutralization transistors 76A and 76B.

[0056] In implementation, it may be desirable to transmit RFSIG signals at frequencies within the D-band spectrum, as this spectrum potentially addresses the demands for extreme data rates and its diverse application range across various industries. Nanoscale complementary metal-oxide-semiconductor (CMOS) technology facilitates low-cost, high-volume production and integration with high-speed baseband and digital signal processor (DSP) circuitry. Designing satisfactory amplifiers for these frequencies using certain process technologies, such as FinFETs, can be challenging. This is because RF performance can degrade due to increased device and interconnect parasitic effects. This effect can become more pronounced due to long interconnect lengths, as large transistor widths may be required to deliver RF power. Furthermore, designing satisfactory output matching networks for D-band amplifiers utilizing FinFET technology can be difficult. This is because the inductance required to resonate the device capacitance decreases rapidly with increasing capacitance and frequency. Further reduction in inductance can lead to decreased coupling coefficients and degraded insertion losses.

[0057] Device and interconnect parasitic effects are two major reasons why amplifier 50's gain, output power, and / or efficiency can be reduced at relatively high frequencies. This is particularly true at D-band frequencies (e.g., approximately 110 GHz to approximately 170 GHz), where the operating frequency is close to a significant portion of the transistor cutoff frequencies in the amplifier (e.g., FT / FMAX). Device parasitic effects represent a large portion of the total impedance at each node, which can significantly degrade RF performance. Layout design becomes crucial for minimizing parasitic effects in each transistor, especially gate resistance, source resistance / inductance, and gate-to-drain capacitance. Meanwhile, large power cell sizes can introduce long interconnects around the transistors. The associated parasitic resistances and inductances, especially in the source network (which do not scale down with technology size or even worsen), can substantially degrade the transistors and thus limit the power gain and output power of amplifier 50. Therefore, it is also desirable to minimize degradation due to interconnect lengths during layout optimization.

[0058] Device and interconnect parasitic effects in amplifier 50 may include, for example, the parasitic gate resistance R between the gate node of each of transistors 76A and 72A and terminal 66P. g The parasitic gate resistance R between the gate node of each of transistors 76B and 72B and terminal 66N. g The parasitic source resistance R between the source node of each of the power transistors 72A / 72B and the reference voltage 64 s and the parasitic source inductance L between the source node of each of the power transistors 72A / 72B and the reference voltage 64. sDue to degradation effects, the parasitic source resistance R s Parasitic source inductance L s Both can significantly reduce the power gain of amplifier 50 (e.g., for parasitic source resistance R). s The resistance or parasitic source inductance L of each 1 ohm s For every 1 pH of inductance, the gain can decrease by 0.8 dB or more. Furthermore, for the parasitic gate resistance R... g The parasitic gate resistance R for each 1 ohm of resistance. g This can reduce the gain of amplifier 50 by up to 0.6 dB or more. To help minimize these device and interconnect parasitic effects, as described below, amplifier 50 can be implemented using dual-gate connections at both the transistor unit level and the amplifier stage level, and can have a common-mode differential-mode decoupling source network at the amplifier stage level.

[0059] Figure 5 This is a top (layout) view of an exemplary transistor unit cell 90 that can be implemented in amplifier 50. Transistor unit cells (such as...) Figure 5 The transistor unit 90 may, for example, be used to form one or more of transistors 76A, 72A, 72B, and 76B in amplifier stage 82. Individual transistors in amplifier stage 82 (e.g., transistors 76A, 72A, 72B, or 76B) may include... Figure 5 A collection of one or more transistor unit cells 90 coupled together (e.g., a row or column of transistor unit cells having gate nodes coupled together to effectively form a gate node of a transistor, source nodes coupled together to effectively form a source node of a transistor, and / or drain nodes coupled together to effectively form a drain node of a transistor).

[0060] like Figure 5 As shown, transistor unit cell 90 (sometimes referred to herein as transistor cell 90) may be fabricated on and / or within a corresponding substrate 92 (e.g., a semiconductor substrate such as an integrated circuit wafer, chip, or die). In a specific implementation of fabricating the corresponding transistor using finFET process technology, transistor unit cell 90 may, for example, form part of a finFET.

[0061] The transistor unit cell 90 may include a drain node D (e.g., forming some or all of the drain nodes or terminals of the corresponding transistor), a gate node G (e.g., forming some or all of the gate nodes or terminals of the corresponding transistor), and a source node S (e.g., forming some or all of the source nodes or terminals of the corresponding transistor). The gate node G may be formed by a first set of one or more interconnect conductors (e.g., conductive traces in one or more metallization layers of the substrate 92 and / or one or more conductive vias extending vertically parallel to the Z-axis through the substrate 92). The source node S may be formed by a second set of one or more interconnect conductors (e.g., conductive traces in one or more metallization layers of the substrate 92, and / or one or more conductive vias). The drain node D may be formed by a third set of one or more interconnect conductors (e.g., conductive traces in one or more metallization layers of the substrate 92 and / or one or more conductive vias extending vertically through the substrate 92).

[0062] Drain node D may include an elongated drain contact 102. The drain contact 102 is sometimes also referred to herein as a drain conductor 102 or a drain connector 102. The drain contact 102 may be formed from a continuous and elongated conductor or conductive trace in a corresponding metallization layer of the substrate 92. The drain contact 102 may have a length parallel to... Figure 5 The drain contact 102 is an elongated shape extending along the linear longitudinal axis of the X-axis. It may, for example, have a rectangular shape having a first edge, a second edge, a third edge, and a fourth edge. The first and second edges are orthogonal to the longitudinal axis (e.g., parallel to the X-axis). Figure 5 The third and fourth edges extend parallel to the first and second edges (e.g., parallel to the longitudinal axis of the drain contact 102 and parallel to the Y-axis). Figure 5 The X-axis extends (orthogonal to the first and second edges). The third and fourth edges are longer than the first and second edges (e.g., the drain contacts are configured to present an elongated linear or rectangular shape).

[0063] The drain contact 102 can be electrically / communically coupled or connected to other components in the amplifier 50. For example, when Figure 5 The transistor unit cell 90 in Figure 4 When implemented in the capacitor neutralization transistor 76A, the drain contact 102 can be coupled to circuit node 70B, the drain node of power transistor 72B, and terminal 68P. When Figure 5 The transistor unit cell 90 in Figure 4 When implemented in the capacitor neutralization transistor 76B, the drain contact 102 can be coupled to circuit node 70A, the drain node of power transistor 72A, and terminal 68N. When Figure 5 The transistor unit cell 90 in Figure 4When implemented in power transistor 72A, drain contact 102 can be coupled to circuit node 70A, capacitor neutralization, the drain node of transistor 76B, and terminal 68N. Figure 5 The transistor unit cell 90 in Figure 4 When implemented in the power transistor 72B, the drain contact 102 can be coupled to circuit node 70B, capacitor neutralization transistor 76A's drain node and terminal 68P.

[0064] The source node S may include a first elongated source contact 94 and a second elongated source contact 94. The source contact 94 is sometimes also referred to herein as a source conductor 94 or a source connector 94. Each source contact 94 may be formed from a corresponding continuous and elongated conductor or conductive trace in a corresponding metallization layer of the substrate 92 (e.g., different from the metallization layer used to form the drain contact 102). Each source contact 94 may have a trace parallel to... Figure 5 The source contact 94 has an elongated shape extending along a linear longitudinal axis of the X-axis. The longitudinal axis of each source contact 94 may extend parallel to the longitudinal axis of the drain contact 102. A first source contact 94 may be laterally facing the third edge of the drain contact 102 and may extend along, facing, and parallel to the third edge of the drain contact 102. A second source contact 94 may be laterally facing the fourth edge of the drain contact 102 and may extend along, facing, and parallel to the fourth edge of the drain contact 102 (e.g., each source contact 94 is elongated and extends parallel to the drain contact 102). Each source contact 94 may, for example, have a first edge and a second edge extending parallel to the Y-axis and the first and second edges of the drain contact 102, and may have a third edge and a fourth edge extending from the first edge to the second edge parallel to the X-axis and the third and fourth edges of the drain contact 102. The third and fourth edges of each source contact 94 are longer than the first and second edges of the source contact 94 (e.g., each source contact 94 is configured to have an elongated shape parallel to the X-axis). If desired, each source contact 94 may be longer than the drain contact 102 (e.g., parallel to the X-axis).

[0065] The source node S may also include a collection of source lines 96 extending from the first source contact 94 to the second source contact 94. The source lines 96 may extend along a parallel longitudinal axis orthogonal to the longitudinal axis of the source contact 94. The source lines 96 may include conductors and / or conductive traces in one or more metallization layers of the substrate 92, and / or may include conductive vias extending through the substrate 92. Each source line 96 may electrically couple the first source contact 94 to the second source contact 94 (e.g., at a corresponding location along the length of the source contact). This allows the source contacts 94 and source lines 96 to be configured together to form a single electrically continuous source node S of the transistor unit cell 90. Each source line 96 may extend parallel to the Y-axis and orthogonal to the source contact 94 and drain contact 102. The source lines 96 are sometimes also referred to as source conductors 96 or fingers 96. Each source contact 94 may be wider than each source line 96 (e.g., measured orthogonally to the longitudinal axis of the source contact) (e.g., each source contact 94 may be formed by a wide metal trace on the substrate 92). The drain contact 102 may overlap with at least some of the source lines 96 of the source node S (e.g., as viewed in the -Z direction). The drain contact 102 may not overlap with respect to the first source contact and the second source contact 94.

[0066] The two source contacts 94 can be electrically / communically coupled or connected to other components in amplifier 50. For example, when Figure 5 The transistor unit cell 90 in Figure 4 When implemented in the capacitor neutralization transistor 76A, the source contact 94 can be coupled to the reference voltage 64 via resistor 78A. Figure 5 The transistor unit cell 90 in Figure 4 When implemented in the capacitor neutralization transistor 76B, the source contact 94 can be coupled to the reference voltage 64 via resistor 78B. Figure 5 The transistor unit cell 90 in Figure 4 When implemented in power transistor 72A, source contact 94 can be coupled to circuit reference voltage 64 and source node of power transistor 72B (e.g., in...). Figure 4 (Circuit node 74). When Figure 5 The transistor unit cell 90 in Figure 4 When implemented in power transistor 72B, source contact 94 can be coupled to circuit reference voltage 64 and source node of power transistor 72A (e.g., in...). Figure 4 (Circuit node 74).

[0067] In some specific implementations, the gate node G of the transistor unit cell 90 includes a single gate contact only on one side of the transistor unit cell (e.g., only at the first edge facing the source contact 94 and the drain contact 102). To reduce the effective gate resistance of the transistor unit cell 90 (e.g., by a factor of 4 or greater), the gate node G of the transistor unit cell 90 may include a pair of gate contacts 98 on both sides of the transistor unit cell. For example, as... Figure 5 As shown, the gate node G may include a first gate contact 98 and a second gate contact 98 on opposite sides of the drain contact 102. The first gate contact 98 may face a first edge of the drain contact 102. The second gate contact 98 may face a second edge of the gate contact 98. The drain contact 102 may be laterally inserted between the first gate contact and the second gate contact 98. If desired, the gate contact 98 may extend along a corresponding parallel longitudinal axis. The longitudinal axis of the gate contact 98 may extend orthogonally to the longitudinal axis of the source contact 94, orthogonally to the longitudinal axis of the drain contact 102, parallel to the longitudinal axis of the source line 96, and parallel to the Y-axis. The gate terminal may have a length along its longitudinal axis that is less than the lengths of the source contact 94 and the drain contact 102. Each gate contact 98 may have a length (e.g., measured parallel to the Y-axis) greater than the width of the drain contact 102 (e.g., measured parallel to the Y-axis).

[0068] Each gate contact 98 may be formed from a corresponding continuous and elongated conductor or conductive trace in a corresponding metallization layer of the substrate 92. If desired, the gate contact 98 may be formed from the same metallization layer as the drain contact 102. The gate node G may also include a collection of two or more gate lines 100 extending from the first gate contact 98 to the second gate contact 98. Each gate line 100 may include a conductor or conductive trace in one or more metallization layers of the substrate 92 and / or one or more conductive vias extending through the substrate 92. If desired, the gate line 100 may overlap with the source line 96 but not with the drain contact 102 (e.g., when viewed in the -Z direction, the gate line 100 may not overlap relative to the drain contact 102). Each gate line 100 may extend along a corresponding longitudinal axis parallel to the longitudinal axes of the source contact 94 and the drain contact 102 and orthogonal to the longitudinal axes of the gate contact 98 and the source line 96. Each gate line 100 can electrically couple a first gate contact 98 to a second gate contact 98, thereby configuring the gate contact 98 and the gate line 100 to jointly form a single electrically continuous gate node G of a transistor unit cell 90 (e.g., an annular gate node laterally surrounding the drain contact 102 when viewed in the -Z direction).

[0069] The first source contact and the second source contact 94 of the transistor unit 90 can both be electrically / communically coupled or connected to other components in the amplifier 50. For example, when Figure 5 The transistor unit cell 90 in Figure 4 When implemented in the capacitor neutralization transistor 76A, the source contact 94 can be coupled to the reference voltage 64 via resistor 78A. Figure 5 The transistor unit cell 90 in Figure 4 When implemented in the capacitor neutralization transistor 76B, the source contact 94 can be coupled to the reference voltage 64 via resistor 78B. Figure 5 The transistor unit cell 90 in Figure 4 When implemented in power transistor 72A, source contact 94 can be coupled to circuit reference voltage 64 and source node of power transistor 72B (e.g., in...). Figure 4 (Circuit node 74). When Figure 5 The transistor unit cell 90 in Figure 4 When implemented in power transistor 72B, source contact 94 can be coupled to circuit reference voltage 64 and source node of power transistor 72A (e.g., in...). Figure 4 (Circuit node 74).

[0070] Figure 6 This is a cross-sectional side view of transistor unit cell 90 (e.g., along...). Figure 5 (Observe line AA'). Figure 6 As shown, the first gate contact 98, drain contact 102, and second gate contact 98 of the transistor unit cell 90 may be formed from a metallization layer MA in the substrate 92 (e.g., the top or uppermost metallization layer of the substrate 92). The drain terminal 102 may be laterally interposed between the first gate contact 98 and the second gate contact 98 (e.g., the gate contact 98 may face the opposite side or edge of the drain contact 102). The gate node G may also include a collection of conductive vias 108 extending downward from the gate terminal 98 through the substrate 92 to a substrate portion 104 (e.g., a semiconductor body region of the substrate 92). The substrate portion 104 may include a transistor device 106 for the transistor unit cell 90. The transistor device 106 may, for example, include one or more doped semiconductor regions of the substrate portion 104 and may form a channel for the transistor unit cell 90 and / or containing a corresponding transistor of the transistor unit cell 90. The transistor device 106 is sometimes also referred to herein as oxide diffusion (OD) region 106, channel 106, or simply device 106.

[0071] The conductive via 108 of the gate node G can electrically couple the first gate terminal and the second gate terminal 98 to the gate line 100 of the gate node G. The gate line 100 can be formed from an assembly of one or more metallization layers MC of the substrate 92. If desired, the gate line 100 may also include one or more conductive vias electrically coupling multiple metallization layers MC together. Figure 6 As shown, gate line 100 may extend laterally from a first gate contact 98 of transistor unit cell 90 to a second gate contact 98. A first end of gate line 100 may be coupled to a first set of conductive vias 108, which in turn is coupled to the first gate contact 98. A second end of gate line 100 opposite to the first end may be coupled to a second set of conductive vias 108, which in turn is coupled to the second gate contact 98 (e.g., gate line 100 may extend from the first set of conductive vias 108 to the second set of conductive vias 108).

[0072] Drain node D may also include a collection of conductive vias 110 extending downward from drain contact 102 through substrate 92 to device 106. The conductive vias 110 may, for example, electrically couple drain contact 102 to device 106 (e.g., the conductive vias 110 may extend through one or more openings between gate lines 100 to reach device 106). Gate lines 100 may overlap with device 106. Drain contact 102 may overlap with device 106. If desired, drain contact 102 may not overlap with gate line 110 (see example...). Figure 5 (Top view).

[0073] Source node S (e.g., Figure 5 The source line 96 and / or source contact 94 may be formed from an assembly of one or more metallization layers MB in the substrate 92. If desired, the source node S may also include traces in one or more metallization layers MC (e.g., because the horizontal line of the source node S does not overlap with the horizontal line of the gate node G). If desired, the source node S may include coupling different metallization layers MB together and / or coupling them to device 106 (e.g., in…). Figure 5 The conductive via in the source line 96 and / or source contact 94. The source contact 94 ( Figure 6 Implementing this as a wide metal trace and / or multiple metallization layers MB across substrate 92 can help minimize the impedance of the source node S, which can also help reduce the IR drop in the transistor's ground plane.

[0074] A metallization layer MB can be vertically inserted in substrate 92 between metallization layers MC and 98. Metallization layer MC can be vertically inserted between metallization layer MB and device 106. When implementing transistor unit cell 90 in amplifier stage 82, placing drain contact 102 on top of transistor unit cell 90 helps simplify wiring. At least some source nodes S (e.g., in the vertical direction along the Z-axis) exist between drain contact 102 and gate line 100 (e.g., between drain contact 102 and gate line 100). Figure 5 The source line 96 allows the source node S to at least partially shield the gate line 100 from the drain contact 102. This helps reduce the external gate-to-drain capacitance Cgd of the transistor unit cell 90, which reduces potential performance degradation due to the Miller effect.

[0075] When implemented in this manner, the transistor unit cell 90 includes a pair of gate contacts 98 located on opposite sides of the drain contact 102, instead of a single gate contact 98 located on one side of the drain contact 102. This allows for a factor-four reduction in the effective gate resistance of the transistor unit cell. If desired, the gate polysilicon layer and metallization layers (e.g., M1 and M2 layers) can be connected together (e.g., forming gate line 100) extending to both ends of the layout and connecting to the top metallization layer of the substrate 92 (e.g., connecting to the first and second gate terminals 98 in the metallization layer MA). Compared to a specific implementation where the unit cell includes only a single gate contact / connector, this dual-sided gate connection can, for example, reduce the total gate resistance of the transistor unit cell 90 by approximately 40%.

[0076] Transistor unit cell (such as Figure 4 and Figure 5 The transistor unit 90 can be used to form Figure 4 Some or all of the transistors in the amplifier stage 82. Figure 7 This is a top (layout) view of a specific implementation of an amplifier stage 82 in which each of the transistors 76A, 72A, 72B, and 76B comprises a corresponding set (column) of five transistor unit cells 90. This is illustrative and not limiting. In general, each transistor may include any desired number of one or more transistor unit cells 90, which are coupled together to perform the operation of the corresponding transistor.

[0077] like Figure 7As shown, the capacitor neutralizing transistor 76A of amplifier stage 82 may include a first set (column) of five transistor unit cells 90. The first gate contact and second gate contact 98 of each transistor unit cell 90 in capacitor neutralizing transistor 76A may be coupled together via gate lines 100 in those transistor unit cells 90 (e.g., commonly and electrically forming the gate node / terminal of capacitor neutralizing transistor 76A). The first gate contact and second gate contact 98 in each transistor unit cell 90 of capacitor neutralizing transistor 76A may all be coupled to a shared node 113A, which may be coupled to... Figure 4 The signal line 80A. Because each transistor unit cell 90 has two opposing gate contacts 98, the voltage applied at the shared node 113A (e.g., from...) Figure 3 The input voltage VIN is concurrently applied to the two gate contacts 98 of each transistor unit 90 in the capacitor neutralizing transistor 76A, which reduces the effective gate resistance of the capacitor neutralizing transistor 76A compared to an implementation in which each transistor unit 90 includes a single gate contact 98 only on one side of the drain contact 102.

[0078] The drain contacts 102 of each transistor unit 90 of the capacitor neutralizing transistor 76A may be coupled together (e.g., commonly and electrically forming the drain node / terminal of the capacitor neutralizing transistor 76A). Each transistor unit 90 of the capacitor neutralizing transistor 76A may include a first source contact and a second source contact 94 extending parallel to the gate line 100 in that transistor unit. The source contacts 94 and source lines 96 in each transistor unit 90 of the capacitor neutralizing transistor 76A may be electrically coupled together (e.g., commonly and electrically forming the source node / terminal of the capacitor neutralizing transistor 76A). For example, the first source contact and the second source contact 94 in each transistor unit 90 of the capacitor neutralizing transistor 76A may each be coupled to a large resistor (e.g., Figure 4 The resistor is 78A. In this specific implementation, different metallization layers MB ( Figure 6 This can be used to implement the source contacts of capacitor neutralizing transistors and power transistors. For example, the metallization layer MB in capacitor neutralizing transistors 76A and 76B may consist of only a single underlying metallization layer, while the metallization layer MB in power transistors 72A and 72B may include parallel additional layers for reducing parasitic resistance and inductance. If desired, the peripheral conductor 115 (e.g., kept in...) Figure 4 The conductor of the reference voltage 64 may be transversely wrapped around some or all of the sides of the amplifier stage 82.

[0079] Similarly, the capacitor neutralizing transistor 76B of amplifier stage 82 may include a second set (column) of five transistor unit cells 90. The first gate contact and second gate contact 98 of each transistor unit cell 90 of capacitor neutralizing transistor 76B may be coupled together via gate lines 100 in those transistor unit cells 90 (e.g., collectively and electrically forming the gate node / terminal of capacitor neutralizing transistor 76B). The first gate contact and second gate contact 98 in each transistor unit cell 90 of capacitor neutralizing transistor 76B may all be coupled to a shared node 113B, which may be coupled to... Figure 4 The signal line 80B. Because each transistor unit cell 90 has two opposing gate contacts 98, the voltage applied at the shared node 113B (e.g., from...) Figure 3 The input voltage VIN is concurrently applied to the two gate contacts 98 of each transistor unit 90 in the capacitor neutralizing transistor 76B, which reduces the effective gate resistance of the capacitor neutralizing transistor 76B compared to an implementation in which each transistor unit 90 includes a single gate contact 98 only on one side of the drain contact 102.

[0080] The drain contacts 102 of each transistor unit 90 of the capacitor neutralizing transistor 76B may be coupled together (e.g., commonly and electrically forming the drain node / terminal of the capacitor neutralizing transistor 76B). Each transistor unit 90 of the capacitor neutralizing transistor 76B may include a first source contact and a second source contact 94 extending parallel to the gate line 100 in that transistor unit. The source contacts 94 and source lines 96 in each transistor unit 90 of the capacitor neutralizing transistor 76B may be electrically coupled together (e.g., commonly and electrically forming the source node / terminal of the capacitor neutralizing transistor 76B). For example, the first source contact and the second source contact 94 in each transistor unit 90 of the capacitor neutralizing transistor 76B may each be coupled to a large resistor (e.g., Figure 4 (Resistor 78B).

[0081] The power transistor 72A of amplifier stage 82 may include a third set (column) of five transistor unit cells 90. The first gate contact and second gate contact 98 of each transistor unit cell 90 of power transistor 72A can be coupled together via gate lines 100 in those transistor unit cells 90 (e.g., commonly and electrically forming the gate node / terminal of power transistor 72A). The first gate contact and second gate contact 98 in each transistor unit cell 90 of power transistor 72A can all be coupled to a shared node 113A (e.g., electrically coupling the gate of power transistor 72A to the gate of capacitor and transistor 76A). Because each transistor unit cell 90 has two opposing gate contacts 98, the voltage applied at the shared node 113A (e.g., from...) Figure 3 The input voltage VIN is concurrently applied to the two gate contacts 98 of each transistor unit 90 in power transistor 72A (and capacitor neutralizing transistor 76A), which reduces the effective gate resistance of power transistor 72A compared to an implementation in which each transistor unit 90 includes a single gate contact 98 only on one side of drain contact 102.

[0082] The drain contacts 102 of each transistor unit 90 of the power transistor 72A may be coupled together (e.g., collectively and electrically forming the drain node / terminal of the power transistor 72A). Each transistor unit 90 in the power transistor 72A may include a first source contact and a second source contact 94 extending parallel to the gate line 100 in that transistor unit. The source contacts 94 and source lines 96 in each transistor unit 90 of the power transistor 72A may be electrically coupled together (e.g., collectively and electrically forming the source node / terminal of the power transistor 72A).

[0083] The drain of power transistor 72A (e.g., including the drain terminal 102 from each transistor unit cell 90 in power transistor 72A) can be coupled to the drain of capacitor neutralization transistor 76B (e.g., including the drain terminal 102 from each transistor unit cell 90 in capacitor neutralization transistor 76B) via conductive line 84B. Conductive line 84B can extend, for example, from a first end coupled to the drain of power transistor 72A to a opposite second end coupled to the drain of capacitor neutralization transistor 76B (e.g., in...). Figure 4 (at node 70B). The conductive line 84B may be formed, for example, by a conductive trace in an additional metallization layer of the substrate (e.g., overlapping with or below the metallization layer that forms the drain contact 102 and the gate contact 98).

[0084] The power transistor 72B of amplifier stage 82 may include a fourth set (column) of five transistor unit cells 90. The first gate contact and second gate contact 98 of each transistor unit cell 90 of power transistor 72B can be coupled together via gate lines 100 in those transistor unit cells 90 (e.g., commonly and electrically forming the gate node / terminal of power transistor 72B). The first gate contact and second gate contact 98 in each transistor unit cell 90 of power transistor 72B can all be coupled to a shared node 113B (e.g., electrically coupling the gate of power transistor 72B to the gate of capacitor and transistor 76B). Because each transistor unit cell 90 has two opposing gate contacts 98, the voltage applied at the shared node 113B (e.g., from...) Figure 3 The input voltage VIN is concurrently applied to the two gate contacts 98 of each transistor unit 90 in the power transistor 72B (and the capacitor neutralizing transistor 76B), which reduces the effective gate resistance of the power transistor 72B compared to an implementation in which each transistor unit 90 includes a single gate contact 98 only on one side of the drain contact 102.

[0085] The drain contacts 102 of each transistor unit 90 of power transistor 72B may be coupled together (e.g., commonly and electrically forming the drain node / terminal of power transistor 72B). Each transistor unit 90 in power transistor 72B may include a first source contact and a second source contact 94 extending parallel to the gate line 100 in that transistor unit. The source contacts 94 and source lines 96 in each transistor unit 90 of power transistor 72B may be electrically coupled together (e.g., commonly and electrically forming the source node / terminal of power transistor 72B). Power transistors 72A and 72B may share a common source potential (e.g., Figure 4 The reference potential 64 in the capacitor can be coupled to the source contact S of both power transistors 72A and 72B, while the capacitor neutralizing transistors 76A and 76B are connected to corresponding large resistors (e.g., respectively). Figure 4 Resistors 78A and 78B each have their own source potential. The source contacts S of power transistors 72A and 72B can be connected to the peripheral conductor 115, but not to the capacitor neutralizing the source contacts S of transistors 76A and 76B.

[0086] The drain of power transistor 72B (e.g., including the drain terminal 102 from each transistor unit cell 90 in power transistor 72B) can be coupled to the drain of capacitor neutralization transistor 76A (e.g., including the drain terminal 102 from each transistor unit cell 90 in capacitor neutralization transistor 76A) via conductive line 84A. Conductive line 84A can extend, for example, from a first end coupled to the drain of power transistor 72B to a opposite second end coupled to the drain of capacitor neutralization transistor 76A (e.g., in...). Figure 4 At node 70A). Conductive line 84A may be formed, for example, by conductive traces in an additional metallization layer of the substrate (e.g., overlapping with or below the metallization layer forming drain contact 102 and gate contact 98). The drain of power transistor 72A may be coupled to terminal 68N of output matching network 62. Figure 4 This is also used to electrically couple the drain of capacitor neutralizing transistor 76B to terminal 68N via conductive line 84B. The drain of power transistor 72B can be coupled to terminal 68P of output matching network 62. Figure 4 This is also used to electrically couple the drain of capacitor neutralizing transistor 76A to terminal 68P via conductive line 84A.

[0087] When implemented in this manner, power transistors 72A and 72B can be laterally interposed on substrate 92 between capacitor neutralization transistors 76A and 76B (e.g., power transistor 72A can be laterally interposed between power transistor 72B and capacitor neutralization transistor 76A, while power transistor 72B can be laterally interposed between power transistor 72A and capacitor neutralization transistor 76B). This minimizes the wiring / interconnect path length between the source nodes of power transistors 72A and 72B, while also minimizing the area footprint of amplifier stage 82. During signal transmission, the signal travels laterally within each transistor unit cell 90, which is coupled together in corresponding columns to boost the output power of amplifier stage 82. Compared to a specific implementation in which each transistor unit 90 includes a single gate contact 98 on only one side of its drain contact 102, this arrangement produces a more compact (e.g., square) layout and reduces the overall interconnect length (e.g., in a specific implementation in which each transistor unit 90 includes a single gate contact 98 on only one side of its drain contact 102, the capacitor neutralizing transistor needs to be laterally interposed between the power transistors, which increases the overall area occupied by the amplifier stage).

[0088] Furthermore, this layout simplifies the connection of the input and output matching networks because the gate and drain terminals are located at two different ends. The dual-sided gate connection of each transistor unit cell 90 significantly reduces parasitic gate resistance (see, for example...). Figure 4 parasitic gate resistance R g As described above, this configuration also allows the source nodes of power transistors 72A and 72B to have minimal interconnect length (see example...). Figure 7 The very short length of the source contact 94 extending between power transistors 72A and 72B is directly connected together (e.g., in...). Figure 5 (at circuit node 74). This makes source interconnect parasitic effects virtually nonexistent between power transistors 72A and 72B and the reference voltage 64 in differential mode, thus effectively eliminating... Figure 4 The parasitic source resistance R of the differential mode of the signal used for transmission s Parasitic source inductance L s This only results in common-mode (CM) parasitic effects along a longer interconnect wiring path via the peripheral conductor 115, as shown in CM parasitic effect 114. This effectively means that the associated parasitic resistance and inductance of the system will not degrade the amplifier stage in differential mode. Parasitic resistance and inductance in common mode can contribute to the stability of the amplifier stage because it reduces the common-mode gain. On the other hand, in a specific embodiment where each transistor unit cell 90 includes a single gate contact 98 only on one side of the drain contact 102, the amplifier stage occupies a larger area on the substrate 92, suffers from higher gate resistance (e.g., increased gate resistance) due to the single-sided gate connection, and exhibits higher differential-mode parasitic source resistance and inductance, which can significantly reduce power gain and RF performance.

[0089] Figure 8 This is an example of a specific implementation in which each transistor unit cell 90 includes a single gate contact 98 only on one side of the drain contact 102. Figures 4 to 7 The specific implementation plots how this improves the performance of amplifier 50. Curve 120 plots the maximum gain (Gmax) of the amplifier in a specific implementation where each transistor unit cell 90 includes a single gate contact 98 on only one side of the drain contact 102, and curve 124 plots the stability factor kf of the amplifier, which varies with frequency. Curve 122 plots... Figures 4 to 7 The specific implementation of the amplifier's Gmax is plotted, and curve 126 plots the amplifier's kf. As shown in curves 120 to 126, Figures 4 to 7 Specific implementations can be used to increase Gmax (e.g., by up to 2.4 dB) and can be used to provide a wider stable operating bandwidth (e.g., a wider frequency range exceeding kf=1) compared to implementations where each transistor unit cell 90 includes a single gate contact 98 only on one side of the drain contact 102. In summary, relative to implementations where each transistor unit cell 90 includes a single gate contact 98 only on one side of the drain contact 102, Figures 4 to 7 The specific implementation is much less affected by layout-related parasitic effects and long interconnect wiring.

[0090] Figure 9 The output matching network 62 was plotted. Figure 4 This includes the performance of amplifier 50 (e.g., a D-band amplifier) ​​in an example of a distributed balun based on coupling connections. Curve 128 plots the impedance magnitude at terminal 68N, curve 130 plots the real part of the impedance at terminal 68N, and curve 132 plots the imaginary part of the impedance at terminal 68N. The magnitude and impedance components at terminal 68P follow similar characteristics. Curve 134 plots the passive efficiency (PE) of the amplifier. As shown by curves 128 to 134, using Figures 4 to 7 The specific implementation of amplifier 50 enables the amplifier to be configured to exhibit broadband optimal load impedance while maintaining very high passive efficiency (e.g., greater than 84% or higher) over a relatively wide bandwidth (e.g., including D-band frequencies). Figure 8 and Figure 9 The examples are illustrative and not limiting. In practice, curves 120 to 134 may have other shapes.

[0091] Figure 10 Another example is illustrated, where amplifier 50 is a multi-stage amplifier comprising both a first amplifier stage 82 and a second amplifier stage 82' coupled between an input matching network 60 and an output matching network 62. Figure 10 As shown, amplifier stage 82' can be coupled between input matching network 60 and interstage matching network 136. Amplifier stage 82 can be coupled between interstage matching network 136 and output matching network 62. Each matching network may include a corresponding transformer if desired. The input and output matching networks may include baluns if desired. Figure 10 The output matching network 62 in the example includes a distributed balun based on coupling wires. This is illustrative and not limiting.

[0092] Input matching network 60 can receive an RF signal (e.g., as a single-ended signal) at input terminal 140 and can transmit the RF signal to terminals 66P and 66N (e.g., as a differential signal). Amplifier stage 82' can be a driver stage that drives the signal to amplifier stage 82 via interstage matching network 136. Amplifier stage 82 can be a PA stage that amplifies the signal and drives the signal to output matching network 62. Output matching network 62 can output a signal via output terminal 138 (e.g., as a single-ended signal). Figure 3The radio frequency signal RFSIG (e.g., as a single-ended signal). Amplifier stage 82 and amplifier stage 82' may each include a pair of power transistors 72 and a pair of capacitor neutralizing transistors 76. Some or all of the transistors in amplifier stage 82 and amplifier stage 82' may be used individually. Figure 5 and Figure 6 This is achieved through a corresponding set of one or more transistor unit cells 90. The transistors of amplifier stage 82 and / or amplifier stage 82' can be implemented as follows: Figure 7 The layout is shown.

[0093] Figure 11 yes Figure 10 The graph shows the scattering parameters (S-parameters) of a two-stage amplifier 50 as a function of frequency. Figure 11 As shown, curve 142 plots the S21 scattering parameter, curve 146 plots the S22 scattering parameter, curve 148 plots the S11 scattering parameter, and curve 144 plots the noise figure of amplifier 50. As shown by curves 142 to 148, amplifier 50 can exhibit a relatively high peak S21 (characterizing forward signal transmission), such as 19.5 dB at 107 GHz (e.g., with a 3 dB-S21 bandwidth from 98.5 GHz to 125 GHz), a relatively low S22 (characterizing output port signal reflection), a relatively low S11 (characterizing input port signal reflection), and a sufficiently low noise figure across a relatively wide frequency range including the D band (e.g., as low as 5 dB to 5.3 dB from about 116 GHz to about 123 GHz). The input matching network can, for example, configure S11 to be better than -10 dB from about 103 GHz to about 152 GHz.

[0094] Figure 12 It is shown Figure 10 A graph showing other performance characteristics of the two-stage amplifier 50 in a continuous wave (CW) transmission implementation (e.g., at 120 GHz). Figure 12 Curve 150 plots the output phase, curve 152 plots the gain, curve 154 plots the DE of the final amplifier stage, curve 156 plots the power-added efficiency (PAE), and curve 158 plots the Pdc of the amplifier. At 120 GHz, the amplifier achieves, for example, a power gain of 18 dB and a saturation power of 10.4 dBm, as well as a very high peak PAE of 22%.

[0095] This method of implementing amplifier 50 also allows the amplifier to be configured to exhibit robust performance across operating frequencies and process corners. Figure 13 The error vector magnitude (EVM) of amplifier 50 as a function of output power level POUT under different conditions was plotted. Figure 13Curve 160 plots the EVM of amplifier 50 across different frequencies, process angles, and temperatures when transmitting QPSK signals. Figure 13 Curve 162 plots the EVM of amplifier 50 across different frequency, process angle, and temperature variations when transmitting a 64 QAM signal. As shown by curves 160 to 162, the EVM of amplifier 50 remains relatively low and consistent across modulation schemes, as well as frequency, process angle, and temperature variations. Figures 11 to 13 The examples are illustrative, and in practice, curves 142 to 162 may have other shapes.

[0096] use Figures 5 to 7 Implementing amplifier 50 using transistor unit cells 90 and its layout allows amplifier 50 to exhibit performance similar to a three-stage amplifier when comprising only two amplifier stages 82 and 82'. For example, amplifier 50 can use only two amplifier stages to exhibit similar gain to a three-stage finFET amplifier comprising transistor unit cells having a single gate contact only on one side of the drain contact, and can exhibit a higher peak PAE (e.g., 22%) compared to an amplifier comprising transistor unit cells having a single gate contact only on one side of the drain contact (e.g., 12.8%). Implementing amplifier 50 using only two stages also reduces amplifier area, power consumption, and cost compared to implementations with three or more stages.

[0097] The above text combined Figures 1 to 13 The described methods and operations can be performed by components of device 10 using software, firmware, and / or hardware (e.g., dedicated circuitry or hardware). Software code for performing these operations may be stored on a non-transitory computer-readable storage medium (e.g., a tangible computer-readable storage medium) stored on one or more components of device 10 (e.g., ...). Figure 1 The storage device circuitry 16 and / or wireless communication circuitry 24). This software code may sometimes be referred to as software, data, instructions, program instructions, or code. Non-transitory computer-readable storage media may include drives, non-volatile memory such as non-volatile random access memory (NVRAM), removable flash drives or other removable media, other types of random access memory, etc. The software stored on the non-transitory computer-readable storage medium may be processed by processing circuitry on one or more components of device 10 (e.g., processing circuitry in wireless communication circuitry 24, ...). Figure 1 The processing circuitry (e.g., 18) executes the operation. This processing circuitry may include a microprocessor, application processor, digital signal processor, central processing unit (CPU), application-specific integrated circuit (ASIC) with processing circuitry, or other processing circuitry.

[0098] As used herein, the term "concurrent" means at least partially overlapping in time. In other words, the first and second events are referred to herein as "concurrent" if at least some of the first events occur simultaneously with at least some of the second events (e.g., if at least some of the first events occur during, concurrently with, or when at least some of the second events occur). The first and second events can be concurrent if they are synchronized (e.g., if the entire duration of the first event overlaps with the entire duration of the second event in time), but they can also be concurrent if they are asynchronous (e.g., if the first event begins before or after the second event, ends before or after the second event, or does not partially overlap in time). As used herein, the term "at the time of" is synonymous with "concurrent".

[0099] As is widely recognized, the use of personally identifiable information should comply with privacy policies and measures that are generally accepted to meet or exceed industry or governmental requirements for protecting user privacy. Specifically, personally identifiable information data should be managed and processed to minimize the risk of unintentional or unauthorized access or use, and the nature of authorized use should be clearly explained to users.

[0100] According to one embodiment, a radio frequency amplifier includes an input matching network; an output matching network; a semiconductor substrate; and an amplifier stage located on the semiconductor substrate and coupled between the input matching network and the output matching network. The amplifier stage includes a first transistor, and the first transistor includes: a first drain contact communicatively coupled to the output matching network; a first gate contact communicatively coupled to the input matching network; and a second gate contact communicatively coupled to the input matching network. The first drain contact is laterally interposed on the semiconductor substrate between the first gate contact and the second gate contact.

[0101] According to another embodiment, the first transistor may optionally include: a first gate line that couples the first gate contact to the second gate contact; and a second gate line that is parallel to the first gate line and couples the first gate contact to the second gate contact.

[0102] According to another embodiment, the first transistor may optionally further include: a first source contact, the first source contact being communicatively coupled to a reference voltage; a second source contact, the second source contact being communicatively coupled to the reference voltage; and a set of source lines, the set of source lines coupling the first contact to the second contact.

[0103] According to another embodiment, the first drain contact may extend along a first longitudinal axis, the first source contact extends along a second longitudinal axis parallel to the first longitudinal axis, the second source contact extends along a third longitudinal axis parallel to the second longitudinal axis, the set of source lines extends orthogonally to the first longitudinal axis, the second longitudinal axis and the third longitudinal axis, the first drain contact has a first edge and a second edge orthogonal to the first longitudinal axis, the first drain contact has a third edge and a fourth edge extending from the first edge to the second edge parallel to the first longitudinal axis, the first gate contact faces the first edge of the first drain contact, the second gate contact faces the second edge of the first drain contact, the first source contact faces the third edge of the first drain contact, and the second source contact faces the fourth edge of the first drain contact.

[0104] According to another embodiment, the amplifier stage may optionally include a common-source stage.

[0105] According to another embodiment, the RF amplifier may optionally include a common-source amplifier, a common-source cascode amplifier, or an amplifier implementing a stacked topology.

[0106] According to another embodiment, the first drain contact, the first gate contact, and the second gate contact may each optionally include a corresponding portion of the same metallization layer on the semiconductor substrate.

[0107] According to another embodiment, the first drain contact of the first transistor is optionally coupled to a first input terminal of the output matching network. The amplifier stage includes a second transistor, and the second transistor includes: a second drain contact coupled to a second input terminal of the output matching network; a third gate contact; a fourth gate contact, wherein the first gate contact and the second gate contact of the first transistor are coupled to a first output terminal of the input matching network via a first signal line, and the third gate contact and the fourth gate contact of the second transistor are coupled to a second output terminal of the input matching network via a second signal line, and the second drain contact is laterally interposed on the semiconductor substrate between the third gate contact and the fourth gate contact; and a source node, wherein the source node is coupled to a reference voltage and the source node of the first transistor.

[0108] According to another embodiment, the first drain contact of the first transistor is optionally coupled to a first input terminal of the output matching network. The common-source amplifier includes a second transistor, and the second transistor includes: a second drain contact coupled to a second input terminal of the output matching network; a third gate contact; a fourth gate contact, wherein the first and second gate contacts of the first transistor are coupled to a circuit node, the third and fourth gate contacts of the second transistor are coupled to the circuit node, and the circuit node is coupled to an output terminal of the input matching network via a signal path; and a source node coupled to a reference voltage, wherein the source node of the second transistor is coupled to the reference voltage.

[0109] According to another embodiment, the second transistor may optionally be configured to neutralize the capacitance of the first transistor.

[0110] According to another embodiment, the first transistor optionally includes a first power transistor, the first gate contact and the second gate contact forming part of a first gate node of the first power transistor, the first power transistor having a first source node, the first drain contact coupled to a first input terminal of the output matching network, and the amplification stage including: a second power transistor having a second drain contact coupled to a second input terminal of the output matching network, a second gate node and a second source node, wherein the second source node is coupled to the first source node and a reference voltage; a first capacitor neutralizing transistor having a third source node coupled to the reference voltage, and a second gate node coupled to the reference voltage. The first input matching network includes a second input terminal and a third drain contact connected to the second drain contact of the output matching network, and a third gate node coupled to the first gate node of the first power transistor, wherein the first gate node and the third gate node are coupled to the first output terminal of the first input matching network; and a second capacitor neutralizing transistor having a fourth source node coupled to the reference voltage, a fourth drain contact coupled to the first input terminal and the first drain contact of the output matching network, and a fourth gate node coupled to the second gate node of the second power transistor, wherein the second gate node and the fourth gate node are coupled to the second output terminal of the first input matching network.

[0111] According to another embodiment, the first power transistor is optionally laterally interposed on the semiconductor substrate between the first capacitor neutralizing transistor and the second power transistor, and the second power transistor is laterally interposed on the semiconductor substrate between the first power transistor and the second capacitor neutralizing transistor.

[0112] According to one embodiment, an RF amplifier includes: an input network having a first terminal and a second terminal; an output network having a third terminal and a fourth terminal; a substrate; a first transistor located on the substrate and having a first gate terminal coupled to the first terminal, a first source-drain terminal coupled to the third terminal, and a second source-drain terminal coupled to a reference voltage; a second transistor located on the substrate and having a second gate terminal coupled to the second terminal, a third source-drain terminal coupled to the fourth terminal, and a fourth source-drain terminal coupled to the second source-drain terminal and the reference voltage; the third transistor, The third transistor is located on the substrate and has a third gate terminal coupled to the first terminal and the first gate terminal, a fifth source-drain terminal coupled to the fourth terminal and the third source-drain terminal, and a sixth source-drain terminal coupled to the reference voltage; and a fourth transistor, the fourth transistor being located on the substrate and having a fourth gate terminal coupled to the second terminal and the second gate terminal, a seventh source-drain terminal coupled to the third terminal and the first source-drain terminal, and an eighth source-drain terminal coupled to the reference voltage, wherein the first transistor and the second transistor are laterally interposed on the substrate between the third transistor and the fourth transistor.

[0113] According to another embodiment, the first transistor is optionally laterally interposed on the substrate between the second transistor and the third transistor, and the second transistor is laterally interposed on the substrate between the first transistor and the fourth transistor.

[0114] According to another embodiment, the first transistor may optionally include a first set of transistor unit cells, the second transistor includes a second set of transistor unit cells, the third transistor includes a third set of transistor unit cells, and the fourth transistor includes a fourth set of transistor unit cells, wherein the first set of transistor unit cells and the second set of transistor unit cells are laterally interposed on the substrate between the third set of transistor unit cells and the fourth set of transistor unit cells.

[0115] According to another embodiment, each transistor unit cell in the first set of unit cells and the second set of unit cells optionally includes: an elongated drain contact having a first edge and a second edge extending parallel to a longitudinal axis of the elongated drain contact, and having a third edge and a fourth edge extending from the first edge to the second edge; a first elongated source contact extending parallel to the elongated drain contact and facing the first edge of the elongated drain contact; a second elongated source contact extending parallel to the elongated drain contact and facing the second edge of the elongated drain contact; a first gate contact facing the third edge of the elongated drain contact; a second gate contact facing the third edge of the elongated drain contact; a plurality of gate lines coupling the first gate contact to the second gate contact; and a plurality of source lines coupling the first elongated source contact to the second elongated source contact.

[0116] According to another embodiment, the plurality of source lines may optionally be vertically inserted between the plurality of gate lines and the elongated drain contact.

[0117] According to another embodiment, the elongated drain contact, the first gate contact, and the second gate contact may optionally be formed in the same metallization layer of the substrate.

[0118] According to one embodiment, a common-source amplifier includes: a first set of transistor cells sharing a first gate node, a first source node coupled to a reference voltage, and a first drain node, wherein the transistor cells in the first set include: a first drain contact of the first drain node extending along a longitudinal axis; a first source contact of the first source node extending parallel to the longitudinal axis at a first side of the first drain contact; and a second source contact of the first source node extending parallel to the longitudinal axis at a second side of the first drain contact opposite to the first side. The first gate contact of the first gate node extends orthogonally to the longitudinal axis at a third side of the first drain contact; the second gate contact of the first gate node extends orthogonally to the longitudinal axis at a fourth side of the first drain contact opposite to the third side; the first plurality of gate lines of the first gate node extend parallel to the longitudinal axis and couple the first gate contact to the second gate contact; and the first plurality of source lines of the first source node extend orthogonally to the longitudinal axis and couple the first source contact to the second source contact.

[0119] According to another embodiment, the common-source amplifier may optionally further include: a second set of transistor units, the second set of transistor units sharing a second gate node, a second source node coupled to the first source node and the reference voltage, and a second drain node, wherein the transistor unit in the second set includes: a second drain contact of the second drain node, the second drain contact extending parallel to the longitudinal axis; a third source contact of the second source node, the third source contact extending parallel to the longitudinal axis at a first side of the second drain contact and coupled to the first source contact of the first set of transistor units; and a fourth source contact of the second source node, the fourth source contact being flush with the second side of the second drain contact opposite to the first side of the second drain contact. The second source contact extends along the longitudinal axis and is coupled to a first set of transistor cells; a third gate contact of the second gate node, the third gate contact extending orthogonally to the longitudinal axis at a third side of the second drain contact; a fourth gate contact of the second gate node, the fourth gate contact extending orthogonally to the longitudinal axis at a fourth side of the second drain contact opposite the third side of the second drain contact; a second plurality of gate lines of the second gate node, the second plurality of gate lines extending parallel to the longitudinal axis and coupling the third gate contact to the fourth gate contact; and a second plurality of source lines of the second source node, the second plurality of source lines extending orthogonally to the longitudinal axis and coupling the third source contact to the fourth source contact.

[0120] The foregoing is merely illustrative and various modifications can be made to the described implementation scheme. The foregoing implementation scheme can be implemented individually or in any combination.

Claims

1. A radio frequency amplifier, the radio frequency amplifier comprising: Input matching network; Output matching network; Semiconductor substrate; and An amplifier stage, located on the semiconductor substrate and coupled between the input matching network and the output matching network, wherein the amplifier stage includes a first transistor, and the first transistor includes... The first drain contact is communicatively coupled to the output matching network. A first gate contact, the first gate contact being communicatively coupled to the input matching network, and A second gate contact is communicatively coupled to the input matching network, wherein a first drain contact is laterally inserted on the semiconductor substrate between the first gate contact and the second gate contact.

2. The radio frequency amplifier according to claim 1, wherein the first transistor comprises: A first gate line, wherein the first gate line couples the first gate contact to the second gate contact; and A second gate line, parallel to the first gate line, couples the first gate contact to the second gate contact.

3. The radio frequency amplifier according to claim 2, wherein the first transistor further comprises: The first source contact is communicatively grounded to the reference voltage; The second source contact is communicatively coupled to the reference voltage; and A set of source lines that couples the first contact to the second contact.

4. The radio frequency amplifier according to claim 3, wherein: The first drain contact extends along the first longitudinal axis. The first source contact extends along a second longitudinal axis parallel to the first longitudinal axis. The second source contact extends along a third longitudinal axis parallel to the second longitudinal axis. The set of source lines extends orthogonally to the first longitudinal axis, the second longitudinal axis, and the third longitudinal axis. The first drain contact has a first edge and a second edge orthogonal to the first longitudinal axis. The first drain contact has a third edge and a fourth edge that extend from the first edge to the second edge parallel to the first longitudinal axis. The first gate contact faces the first edge of the first drain contact. The second gate contact faces the second edge of the first drain contact. The first source contact faces the third edge of the first drain contact, and The second source contact faces the fourth edge of the first drain contact.

5. The radio frequency amplifier according to claim 1, wherein the amplifier stage includes a common-source stage.

6. The radio frequency amplifier of claim 5, wherein the radio frequency amplifier comprises a common-source amplifier, a common-source cascode amplifier, or an amplifier implementing a stacked topology.

7. The radio frequency amplifier of claim 1, wherein the first drain contact, the first gate contact and the second gate contact each comprise a corresponding portion of the same metallization layer on the semiconductor substrate.

8. The RF amplifier of claim 1, wherein the first drain contact of the first transistor is coupled to a first input terminal of the output matching network, the amplifier stage includes a second transistor, and the second transistor includes: The second drain contact is coupled to the second input terminal of the output matching network; Third gate contact; A fourth gate contact, wherein the first gate contact and the second gate contact of the first transistor are coupled to the first output terminal of the input matching network via a first signal line, the third gate contact and the fourth gate contact of the second transistor are coupled to the second output terminal of the input matching network via a second signal line, and the second drain contact is laterally inserted on the semiconductor substrate between the third gate contact and the fourth gate contact; and The source node is coupled to the reference voltage and the source node of the first transistor.

9. The RF amplifier of claim 1, wherein the first drain contact of the first transistor is coupled to a first input terminal of the output matching network, the common-source amplifier includes a second transistor, and the second transistor includes: The second drain contact is coupled to the second input terminal of the output matching network; Third gate contact; A fourth gate contact, wherein the first gate contact and the second gate contact of the first transistor are coupled to a circuit node, the third gate contact and the fourth gate contact of the second transistor are coupled to the circuit node, and the circuit node is coupled to the output terminal of the input matching network via a signal path; and A source node coupled to a reference voltage, wherein the source node of the second transistor is coupled to the reference voltage.

10. The radio frequency amplifier of claim 9, wherein the second transistor is configured to neutralize the capacitance of the first transistor.

11. The RF amplifier of claim 1, wherein the first transistor includes a first power transistor, the first gate contact and the second gate contact form part of a first gate node of the first power transistor, the first power transistor has a first source node, the first drain contact is coupled to a first input terminal of the output matching network, and the amplifier stage includes: The second power transistor has a second drain contact, a second gate node, and a second source node coupled to a second input terminal of the output matching network, wherein the second source node is coupled to the first source node and a reference voltage; A first capacitor neutralizing transistor has a third source node coupled to the reference voltage, a third drain contact coupled to the second input terminal and the second drain contact of the output matching network, and a third gate node coupled to the first gate node of the first power transistor, wherein the first gate node and the third gate node are coupled to the first output terminal of the first input matching network. and The second capacitor neutralizing transistor has a fourth source node coupled to the reference voltage, a fourth drain contact coupled to the first input terminal and the first drain contact of the output matching network, and a fourth gate node coupled to the second gate node of the second power transistor, wherein the second gate node and the fourth gate node are coupled to the second output terminal of the first input matching network.

12. The radio frequency amplifier of claim 11, wherein the first power transistor is laterally interposed on the semiconductor substrate between the first capacitor neutralizing transistor and the second power transistor, and wherein the second power transistor is laterally interposed on the semiconductor substrate between the first power transistor and the second capacitor neutralizing transistor.

13. A radio frequency amplifier, the radio frequency amplifier comprising: An input network having a first terminal and a second terminal; An output network having a third terminal and a fourth terminal; substrate; A first transistor, the first transistor being located on the substrate and having a first gate terminal coupled to the first terminal, a first source-drain terminal coupled to the third terminal, and a second source-drain terminal coupled to a reference voltage; The second transistor is located on the substrate and has a second gate terminal coupled to the second terminal, a third source-drain terminal coupled to the fourth terminal, and a fourth source-drain terminal coupled to the second source-drain terminal and the reference voltage; A third transistor is located on the substrate and has a third gate terminal coupled to the first terminal and the first gate terminal, a fifth source-drain terminal coupled to the fourth terminal and the third source-drain terminal, and a sixth source-drain terminal coupled to the reference voltage; and A fourth transistor, located on the substrate, has a fourth gate terminal coupled to the second terminal and the second gate terminal, a seventh source-drain terminal coupled to the third terminal and the first source-drain terminal, and an eighth source-drain terminal coupled to the reference voltage, wherein... The first transistor and the second transistor are laterally interposed on the substrate between the third transistor and the fourth transistor.

14. The radio frequency amplifier of claim 13, wherein the first transistor is laterally interposed on the substrate between the second transistor and the third transistor, and wherein the second transistor is laterally interposed on the substrate between the first transistor and the fourth transistor.

15. The radio frequency amplifier of claim 13, wherein the first transistor comprises a first set of transistor unit cells, the second transistor comprises a second set of transistor unit cells, the third transistor comprises a third set of transistor unit cells, and the fourth transistor comprises a fourth set of transistor unit cells, the first set of transistor unit cells and the second set of transistor unit cells being laterally interposed on the substrate between the third set of transistor unit cells and the fourth set of transistor unit cells.

16. The radio frequency amplifier of claim 15, wherein each transistor unit cell in the first set of unit cells and the second set of unit cells comprises: An elongated drain contact having a first edge and a second edge extending parallel to the longitudinal axis of the elongated drain contact, and having a third edge and a fourth edge extending from the first edge to the second edge; A first elongated source contact extends parallel to the elongated drain contact and faces the first edge of the elongated drain contact; The second elongated source contact extends parallel to the elongated drain contact and faces the second edge of the elongated drain contact; A first gate contact, the first gate contact facing the third edge of the elongated drain contact; A second gate contact, the second gate contact facing the third edge of the elongated drain contact; A plurality of gate lines, wherein the plurality of gate lines couple the first gate contact to the second gate contact; and Multiple source lines, wherein the multiple source lines couple the first elongated source contact to the second elongated source contact.

17. The radio frequency amplifier of claim 16, wherein the plurality of source lines are vertically inserted between the plurality of gate lines and the elongated drain contact.

18. The radio frequency amplifier of claim 16, wherein the elongated drain contact, the first gate contact, and the second gate contact are formed in the same metallization layer of the substrate.

19. A common-source amplifier, the common-source amplifier comprising: A first set of transistor cells, the first set of transistor cells sharing a first gate node, a first source node coupled to a reference voltage, and a first drain node, wherein the transistor cells in the first set include The first drain contact of the first drain node extends along the longitudinal axis; The first source contact of the first source node extends parallel to the longitudinal axis at a first side of the first drain contact; The second source contact of the first source node extends parallel to the longitudinal axis at the second side of the first drain contact opposite to the first side; The first gate contact of the first gate node extends orthogonally to the longitudinal axis at the third side of the first drain contact; The second gate contact of the first gate node extends orthogonally to the longitudinal axis at the fourth side of the first drain contact opposite to the third side; The first plurality of gate lines of the first gate node extend parallel to the longitudinal axis and couple the first gate contact to the second gate contact. and The first plurality of source lines of the first source node extend orthogonally to the longitudinal axis and couple the first source contact to the second source contact.

20. The common-source amplifier of claim 19, further comprising a second set of transistor units, the second set of transistor units sharing a second gate node, a second source node coupled to the first source node and the reference voltage, and a second drain node, wherein the transistor units in the second set comprise: The second drain contact of the second drain node extends parallel to the longitudinal axis; The third source contact of the second source node extends parallel to the longitudinal axis at the first side of the second drain contact and is coupled to the first source contact of the first set of transistor cells; The fourth source contact of the second source node extends parallel to the longitudinal axis at the second side of the second drain contact opposite to the first side of the second drain contact and is coupled to the second source contact of the first set of transistor cells; The third gate contact of the second gate node extends orthogonally to the longitudinal axis at the third side of the second drain contact; The fourth gate contact of the second gate node extends orthogonally to the longitudinal axis at the fourth side of the second drain contact opposite to the third side of the second drain contact; The second gate node has a second plurality of gate lines that extend parallel to the longitudinal axis and couple the third gate contact to the fourth gate contact. and The second plurality of source lines of the second source node extend orthogonally to the longitudinal axis and couple the third source contact to the fourth source contact.

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