Relaxation oscillator and frequency stabilization method for relaxation oscillator

Abstract

This application relates to a relaxation oscillator and a method for stabilizing the frequency of the relaxation oscillator. The relaxation oscillator includes: a first RC network module comprising an RC network and a signal multiplexing unit with identical structures; the RC network receiving an external power supply signal and a clock signal output from a first clock feedback module, and outputting a first voltage signal pair and a second voltage signal pair respectively; the clock signal including a first clock signal and a second clock signal with opposite phases; the signal multiplexing unit selecting, based on the phase of the clock signal, a voltage pair with a higher common-mode voltage as a first target voltage signal pair and outputting it to the first clock feedback module; and the first clock feedback module comparing the amplitudes of the two voltage signals in the first target voltage signal pair with preset thresholds respectively, and outputting the first clock signal and the second clock signal to the first RC network module based on the comparison results. The frequency stability of the relaxation oscillator is improved by enhancing the RC network through asymmetric swing.

Description

Technical Field

[0001] This application relates to the field of integrated circuit relaxation oscillator technology, and in particular to relaxation oscillators and methods for stabilizing the frequency of relaxation oscillators. Background Technology

[0002] A relaxation oscillator is an on-chip clock source based on the periodic charging and discharging of a resistor-capacitor network and triggering by a voltage comparator. It is widely used in low-power devices such as IoT nodes and wireless transceivers as a precise timer. Currently, to achieve full-cycle oscillation of a relaxation oscillator, it is usually necessary to simultaneously drive two resistor-capacitor networks with opposite phases to generate complementary voltage signal pairs. When one voltage signal gradually rises and the other gradually falls, the two signals complete level alternation near the crossover point, thereby triggering the switching of the relaxation oscillator's operating state. The two voltage signals continue to alternately rise and fall, and the above level alternation and state switching process is repeated continuously, thus achieving full-cycle continuous oscillation of the relaxation oscillator.

[0003] However, when the two sets of voltage signal pairs are input to the subsequent circuitry of the RC network, each set of voltage signal pairs introduces independent circuit noise. Since the circuit noise is difficult to effectively cancel in subsequent differential processing, it directly superimposes and transforms into periodic timing jitter, thereby degrading the overall phase noise of the relaxation oscillator and reducing its frequency stability.

[0004] There is currently no effective solution to the problem of low frequency stability of relaxation oscillators in related technologies. Summary of the Invention

[0005] This embodiment provides a relaxation oscillator and a method for stabilizing the frequency of the relaxation oscillator to solve the problem of low frequency stability of relaxation oscillators in related technologies.

[0006] In a first aspect, this embodiment provides a relaxation oscillator, including: a first RC network module and a first clock feedback module; the first RC network module includes a first asymmetric RC network, a second asymmetric RC network, and a signal multiplexing unit with identical structures; the output terminal of the first RC network module is connected to the input terminal of the first clock feedback module; the output terminal of the first clock feedback module is connected to the input terminal of the first RC network module; wherein:

[0007] The first asymmetric RC network and the second asymmetric RC network are used to receive the external power supply signal and the clock signal output by the first clock feedback module, and respectively output a first voltage signal pair and a second voltage signal pair; the clock signal includes a first clock signal and a second clock signal with opposite phases.

[0008] The signal multiplexing unit is used to select, based on the phase of the clock signal, the voltage pair with the higher common-mode voltage among the first voltage signal pair and the second voltage signal pair as the first target voltage signal pair and output it to the first clock feedback module.

[0009] The first clock feedback module is used to compare the amplitudes of the two voltage signals in the first target voltage signal pair with preset thresholds respectively, and output the first clock signal and the second clock signal to the first resistor-capacitor network module according to the comparison results.

[0010] In some embodiments, the relaxation oscillator further includes a duty cycle control module; the duty cycle control module includes an enable signal generation unit, a phase detection unit, and a feedback control unit; the input terminal of the enable signal generation unit is connected to the output terminal of the first clock feedback module, the output terminal of the enable signal generation unit is connected to the input terminal of the phase detection unit, the output terminal of the phase detection unit is connected to the input terminal of the feedback control unit, and the output terminal of the feedback control unit is connected to the enable terminal of the first clock feedback module; wherein:

[0011] The enable signal generating unit is used to generate and output periodic enable pulses according to the clock signal;

[0012] The phase detection unit is used to obtain the phase difference between the falling edge of the enable pulse and the rising edge of the second clock signal;

[0013] The feedback control unit outputs a control signal to the enable signal generating unit based on the phase difference; the control signal is used to adjust the enable pulse.

[0014] In some embodiments, the feedback control unit further includes a charge pump subunit and a capacitor subunit;

[0015] The charge pump subunit is used to charge and discharge the capacitor in the capacitor subunit;

[0016] The capacitor subunit is used to output the control signal and adjust the enable pulse according to the control signal.

[0017] In some embodiments, the first clock feedback module includes: a signal shaping unit and a latching unit; the input terminal of the signal shaping unit is connected to the output terminal of the first RC network module; the output terminal of the signal shaping unit is connected to the input terminal of the latching unit, and the output terminal of the latching unit is connected to the input terminal of the first RC network module; wherein:

[0018] The signal shaping unit is configured to receive a first signal and a second signal from the first target voltage signal pair, compare the first signal with a preset first threshold and output a set signal according to the comparison result; compare the second signal with a preset second threshold and output a reset signal according to the comparison result.

[0019] The latch unit is used to output the clock signal to the first resistor-capacitor network module in response to the set signal and the reset signal.

[0020] In some embodiments, the signal shaping unit is configured to, in response to an enable pulse, compare the first signal with a corresponding preset first threshold and compare the second signal with a corresponding preset second threshold.

[0021] In some embodiments, the first clock feedback module further includes: a clock boosting unit, the input of which is connected to the output of the latch unit, and the output of which is connected to the input of the first RC network module; wherein:

[0022] The clock boosting unit is used to boost the voltage swing and power of the clock signal and output the enhanced clock signal to the first resistor-capacitor network module.

[0023] In some embodiments, the relaxation oscillator further includes a signal amplification module, which includes a feedback amplification unit and a threshold voltage amplification unit. The input of the feedback amplification unit is connected to the output of the first RC network module, the output of the feedback amplification unit is connected to the input of the threshold voltage amplification unit, and the output of the threshold voltage amplification unit is connected to the input of the first clock feedback module.

[0024] The feedback amplification unit is used to amplify the differential-mode component of the first target voltage signal pair, compare the common-mode voltage of the first target voltage signal pair with a preset reference voltage, adjust the first target voltage signal pair according to the comparison result so that the common-mode voltage approaches the preset reference voltage, obtain a first-stage amplified signal pair, and input the first-stage amplified signal pair to the threshold voltage amplification unit.

[0025] The threshold voltage amplification unit is used to amplify the differential-mode component of the first-stage amplified signal pair and adjust the first-stage amplified signal pair according to the preset first threshold or the preset second threshold, so that the transition point of the first-stage amplified signal pair is increased to obtain the second-stage amplified signal pair; the transition point is the voltage value when the difference between the two voltage signals in the first-stage amplified signal pair is less than the preset first transition threshold.

[0026] In some embodiments, the relaxation oscillator further includes a temperature compensation module: wherein the temperature compensation module includes a second RC network module with the same structure as the first RC network module, a second clock feedback module with the same structure as the first clock feedback module, a measurement circuit unit, and a compensation voltage generation unit; the time constants of the capacitors and resistors in the second RC network module are less than the time constants of the capacitors and resistors in the first RC network module; the output terminal of the second RC network module is connected to the input terminal of the second clock feedback module, the output terminal of the second clock feedback module is connected to the input terminal of the measurement circuit unit, the output terminal of the measurement circuit unit is connected to the input terminal of the compensation voltage generation unit, and the output terminal of the compensation voltage generation unit is connected to the input terminal of the first RC network module; wherein:

[0027] The second RC network module is used to receive the external power supply signal and the third clock signal and fourth clock signal output by the second clock feedback module, which are out of phase, and output the third voltage signal pair and the fourth voltage signal pair; according to the phase of the third clock signal and the fourth clock signal, the voltage pair with the higher common-mode voltage among the third voltage signal pair and the fourth voltage signal pair is selected as the second target voltage signal pair and output to the second clock feedback module.

[0028] The second clock feedback module is used to compare the amplitudes of the two voltage signals in the second target voltage signal pair with preset thresholds respectively, and output the third clock signal and the fourth clock signal to the second resistor-capacitor network module according to the comparison results;

[0029] The measurement circuit is used to measure the transition time of the two voltage signals in the second target voltage signal pair; the transition time is the time length between the previous moment when it is determined that the difference between the two voltage signals in the second target voltage signal pair is less than a preset second transition threshold and the current moment.

[0030] The compensation voltage generation unit is used to generate a compensation voltage based on the time difference between the switching time and the theoretical switching time, and output the compensation voltage to the second RC network module to adjust the current of the resistor in the first RC network.

[0031] Secondly, this embodiment provides a method for stabilizing the frequency of a relaxation oscillator, the method comprising:

[0032] A clock signal and a power signal are input to a first asymmetric RC network and a second asymmetric RC network, so that the first asymmetric RC network and the second asymmetric RC network output a first voltage signal pair and a second voltage signal pair, respectively; the clock signal includes a first clock signal and a second clock signal with opposite phases; the first asymmetric RC network and the second asymmetric RC network have the same structure.

[0033] Based on the phase of the clock signal, the voltage pair with the higher common-mode voltage among the first voltage signal pair and the second voltage signal pair is selected as the first target voltage signal pair;

[0034] The amplitudes of the two voltage signals in the first target voltage signal pair are compared with preset thresholds, and the clock signal is adjusted according to the comparison results.

[0035] Thirdly, this embodiment provides a self-powered Internet of Things (IoT) device that implements the relaxation oscillator described in the first aspect above.

[0036] Compared with related technologies, in the relaxation oscillator and frequency stabilization method provided in this embodiment, the first asymmetric RC network and the second asymmetric RC network with the same structure generate two signal pairs with opposite phases in response to the first clock signal and the second clock signal. With the help of the signal multiplexing unit, the signal pair with a high common-mode crossover point is selected from the signal pairs as the input of the first clock feedback module. This integrates the signals with different common-mode voltages originally generated by the two RC networks at different times into a continuous signal with a constant common-mode voltage. By splicing signal segments with the same high common-mode crossover point, the noise caused by the transient response of the circuit due to the periodic jump of the common-mode voltage of the signal source is avoided. The clock feedback module operates based on the integrated continuous signal with a constant common-mode voltage, thereby obtaining a low-noise relaxation oscillator and solving the problem of low frequency stability of the relaxation oscillator.

[0037] Details of one or more embodiments of this application are set forth in the following drawings and description to make other features, objects and advantages of this application more readily apparent. Attached Figure Description

[0038] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0039] Figure 1 This is a schematic diagram of the structure of a relaxation oscillator according to an embodiment of this application;

[0040] Figure 2 This is a circuit diagram of the first RC network module of a relaxation oscillator according to an embodiment of this application;

[0041] Figure 3 This is a timing waveform diagram of the first RC network module of a relaxation oscillator according to an embodiment of this application within a continuous time period;

[0042] Figure 4 This is a structural diagram of a relaxation oscillator duty cycle control module according to an embodiment of this application;

[0043] Figure 5 This is a timing waveform diagram of the duty cycle control module signal in a relaxation oscillator according to an embodiment of this application;

[0044] Figure 6 This is a simulation result diagram of the enable pulse enable rate in a relaxation oscillator according to one embodiment of this application;

[0045] Figure 7 This is a circuit schematic diagram of the signal shaping unit in a relaxation oscillator according to one embodiment of this application;

[0046] Figure 8 This is a circuit schematic diagram of the feedback amplification unit in a relaxation oscillator according to one embodiment of this application;

[0047] Figure 9 This is a circuit schematic diagram of the threshold voltage amplification unit in a relaxation oscillator according to one embodiment of this application;

[0048] Figure 10 This is a system block diagram of a relaxation oscillator temperature compensation module according to one embodiment of this application;

[0049] Figure 11 This is a frequency deviation diagram showing the effect of a temperature compensation module on the frequency of a relaxation oscillator as a function of temperature, according to one embodiment of this application.

[0050] Figure 12 This is a micrograph of a relaxation oscillator chip structure according to an embodiment of this application;

[0051] Figure 13 This is a frequency deviation curve of different sample chips of a relaxation oscillator according to an embodiment of this application within a temperature range;

[0052] Figure 14 This is a frequency deviation curve of different sample chips of a relaxation oscillator according to an embodiment of this application within a range of power supply voltage variation;

[0053] Figure 15 This is a graph showing the periodic jitter test results of a relaxation oscillator according to an embodiment of this application;

[0054] Figure 16This is a flowchart of a frequency stabilization method for a relaxation oscillator according to an embodiment of this application. Detailed Implementation

[0055] To better understand the purpose, technical solution, and advantages of this application, the application is described and illustrated below in conjunction with the accompanying drawings and embodiments.

[0056] Unless otherwise defined, the technical or scientific terms used in this application shall have the general meaning understood by one of ordinary skill in the art to which this application pertains. Words such as “a,” “an,” “an,” “the,” “the,” and “these” used in this application do not indicate quantitative limitation and may be singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that comprises a series of steps or modules (units) is not limited to the listed steps or modules (units) but may include steps or modules (units) not listed, or may include other steps or modules (units) inherent to these processes, methods, products, or devices. Words such as “connected,” “linked,” and “coupled” used in this application are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. “Multiple” used in this application refers to two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. Normally, the character " / " indicates that the objects before and after it are in an "or" relationship. The terms "first," "second," "third," etc., used in this application are merely to distinguish similar objects and do not represent a specific order of objects.

[0057] This embodiment provides a relaxation oscillator. Figure 1 This is a schematic diagram of the structure of a relaxation oscillator according to an embodiment of this application, as shown below. Figure 1 As shown, the relaxation oscillator includes: a first RC network module 100 and a first clock feedback module 200; the first RC network module 100 includes a first asymmetric RC network 110, a second asymmetric RC network 120, and a signal multiplexing unit 130 with identical structures; the output terminal of the first RC network module 100 is connected to the input terminal of the first clock feedback module 200; the output terminal of the first clock feedback module 200 is connected to the input terminal of the first RC network module 100; wherein:

[0058] The first asymmetric RC network 110 and the second asymmetric RC network 120 are used to receive the external power supply signal and the clock signal output by the first clock feedback module 200, and respectively output the first voltage signal pair and the second voltage signal pair; the clock signal includes the first clock signal and the second clock signal with opposite phases.

[0059] The first RC network module 100 consists of a first asymmetric RC network 110, a second asymmetric RC network 120, and a signal multiplexing unit 130. The RC network, as the timing core of the relaxation oscillator, generates a ramp voltage proportional to time through the linear charging and discharging of the capacitor. Specifically, within each clock half-cycle, the RC network in the charging state outputs a pair of differential ramp voltages that linearly rise from low to high, while the RC network in the discharging state outputs a pair of differential ramp voltages that linearly decrease from high to low. The first asymmetric RC network 110 and the second asymmetric RC network 120 are identical in circuit structure, receiving the same external power supply and driven by complementary clock signals, operating in a complementary and cooperative manner with opposite phases. Throughout the entire oscillation cycle, the first asymmetric RC network 110 and the second asymmetric RC network 120 are always operating simultaneously, but in opposite modes: when the first asymmetric RC network 110 is charging, the second asymmetric RC network 120 is discharging, and vice versa. This complementary design ensures that the first RC network module 100 can provide two pairs of available differential signals at any time, namely a first voltage signal pair and a second voltage signal pair.

[0060] Optionally, the first asymmetric RC network 110 includes a switching element, a resistor, and a capacitor. The specific connection structure of the switching element, resistor, and capacitor can be found in the structure of the asymmetric RC network in the related art. The structure of the second asymmetric RC network 120 is the same as that of the first asymmetric RC network 110, and will not be described in detail here.

[0061] The first asymmetric RC network 110 and the second asymmetric RC network 120 receive a pair of complementary, non-overlapping clock signals from the clock feedback module. Specifically, the first and second clock signals with opposite phases are used as control commands and are simultaneously input to the first and second asymmetric RC networks. The charging and discharging logic of the first and second asymmetric RC networks 110 and 120 is controlled by the clock signals. Therefore, the first voltage signal output by the first asymmetric RC network 110 is complementary to the second voltage signal output by the second asymmetric RC network 120.

[0062] For example, the first asymmetric RC network 110 and the second asymmetric RC network 120 are selected from RC networks with charging and discharging branches configured with different time constants. This design allows the first voltage signal output by the RC network to be centered, and the crossover point of the two voltage waveforms to deviate from the midpoint of the power supply voltage, thereby generating a stable high crossover point voltage (V). CM,H ) and a stable low crossover voltage (V CM,L This is to meet the specific bias voltage requirements of subsequent amplifiers under ultra-low voltage conditions. The crossover voltage, also known as the common-mode voltage, refers to the voltage value at the intersection point when two voltage signals intersect at the same time. Similarly, the second voltage signal pair also has high and low crossover voltages, which will not be elaborated upon here.

[0063] In one specific embodiment, the time constant ratio k of the charging branch to the discharging branch is set to 2, meaning the resistance of the lower half of the RC network is twice that of the upper half. This parameter design ensures that the subsequent amplifier operates stably in the subthreshold region across the entire temperature range of -40°C to 80°C, maintaining its input high crossover voltage at approximately 0.32V. It should be understood that the time constant ratio k of the charging branch to the discharging branch can also be set to other values ​​according to actual needs, and this is not limited here.

[0064] Specifically, the circuit diagram of the first RC network module 100 of the relaxation oscillator in one embodiment of this application is as follows: Figure 2 As shown, Figure 2 It includes a first asymmetric RC network 110, a second asymmetric RC network 120, and a signal multiplexing unit 130. The first asymmetric RC network 110 and the second asymmetric RC network 120 are two sets of RC networks that are symmetrical and have identical structures. Each set consists of a capacitor C, a switch, resistors (including R and R / 2), and a control voltage V. PLS Composition. Connected to the top power supply V. TOP and bottom power supply V BTM A signal path is formed and cross-driven by a pair of complementary clock signals, generating a first voltage signal pair and a second voltage signal pair V with complementary phases, respectively. X1 / V Y1 and V X2 / V Y2 The generated first voltage signal pair and second voltage signal pair are input to the signal multiplexing unit 130, and finally output a pair of first target voltage signal pairs with constant common-mode voltage and constant high-level voltage at the crossover point.

[0065] The signal multiplexing unit 130 is used to select the voltage pair with the higher common-mode voltage from the first voltage signal pair and the second voltage signal pair according to the phase of the clock signal, and output it to the first clock feedback module 200 as the first target voltage signal pair.

[0066] Specifically, the input to the signal multiplexing unit 130 is a first voltage signal pair (V) from the first asymmetric RC network 110. X1 / V Y1 ) and the second voltage signal pair (V) from the second asymmetric RC network 120 X2 / V Y2 The selection logic of the signal multiplexing unit 130 is directly controlled by the current phase state of the first clock signal output by the first clock feedback module 200. The signal multiplexing unit 130 responds to the clock signal (i.e., Figure 2 CLK B and The phase of the first clock signal is selected, and the voltage pair with the higher common-mode voltage among the first and second voltage signal pairs is chosen as the target voltage signal pair. In one embodiment, when the first clock signal is low, the first asymmetric RC network 110 is in a charging state, and its output V X1 / V Y1 The signal pair has a high crossover voltage; while the second asymmetric RC network 120 is in a discharging state, and its output V X2 / V Y2 The signal pair has a low crossover voltage. At this time, the signal multiplexing unit 130 connects the first voltage signal pair V. X1 / V Y1 The second voltage signal pair is blocked at its output terminal. When the first clock signal is high, the operating state is completely reversed. The second asymmetric RC network 120 switches to charging, outputting a V with a high crossover point. X2 / V Y2 The first asymmetric RC network 110 switches to discharge. At this time, the signal multiplexing unit 130 synchronously switches, connecting the second voltage signal pair V. X2 / V Y2 The signal is directed to its output terminal, and the first voltage signal pair is blocked. It should be understood that the selection logic of the signal multiplexing unit 130 can also be adjusted as needed, so that when the first clock signal is high, the second voltage signal pair is connected; when the first clock signal is low, the first voltage signal pair is connected.

[0067] Figure 3 This is a timing waveform diagram of the first RC network module 100 of a relaxation oscillator according to an embodiment of this application over a continuous time period. Figure 3 As shown, the dynamic operation of the first resistor-capacitor network module 100 over a complete clock cycle is illustrated. Figure 3 The horizontal axis represents time, marked with two time periods: T1 and T2. Figure 3The upper part consists of the first voltage signal pair of the first asymmetric RC network 110 and the second voltage signal pair of the second asymmetric RC network 120 at V X1 V Y1 V X2 and V Y2 The timing waveform diagram. From Figure 3 It can be seen from V X1 and V Y1 During time interval T1, the code is submitted to V. CM,H V X2 and V Y2 During time interval T1, the code is submitted to V. CM,L ;and V X1 and V Y1 During time interval T2, the code is submitted to V. CM,L V X2 and V Y2 During time interval T2, the code is submitted to V. CM,H Based on the aforementioned changes in the intersection points of different voltage signal pairs, the signal multiplexing unit 130 selects signal pairs with high intersection voltages in different time periods. Therefore, the signal multiplexing unit 130 selects V during time period T1. X1 and V Y1 As output, select V within time period T2. X2 and V Y2 As outputs, the final outputs of the signal multiplexing unit 130 are V1 and V2.

[0068] The first clock feedback module 200 is used to compare the amplitudes of the two voltage signals in the first target voltage signal pair with preset thresholds respectively, and output the first clock signal and the second clock signal to the first RC network module 100 according to the comparison results.

[0069] The core function of the first clock feedback module 200 is to capture the crossover point of the first target voltage signal pair and convert the voltage value into a stable digital signal, while simultaneously completing closed-loop feedback to drive oscillation. Specifically, the first clock feedback module 200 receives the first target voltage signal pair from the first RC network module 100 and compares the relative amplitudes of the two voltage signals in the first target voltage signal pair. This comparison can be achieved in various ways, such as absolute comparison using a preset threshold, direct detection of relative zero-crossing points using a differential comparator, and utilizing the metastable triggering characteristics of digital logic units such as latches.

[0070] Optionally, the first clock feedback module 200 compares the two voltage signals in the first target voltage signal pair with preset thresholds to obtain a set signal and a reset signal, respectively. Simultaneously, it performs a state flip based on the set signal and the reset signal to output a clock signal, which includes a pair of complementary first clock signals and a second clock signal. This pair of clock signals is fed back to the first RC network module 100 to control the switching of the charging and discharging switch inside the first RC network module 100.

[0071] The aforementioned relaxation oscillator employs two identical asymmetric RC networks driven by complementary clocks, combined with phase-synchronized signal selection. This integrates signals with different common-mode voltages generated by the two networks at different times into a single continuous signal with a constant common-mode voltage. This avoids noise caused by transient circuit responses resulting from periodic jumps in the common-mode voltage of the signal source, forming the basis for improving the frequency stability of the relaxation oscillator. The integrated, constant common-mode voltage continuous signal operates within the clock feedback module, resulting in a low-noise, high-precision relaxation oscillator.

[0072] Optionally, in one embodiment, the relaxation oscillator further includes a duty cycle control module 300; the duty cycle control module 300 includes an enable signal generation unit 310, a phase detection unit 320, and a feedback control unit 330; the input terminal of the enable signal generation unit 310 is connected to the output terminal of the first clock feedback module 200, the output terminal of the enable signal generation unit 310 is connected to the input terminal of the phase detection unit 320, the output terminal of the phase detection unit 320 is connected to the input terminal of the feedback control unit 330, and the output terminal of the feedback control unit 330 is connected to the enable terminal of the first clock feedback module 200; wherein:

[0073] The enable signal generating unit 310 is used to generate and output periodic enable pulses according to the clock signal; the phase detection unit 320 is used to obtain the phase difference between the falling edge of the enable pulse and the rising edge of the second clock signal; the feedback control unit 330 outputs a control signal to the enable signal generating unit according to the phase difference; the control signal is used to adjust the enable pulse.

[0074] The core task of the duty cycle control module 300 is to generate an enable window for the high-power modules in the relaxation oscillator. The duty cycle control module 300 mainly consists of an enable signal generation unit 310, a phase detection unit 320, and a feedback control unit 330. The enable signal generation unit 310 receives the clock signal from the first clock feedback module 200 and generates an initial, periodic enable pulse accordingly. The phase detection unit 320 captures the time difference between the falling edge of the enable pulse and the rising edge of the inverted signal of the master clock, i.e., the phase error. The feedback control unit 330 receives the phase error information from the phase detection unit 320 and converts it into a control signal. This control signal is fed back to the enable signal generation unit 310 to dynamically adjust its internal delay chain or pulse generation logic, thereby aligning the falling edge of the enable pulse with the rising edge of the inverted signal of the master clock.

[0075] This results in a deterministic and stable outcome, locking the effective pulse width of the enable pulse to 25% of the master clock cycle, and allowing its activation time to be set 0.75 half-cycles after the rising edge of the master clock. This ensures that the high-power amplifier is powered on only during the critical period when signals are about to cross over and require the most comparisons in each oscillation cycle, while remaining in a power-off energy-saving state for the remaining 75% of the time.

[0076] Figure 4 This is a structural diagram of a relaxation oscillator duty cycle control module 300 according to an embodiment of this application. Figure 4 As shown, there is a first clock signal (Clock, CLK) and a second clock signal complementary to the first clock signal. The input is sent to the enable signal generation unit 310, which generates periodic enable pulses EN. These enable pulses are designed to last for 1 / 4 of a fixed time range and are used for duty cycle adjustment and fixed delay control in subsequent circuits. Next, the enable pulses are processed by signal processing to obtain a comparison signal CMP. This comparison signal CMP is then compared with a second clock signal. The phase detection unit 320 compares the results to generate Q. A and Q B And through Q A and Q B This drives a subsequent charge pump, thereby generating a control voltage V in the feedback control unit 330. CP .

[0077] Figure 5 This is a timing waveform diagram of the duty cycle control module 300 in a relaxation oscillator according to an embodiment of this application. Figure 5This demonstrates the complete working process from analog voltage comparison to digital logic control. First, the first target voltage signal pair V1 and V2, output by the first RC network module 100, alternately rises within time periods T1 and T2. During this change, the two voltage signals are compared with the high crossover point voltage. Then, the enable pulse EN is designed to be 1 / 4 of a fixed time range, and after signal processing, a comparison signal CMP is obtained. Next, the phase difference between the comparison signal CMP and the second clock signal is output by the phase detection unit 320. Based on this phase difference, the feedback control unit 330 outputs a Q signal to control the charging and discharging of the charge pump. A With Q B Signal, Q A With Q B The signal will drive the charge pump to charge or discharge the capacitor to generate a control voltage V. CP .

[0078] Figure 6 This is a simulation result graph of the enable pulse enable rate in a relaxation oscillator according to an embodiment of this application. The horizontal axis in the graph represents the temperature, ranging from -40°C to 80°C, and the vertical axis represents the enable pulse enable rate. Figure 6 The simulation results are presented for three process corners: SS, TT, and FF. Specifically, SS stands for Slow-Slow process corner, suitable for low-power devices; TT stands for Typical-Typical process corner, with performance close to design expectations; and FF stands for Fast-Fast process corner, used for high-performance computing scenarios. Figure 6 It can be observed that the enable rate of the enable pulse remains highly stable across the entire temperature range under different process angles, fluctuating slightly around the design target value of 25%, with a maximum deviation of no more than 5.5%. This proves that the duty cycle control module 300 has excellent robustness to process and temperature changes and can achieve the design target of stabilizing the enable time duty cycle at about 1 / 4 cycle.

[0079] The duty cycle control module 300 enables a significant reduction in the power consumption of the relaxation oscillator without sacrificing timing performance, and is particularly suitable for ultra-low voltage applications where power consumption is extremely sensitive.

[0080] In addition, in one embodiment, the feedback control unit 330 further includes a charge pump subunit and a capacitor subunit; the charge pump subunit is used to charge and discharge the capacitor in the capacitor subunit; the capacitor subunit is used to output a control signal and adjust the enable pulse according to the control signal.

[0081] The feedback control unit 330 outputs a control signal to the enable signal generation unit based on the phase difference. This control signal is a variable voltage signal used to adjust the internal delay of the enable signal generation unit 310. Specifically, the charge pump subunit converts the phase error information from the phase detection unit 320 into a control signal, thereby charging or discharging the capacitor in the capacitor subunit according to the control signal. If the falling edge of the enable pulse leads the rising edge of the second clock signal, the charge pump subunit injects current into the capacitor subunit, raising the voltage across the capacitor; conversely, if the falling edge of the enable pulse lags behind the rising edge of the second clock signal, the charge pump subunit draws current from the capacitor subunit, lowering its voltage.

[0082] The voltage across the capacitor sub-unit is the control voltage (V) used to achieve delay control via the control signal. CP The control voltage is fed back to the enable signal generation unit 310. By adjusting the control voltage, the internal delay time of the delay unit can be continuously changed, thereby dynamically adjusting the generation time of the enable pulse, so that the falling edge of the enable pulse gradually approaches and aligns with the rising edge of the second clock signal. Finally, the activation window of the enable pulse is controlled at a predetermined position in each oscillation cycle, and its pulse width is stabilized at the target value.

[0083] By using the charge pump subunit and capacitor subunit in the feedback control unit 330, the generation time of the enable pulse is dynamically adjusted by the control signal, and the effective window of the enable pulse is locked at a fixed phase in each oscillation cycle, thereby realizing on-demand power supply to the amplifier. While ensuring the reliability of signal processing, the power consumption of the relaxation oscillator is reduced and the energy utilization efficiency is improved.

[0084] In one embodiment, the first clock feedback module 200 includes: a signal shaping unit and a latching unit; the input terminal of the signal shaping unit is connected to the output terminal of the first RC network module 100; the output terminal of the signal shaping unit is connected to the input terminal of the latching unit, and the output terminal of the latching unit is connected to the input terminal of the first RC network module 100; wherein:

[0085] The signal shaping unit is used to receive the first signal and the second signal in the first target voltage signal pair, compare the first signal with a preset first threshold and output a set signal according to the comparison result; compare the second signal with a preset second threshold and output a reset signal according to the comparison result; the latching unit is used to output a clock signal to the first resistor-capacitor network module 100 in response to the set signal and the reset signal.

[0086] The signal shaping unit serves as the interface circuit between analog signals and digital logic in the relaxation oscillator. Its core function is to convert the continuous analog voltage signal from the first RC network module 100 into a digital pulse signal with a defined logic level, which drives the subsequent digital latch and feedback circuits. The signal shaping unit compares the input voltage with a preset reference threshold using an internal comparator circuit, and uses logic circuits such as inverters to shape the first target voltage signal from the first RC network module 100 into a digital signal with steep edges and a defined logic, thereby providing a stable and reliable digital trigger source for the oscillation loop of the relaxation oscillator.

[0087] Specifically, upon receiving the first and second signals from the first target voltage signal pair from the first RC network module 100, the signal shaping unit internally compares the first signal with a preset first threshold and the second signal with a preset second threshold. When the first signal exceeds the preset first threshold, it outputs a high level, which, after being shaped by an inverter, generates a valid set signal S0. When the second signal exceeds the preset second threshold, it outputs a high level, which, after being shaped by another inverter, generates a valid reset signal R0. The set signal and reset signal are respectively sent to the S0 and R0 terminals of the latch unit to control the toggling of the clock output state.

[0088] The latch unit adopts an SR latch structure, with its set (S0) and reset (R0) terminals receiving the set and reset signals, respectively. The output results of the set and reset signals for different latch units are shown in Table 1. When the set signal is valid, the latch unit outputs a high-level first clock signal; when the reset signal is valid, the output is a low-level first clock signal; when both are valid, the previous state is maintained. The output of the latch unit directly constitutes the first clock signal (CLK), and a complementary second clock signal is generated through an inverter. Both feed back to the first RC network module 100, controlling the charging and discharging switching timing of the first asymmetric RC network 110 and the second asymmetric RC network 120.

[0089] Table 1

[0090]

[0091] By presetting the voltage values ​​of the first and second thresholds in the signal shaping unit, it is possible to ensure that the state switching is triggered at a predetermined intersection point of the RC network charge-discharge curve, thereby achieving stable oscillation with controllable frequency. Furthermore, the introduction of the latch unit effectively avoids false triggering caused by comparator output glitches or unstable states, improving the anti-interference capability and timing stability of the relaxation oscillator.

[0092] In one embodiment, the signal shaping unit, in response to an enable pulse, compares a first signal with a corresponding preset first threshold and compares a second signal with a corresponding preset second threshold.

[0093] Specifically, in one embodiment, the signal shaping unit can operate in two different modes under the modulation of an enable pulse: During the active period of the enable pulse, the signal shaping unit is in signal processing mode, where the internal selector selects the first and second input signals, compares them with preset first and second thresholds respectively, and outputs corresponding set and reset signals. During the inactive period of the enable pulse, the signal shaping unit switches to static holding mode, where the internal selector selects preset high-level and low-level references, and the output is locked at two preset static levels. The enable pulse can be a pulse with a pre-configured enable time set according to requirements, or it can be an enable pulse generated by the duty cycle control module 300.

[0094] Figure 7 This is a circuit diagram of the signal shaping unit in a relaxation oscillator according to one embodiment of this application. Its core function is to shape the input signal V under the control of an enable pulse. AMP1 and V AMP2 This is converted into set and reset signals suitable for driving subsequent digital logic. The input signal V here... AMP1 and V AMP2 It can be the first target voltage signal pair output by the signal multiplexing unit 130, or the second-stage amplified signal pair output by the signal amplification module 400. Figure 7 In the circuit structure, the high-level reference V TOP With low-level reference V BTM This provides a stable common-mode bias point for the first and second voltage signal pairs. When the enable pulse is active, the input signal V... AMP1 and V AMP2 The circuit is selected by a controlled switch and enters a comparator and shaping circuit composed of cross-coupled transistors. The entire circuit uses V... DD Using 0.5V as the operating power supply, reliable comparison speed and noise tolerance are ensured even at ultra-low supply voltages through the synergistic optimization of transistor size and bias.

[0095] The signal shaping unit embodies the key design concept of achieving low-latency and high-robust signal processing in ultra-low voltage, high-precision timing systems: achieving a balance between power consumption and performance through dynamic enable control, improving comparison speed and anti-interference capability through a fully differential structure and positive feedback, and ensuring a reliable interface with subsequent digital logic through a level recovery circuit.

[0096] In this embodiment, dynamic power management of the signal shaping unit is achieved through enable control. The comparison function is activated only during the brief time window when voltage crossover needs to be detected in each oscillation cycle, while it is placed in a low-power static hold mode for most of the remaining time. This relaxes the overall power consumption of the oscillator, while the preset output level ensures stability during the shutdown period.

[0097] In one embodiment, the first clock feedback module 200 further includes: a clock boosting unit, the input of which is connected to the output of the latching unit, and the output of which is connected to the input of the first RC network module 100; wherein, the clock boosting unit is used to boost the voltage swing and power of the clock signal and output the enhanced clock signal to the first RC network module 100.

[0098] In one embodiment, the clock boosting unit can improve clock signal performance through two stages of processing. First, the first stage uses a cross-coupled level shifter circuit to convert the input low-voltage signal into an intermediate signal with a higher voltage swing. The second stage uses inverters with progressively larger device sizes to amplify the power of the intermediate signal, significantly enhancing the clock signal's ability to drive capacitive loads. The clock boosting unit ensures that the clock signal can reliably drive the switching transistors in the RC network while maintaining its fast edge characteristics, thereby improving the overall stability of the relaxation oscillator.

[0099] In addition, in one embodiment, the relaxation oscillator further includes a signal amplification module 400, which includes a feedback amplification unit and a threshold voltage amplification unit. The input terminal of the feedback amplification unit is connected to the output terminal of the first RC network module 100, the output terminal of the feedback amplification unit is connected to the input terminal of the threshold voltage amplification unit, and the output terminal of the threshold voltage amplification unit is connected to the input terminal of the first clock feedback module 200.

[0100] The feedback amplification unit amplifies the differential-mode component of the first target voltage signal pair and compares the common-mode voltage of the first target voltage signal pair with a preset reference voltage. Based on the comparison result, it adjusts the first target voltage signal pair so that the common-mode voltage approaches the preset reference voltage, thus obtaining a first-stage amplified signal pair. The first-stage amplified signal pair is then input to the threshold voltage amplification unit. The threshold voltage amplification unit amplifies the differential-mode component of the first-stage amplified signal pair and adjusts the first-stage amplified signal pair according to a preset first threshold or a preset second threshold, thereby raising the transition point of the first-stage amplified signal pair, thus obtaining a second-stage amplified signal pair. The transition point is the voltage value when the difference between the two voltage signals in the first-stage amplified signal pair is less than the preset first transition threshold.

[0101] The feedback amplification unit employs a differential amplifier with a common-mode feedback structure. It receives the first target voltage signal pair from the signal multiplexing unit 130 and forms a transconductance amplification stage through an active load and a tail current source. Simultaneously, the feedback amplification unit incorporates a common-mode feedback loop to monitor the common-mode voltage of the output node in real time, compares it with a preset reference voltage, and dynamically adjusts the gate voltage of the load transistor through the feedback network to stabilize the output common-mode voltage at the preset reference voltage, thus obtaining the first-stage amplified signal pair.

[0102] Figure 8 This is a circuit schematic of the feedback amplification unit in a relaxation oscillator according to one embodiment of this application. The feedback amplification unit integrates common-mode feedback and duty cycle control functions, enabling high-stability, low-distortion signal amplification at ultra-low voltage. The circuit adopts a fully differential structure, amplifying the first target voltage signals V1 and V2 through complementary differential input stages composed of transistors, and finally outputting the first-stage amplified signal V1. 01 and V 02 The entire circuit operates under ultra-low voltage conditions. The feedback amplification unit includes a common-mode feedback module, which extracts the common-mode voltage V from the output voltage through a resistor network. CMFB and with the externally provided reference voltage V REF The comparison is performed. The generated error signal is converted into a control current by a transconductance amplifier, and then integrated and filtered by a low-pass filter to generate the bias point M of the feedback control voltage dynamic adjustment output stage. P This locks the output common-mode voltage to the reference voltage, effectively suppressing common-mode drift caused by power supply fluctuations or temperature changes. The feedback amplification unit also includes a duty cycle control circuit for calibrating the duty cycle of the first-stage amplified signal pair in timing-sensitive applications. The duty cycle control circuit monitors transient changes at the output node or internal nodes using transistors and adjusts the conduction state based on the bias voltage, thereby controlling the equivalent impedance or charging / discharging current of the signal path and dynamically adjusting the rise and fall times of the output waveform to calibrate the output pulse duty cycle.

[0103] In addition, the feedback amplifier unit circuit also includes a low-pass filter with a cutoff frequency of 40kHz, where R FB1 For 200kΩ, C FB1 It has a capacitance of 20pF and is used to suppress high-frequency noise in the feedback loop and improve the stability of the relaxation oscillator.

[0104] The threshold voltage amplifier unit is connected after the feedback amplifier unit. It mirrors the load conditions of the subsequent inverter through a replication circuit to generate a feedback voltage that dynamically adjusts the amplifier's bias point. This ensures that the switching threshold of the second-stage amplified signal pair output by the threshold voltage amplifier unit automatically tracks the actual switching threshold of the inverter in the subsequent signal shaping unit. Consequently, while amplifying the differential signal, the threshold voltage amplifier unit raises the output switching point to a position slightly higher than the inverter threshold, ensuring that the signal input to the latch unit remains within the valid logic range and avoiding timing errors caused by threshold drift.

[0105] Figure 9 This is a circuit diagram of the threshold voltage amplification unit in a relaxation oscillator according to one embodiment of this application. Figure 9 As shown, the threshold voltage amplification unit circuit adopts a fully differential structure. The first stage amplifies the signal to V. 01 and V 02 After being amplified by a differential input stage composed of complementary transistors, V is output from two output terminals. AMP1 and V AMP2 The power supply is V. TOP With V BTM Provided to ensure normal operation in low-voltage environments. The threshold voltage amplification unit includes a threshold voltage tracking module for real-time monitoring and compensation of transistor threshold drift caused by process, voltage, and temperature variations. Figure 9 The threshold voltage tracking part dynamically generates the regulating voltage V through a replication structure and feedback loop. FB After being smoothed by a filtering network, the bias conditions of the main amplifier are automatically adjusted to maintain stable gain and bandwidth across the entire operating range. Optionally, the threshold voltage amplification unit also includes a common-mode feedback subunit, responsible for stabilizing the common-mode voltage of the differential output. The common-mode feedback subunit extracts the common-mode signal from the two output terminals through a resistor network and compares it with an externally provided reference voltage V. REF A comparison is then made. After amplifying and integrating the error signal generated by the common-mode feedback subunit, a control voltage is generated to dynamically adjust the output stage bias of the main amplifier, thereby locking the output common-mode voltage to the target reference voltage and effectively suppressing common-mode noise and drift. The threshold voltage amplification unit also includes a duty cycle control subunit, which is used to calibrate the timing characteristics of the second-stage amplified signal pair. Specifically, the duty cycle control subunit monitors the waveform changes of the output signal (second-stage amplified signal pair) through internal transistors and adjusts the equivalent impedance of relevant nodes to control the rise and fall times of the signal, achieving dynamic optimization of the output pulse duty cycle and ensuring accurate timing even at low voltages.

[0106] In addition, the threshold voltage amplification unit circuit also includes a low-pass filter with a cutoff frequency of 0.32MHz, where R FB2For 100kΩ, C FB2 It has a power of 5pF and is used to suppress high-frequency noise in the feedback loop and improve stability.

[0107] The signal amplification module 400 can work collaboratively under ultra-low voltage conditions. The feedback amplification unit first stabilizes and amplifies the first target voltage signal output from the first RC network module 100 and locks the common-mode operating point. The threshold voltage amplification unit further provides gain and achieves adaptive calibration of the output switching point. This effectively solves the key problems of amplifier operating point drift and interface mismatch with digital circuits under ultra-low voltage conditions, providing a stable and reliable amplified signal for subsequent comparison and latching circuits.

[0108] In an oscillator based on a resistor-capacitor (RC) network, the ideal oscillation frequency should be determined solely by the temperature coefficient of the RC unit. However, in practical implementations, the comparator, buffer, and subsequent control circuitry introduce delays during signal processing, causing a significant timing deviation between the actual voltage signal waveform and its ideal value. This delay exists between the switching moments of the capacitor charging / discharging signal and the final clock signal, resulting in an increase of t in the actual oscillation period. delay This error term causes the frequency to deviate from the theoretical value. Under ultra-low voltage operating conditions below 0.5V, this delay effect is further amplified, introducing a significant frequency error. Furthermore, t delay It is highly sensitive to changes in process, voltage, and temperature. Its fluctuations are further aggravated by changes in process, voltage, and temperature, which seriously restricts the accuracy and robustness of the oscillator in various application environments.

[0109] Based on this, in one embodiment, the relaxation oscillator further includes a temperature compensation module 500: wherein the temperature compensation module 500 includes a second RC network module 510 with the same structure as the first RC network module 100, a second clock feedback module 520 with the same structure as the first clock feedback module 200, a measurement circuit unit 530, and a compensation voltage generation unit 540; the time constants of the capacitors and resistors in the second RC network module 510 are less than the time constants of the capacitors and resistors in the first RC network module 100; the output terminal of the second RC network module 510 is connected to the input terminal of the second clock feedback module 520, the output terminal of the second clock feedback module 520 is connected to the input terminal of the measurement circuit unit 530, the output terminal of the measurement circuit unit 530 is connected to the input terminal of the compensation voltage generation unit 540, and the output terminal of the compensation voltage generation unit 540 is connected to the input terminal of the first RC network module 100; wherein:

[0110] The second RC network module 510 receives an external power supply signal and a third clock signal and a fourth clock signal with opposite phases output by the second clock feedback module 520, and outputs a third voltage signal pair and a fourth voltage signal pair. Based on the phases of the third and fourth clock signals, it selects the voltage pair with the higher common-mode voltage from the third and fourth voltage signal pairs as the second target voltage signal pair and outputs it to the second clock feedback module 520. The second clock feedback module 520 compares the amplitudes of the two voltage signals in the second target voltage signal pair with preset thresholds, and outputs the results based on the comparison. The third and fourth clock signals are sent to the second RC network module 510; the measurement circuit is used to measure the transition time of the two voltage signals in the second target voltage signal pair; the transition time is the time length between the previous moment when the difference between the two voltage signals in the second target voltage signal pair is less than the preset second transition threshold and the current moment; the compensation voltage generation unit 540 is used to generate a compensation voltage based on the time difference between the transition time and the theoretical transition time, and output the compensation voltage to the second RC network module 510, so as to adjust the current of the resistor in the first RC network through the compensation voltage.

[0111] The second RC network module 510 is a complete copy of the first RC network module 100, but its resistor and capacitor time constants are set to half of their original values. Driven by the copied third and fourth clock signals, the second RC network module 510 generates a third voltage signal pair or a fourth voltage signal with a waveform similar to the first RC network module 100 but with double the charging speed. These signals are then output to the second target voltage signal pair, the second clock feedback module 520, through the same multiplexing logic. The second clock feedback module 520 adopts the same structure as the first clock feedback module 200, used to establish self-excited oscillation in the copy path (i.e., the path where the second RC network module 510 is located). However, because the time constants of the resistors and capacitors in the second RC network module are halved, the oscillation frequency in the second RC network module 510 is approximately twice that of the first RC network module 100. The clock signal output by the second RC network module 510 is simultaneously fed back to the first RC network module 100, forming a copied oscillation loop.

[0112] The core of the measurement circuit unit 530 is a time-to-digital converter, which records the time t required from the triggering of the replica oscillation loop clock edge to the second target voltage signal pair meeting the transition condition (i.e., the difference between the two voltage signals is less than a preset second transition threshold) through a counter. osc This time actually includes the delay t introduced by the comparator, buffer, and latch circuitry in the copy path. delay And the charging time t of the accelerated resistor and capacitor. charge The actual oscillation period is t. osc =t charge +tdelay The compensation voltage generation unit 540 generates voltage based on the measured t. osc The theoretical value t of the ideal resistance-capacitance charging time charge The delay error is calculated as t. delay The measurement circuit unit 530 also integrates a digital-to-analog converter for converting t... delay Converted to the corresponding analog compensation voltage (V) PLS The simulated compensation voltage is fed back to the control terminal of the adjustable resistor array in the first RC network module 100, dynamically adjusting its equivalent resistance value, thereby offsetting t in real time during the main path charging time. delay The resulting timing error.

[0113] Figure 10 This is a system block diagram of a relaxation oscillator temperature compensation module 500 according to an embodiment of this application. The temperature compensation module 500 achieves real-time measurement and dynamic compensation of inherent delays in the circuit by constructing a replica path with the same structure as the main oscillation path but a faster operating speed. The temperature compensation module 500 includes a second RC network module 510, which serves as a replica of the first RC network module 100. By setting the resistance value of the second RC network module 510 to be less than that of the first RC network module 100, and / or setting the capacitance value of the second RC network module 510 to be less than that of the first RC network module 100, the charging time constant of the second RC network module 510 is reduced, thereby accelerating the operating speed. A second clock feedback module 520, with the same structure as the first clock feedback module 200, forms a complete replica oscillation loop with the second RC network module 510. A measurement circuit unit 530, connected to the output of the second clock feedback module 520, is used to measure the actual period of the oscillation loop of the temperature compensation module 500 and extract the circuit delay component from it. The compensation voltage generation unit 540 receives delay information from the measurement circuit unit 530 and converts it into an analog compensation voltage.

[0114] Figure 11 This is a frequency deviation graph illustrating the effect of temperature compensation module 500 on the frequency of a relaxation oscillator as a function of temperature, according to one embodiment of this application. The solid line in the graph represents the frequency deviation curve after using temperature compensation module 500, while the dashed line represents the baseline curve without temperature compensation module 500. The tests covered the entire temperature range from -40℃ to 80℃ and three typical process corners: TT, FF, and SS. Figure 11 It can be clearly observed that after using the temperature compensation module 500, the improvement is greater than 58%, and the frequency deviation under all process corners is significantly suppressed, bringing the overall deviation closer to the zero-deviation baseline. Especially under extreme high and low temperature conditions, the temperature compensation module 500 can still maintain the frequency deviation close to zero, while the deviation can reach more than 1.5% without the temperature compensation module 500.

[0115] Therefore, the temperature compensation module achieves real-time monitoring and dynamic compensation of the inherent delay of the circuit by establishing a replicated path with the same path structure but half the time constant. This improves the frequency stability of the relaxation oscillator across the entire temperature range.

[0116] In one embodiment, this application implements a relaxation oscillator chip based on a 65nm standard complementary metal-oxide-semiconductor process, and its structural micrograph is shown below. Figure 12 As shown, the relaxation oscillator chip includes a first RC network module, a first clock feedback module, a duty cycle control module, a signal amplification module, and a temperature compensation module, with a total effective area of ​​0.087 mm², of which the signal amplification module occupies 35.6% of the total area. The relaxation oscillator operates at 2.35 MHz, and its power consumption is 13.7 μW under 0.5 V power supply voltage and room temperature conditions. Simulation results show that the first RC network module and the signal amplification module account for 33.3% and 36.1% of the total power consumption, respectively. Specifically, the area proportions of the first RC network module, the first clock feedback module, the duty cycle control module, the signal amplification module, and the temperature compensation module in the overall structure are 11.3%, 8.8%, 26.7%, 35.6%, and 17.6%, respectively, and their power consumption proportions are 33.3%, 10.2%, 10.4%, 36.1%, and 10.4%, respectively.

[0117] To adapt to testing equipment, the chip integrates an independently powered (1V) on-chip level shifter and output buffer to increase the signal swing and drive peripheral instruments. Testing of six chip samples showed an oscillation frequency of 2.35MHz. Figure 13 The frequency deviation curves of different sample chips of a relaxation oscillator according to an embodiment of this application are shown, with the maximum deviation not exceeding 3% in the temperature range of -40°C to 80°C. Figure 14 This demonstrates the frequency deviation within a supply voltage range of 0.5V to 0.59V, with an average deviation not exceeding 4.18% and a normalized voltage sensitivity of 17.4%. Due to the introduction of the temperature compensation module, the relaxation oscillator exhibits excellent anti-interference capability against power supply voltage fluctuations in the subthreshold operating region, making it particularly suitable for self-powered ultra-low power systems. Furthermore, the period jitter test results of this relaxation oscillator are as follows... Figure 15 As shown, the effective value of the jitter period is 168ps, indicating that the relaxation oscillator still has excellent timing stability under ultra-low voltage conditions.

[0118] Figure 16 This is a flowchart of a frequency stabilization method for a relaxation oscillator according to an embodiment of this application. Figure 16 As shown, the frequency stabilization method for this relaxation oscillator includes the following steps:

[0119] Step S101: Input the clock signal and the power signal into the first asymmetric RC network and the second asymmetric RC network, so that the first asymmetric RC network and the second asymmetric RC network output the first voltage signal pair and the second voltage signal pair respectively; the clock signal includes the first clock signal and the second clock signal with opposite phases; the first asymmetric RC network and the second asymmetric RC network have the same structure.

[0120] The system receives a clock signal from the first clock feedback module and an external power supply signal, where the clock signals include a first clock signal and a second clock signal with opposite phases. Using two identical asymmetric RC networks, the external power supply is alternately charged and discharged under the control of the first and second clock signals, respectively, thereby outputting a first voltage signal pair and a second voltage signal pair. By designing the resistance ratio of its charging and discharging branches, the asymmetric RC network ensures that the output voltage waveform crosses at a preset common-mode voltage point, providing a stable input bias condition for the subsequent single-path comparator.

[0121] Step S102: Based on the phase of the clock signal, select the voltage pair with the higher common-mode voltage from the first voltage signal pair and the second voltage signal pair as the first target voltage signal pair.

[0122] Based on the current phase of the clock signal, determine the currently valid voltage signal pair. If the current phase corresponds to a valid first clock signal, then the first voltage signal pair is selected as the comparison object; if it corresponds to a valid second clock signal, then the second voltage signal pair is selected as the comparison object.

[0123] Step S103: Compare the amplitudes of the two voltage signals in the first target voltage signal pair with preset thresholds respectively, and adjust the clock signal according to the comparison results.

[0124] The first signal from the selected first target voltage signal pair is compared with a preset first threshold, and a set signal is generated based on the comparison result. Simultaneously, the second signal from the selected voltage signal pair is compared with a preset second threshold, and a reset signal is generated based on the comparison result. The first and second thresholds can be set to the same or different voltage values ​​according to circuit design requirements. Based on the logic states of the set and reset signals, the latch unit updates its output state, generating updated first and second clock signals, which are then fed back to the RC network module to control the switching of its charging and discharging states, thereby forming a closed-loop self-excited oscillation.

[0125] According to steps S101 to S103, firstly, a clock signal and a power supply signal are input to a first asymmetric RC network and a second asymmetric RC network, so that the first asymmetric RC network and the second asymmetric RC network output a first voltage signal pair and a second voltage signal pair, respectively. The clock signal includes a first clock signal and a second clock signal with opposite phases. The first asymmetric RC network and the second asymmetric RC network have the same structure. Subsequently, based on the phase of the clock signal, the voltage pair with the higher common-mode voltage among the first voltage signal pair and the second voltage signal pair is selected as the first target voltage signal pair. Finally, the amplitudes of the two voltage signals in the first target voltage signal pair are compared with preset thresholds, and the clock signal is adjusted according to the comparison results. This method uses a pair of asymmetric swing-boosting RC networks with identical structures and driven by complementary clocks to generate two sets of voltage signal pairs with opposite phases. Combined with a phase-synchronized signal selection mechanism, the signal pair with a common-mode voltage stable at a preset high-level intersection point is always selected for output within each half-oscillation cycle. This transforms the noise introduced by the two RC networks at different times into a highly correlated signal in time, which is then effectively canceled out in the subsequent differential processing. This suppresses the period jitter caused by the accumulation of uncorrelated noise in the traditional dual amplifier architecture, and improves the frequency stability and phase noise performance of the relaxation oscillator under ultra-low voltage conditions.

[0126] This application also provides a self-powered IoT device, which includes embodiments of any of the relaxation oscillators described above. This relaxation oscillator can operate stably at an ultra-low power supply voltage of 0.5V and achieve a cycle jitter as low as 390ppm. This characteristic makes it particularly suitable for IoT nodes powered by weak ambient energy (such as radio frequency energy, solar energy, or thermal energy). In traditional ambient energy harvesting systems, nodes often struggle to directly use high-power, high-startup-voltage clock sources due to low and unstable power supply voltages. The relaxation oscillator of this application can be directly integrated into the back end of the energy harvesting circuit, eliminating the need for complex voltage boosting or regulating modules. It can provide stable and accurate timing signals to the microcontrollers, sensors, or wireless communication modules in the node, thereby ensuring reliable operation and efficient synchronization of the relaxation oscillator under energy-constrained conditions, significantly improving the adaptability, energy efficiency, and overall reliability of IoT terminals in real-world environments.

[0127] It should be understood that the specific embodiments described herein are merely illustrative of the application and not intended to limit it. All other embodiments derived by those skilled in the art based on the embodiments provided in this application without inventive effort are within the scope of protection of this application.

[0128] Obviously, the accompanying drawings are merely some examples or embodiments of this application. Those skilled in the art can apply this application to other similar situations based on these drawings without any creative effort. Furthermore, it is understood that although the work done in this development process may be complex and lengthy, for those skilled in the art, certain design, manufacturing, or production modifications made based on the technical content disclosed in this application are merely conventional technical means and should not be considered as insufficient disclosure of this application.

[0129] The term "embodiment" in this application refers to a specific feature, structure, or characteristic described in connection with an embodiment that may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily imply the same embodiment, nor does it imply that it is mutually exclusive with or independent of other embodiments. It will be clearly or implicitly understood by those skilled in the art that the embodiments described in this application may be combined with other embodiments without conflict.

[0130] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of patent protection. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the appended claims.

Claims

1. A relaxation oscillator, characterized in that, The relaxation oscillator includes: a first RC network module and a first clock feedback module; the first RC network module includes a first asymmetric RC network, a second asymmetric RC network, and a signal multiplexing unit with identical structures; the output terminal of the first RC network module is connected to the input terminal of the first clock feedback module; the output terminal of the first clock feedback module is connected to the input terminal of the first RC network module; wherein, The first asymmetric RC network and the second asymmetric RC network are used to receive the external power supply signal and the clock signal output by the first clock feedback module, and respectively output a first voltage signal pair and a second voltage signal pair; the clock signal includes a first clock signal and a second clock signal with opposite phases. The signal multiplexing unit is used to select, based on the phase of the clock signal, the voltage pair with the higher common-mode voltage among the first voltage signal pair and the second voltage signal pair as the first target voltage signal pair and output it to the first clock feedback module. The first clock feedback module is used to compare the amplitudes of the two voltage signals in the first target voltage signal pair with preset thresholds respectively, and output the first clock signal and the second clock signal to the first resistor-capacitor network module according to the comparison results.

2. The relaxation oscillator according to claim 1, characterized in that, The relaxation oscillator further includes a duty cycle control module; the duty cycle control module includes an enable signal generation unit, a phase detection unit, and a feedback control unit; the input terminal of the enable signal generation unit is connected to the output terminal of the first clock feedback module, the output terminal of the enable signal generation unit is connected to the input terminal of the phase detection unit, the output terminal of the phase detection unit is connected to the input terminal of the feedback control unit, and the output terminal of the feedback control unit is connected to the enable terminal of the first clock feedback module; wherein, The enable signal generating unit is used to generate and output periodic enable pulses according to the clock signal; The phase detection unit is used to obtain the phase difference between the falling edge of the enable pulse and the rising edge of the second clock signal; The feedback control unit outputs a control signal to the enable signal generating unit based on the phase difference; the control signal is used to adjust the enable pulse.

3. The relaxation oscillator according to claim 2, characterized in that, The feedback control unit also includes a charge pump subunit and a capacitor subunit; The charge pump subunit is used to charge and discharge the capacitor in the capacitor subunit; The capacitor subunit is used to output the control signal and adjust the enable pulse according to the control signal.

4. The relaxation oscillator according to claim 1, characterized in that, The first clock feedback module includes: a signal shaping unit and a latching unit; the input terminal of the signal shaping unit is connected to the output terminal of the first RC network module; the output terminal of the signal shaping unit is connected to the input terminal of the latching unit, and the output terminal of the latching unit is connected to the input terminal of the first RC network module; wherein, The signal shaping unit is configured to receive a first signal and a second signal from the first target voltage signal pair, compare the first signal with a preset first threshold and output a set signal according to the comparison result; compare the second signal with a preset second threshold and output a reset signal according to the comparison result. The latch unit is used to output the clock signal to the first resistor-capacitor network module in response to the set signal and the reset signal.

5. The relaxation oscillator according to claim 4, characterized in that, The signal shaping unit is configured to, in response to an enable pulse, compare the first signal with a corresponding preset first threshold and compare the second signal with a corresponding preset second threshold.

6. The relaxation oscillator according to claim 4, characterized in that, The first clock feedback module further includes: a clock boosting unit, the input of which is connected to the output of the latch unit, and the output of which is connected to the input of the first resistor-capacitor network module; wherein, The clock boosting unit is used to boost the voltage swing and power of the clock signal and output the enhanced clock signal to the first resistor-capacitor network module.

7. The relaxation oscillator according to claim 5, characterized in that, The relaxation oscillator further includes a signal amplification module, which includes a feedback amplification unit and a threshold voltage amplification unit. The input terminal of the feedback amplification unit is connected to the output terminal of the first RC network module, the output terminal of the feedback amplification unit is connected to the input terminal of the threshold voltage amplification unit, and the output terminal of the threshold voltage amplification unit is connected to the input terminal of the first clock feedback module. The feedback amplification unit is used to amplify the differential-mode component of the first target voltage signal pair, compare the common-mode voltage of the first target voltage signal pair with a preset reference voltage, adjust the first target voltage signal pair according to the comparison result so that the common-mode voltage approaches the preset reference voltage, obtain a first-stage amplified signal pair, and input the first-stage amplified signal pair to the threshold voltage amplification unit. The threshold voltage amplification unit is used to amplify the differential-mode component of the first-stage amplified signal pair and adjust the first-stage amplified signal pair according to the preset first threshold or the preset second threshold, so that the transition point of the first-stage amplified signal pair is increased to obtain the second-stage amplified signal pair; the transition point is the voltage value when the difference between the two voltage signals in the first-stage amplified signal pair is less than the preset first transition threshold.

8. The relaxation oscillator according to claim 7, characterized in that, The relaxation oscillator further includes a temperature compensation module: wherein the temperature compensation module includes a second RC network module with the same structure as the first RC network module, a second clock feedback module with the same structure as the first clock feedback module, a measurement circuit unit, and a compensation voltage generation unit; the time constants of the capacitors and resistors in the second RC network module are less than the time constants of the capacitors and resistors in the first RC network module; the output terminal of the second RC network module is connected to the input terminal of the second clock feedback module, the output terminal of the second clock feedback module is connected to the input terminal of the measurement circuit unit, the output terminal of the measurement circuit unit is connected to the input terminal of the compensation voltage generation unit, and the output terminal of the compensation voltage generation unit is connected to the input terminal of the first RC network module; wherein, The second RC network module is used to receive the external power supply signal and the third clock signal and fourth clock signal output by the second clock feedback module, which are out of phase, and output the third voltage signal pair and the fourth voltage signal pair; according to the phase of the third clock signal and the fourth clock signal, the voltage pair with the higher common-mode voltage among the third voltage signal pair and the fourth voltage signal pair is selected as the second target voltage signal pair and output to the second clock feedback module. The second clock feedback module is used to compare the amplitudes of the two voltage signals in the second target voltage signal pair with preset thresholds respectively, and output the third clock signal and the fourth clock signal to the second resistor-capacitor network module according to the comparison results; The measurement circuit is used to measure the transition time of the two voltage signals in the second target voltage signal pair; the transition time is the time length between the previous moment when it is determined that the difference between the two voltage signals in the second target voltage signal pair is less than a preset second transition threshold and the current moment. The compensation voltage generation unit is used to generate a compensation voltage based on the time difference between the switching time and the theoretical switching time, and output the compensation voltage to the second RC network module to adjust the current of the resistor in the first RC network.

9. A method for stabilizing the frequency of a relaxation oscillator, characterized in that, The method includes: A clock signal and a power signal are input to a first asymmetric RC network and a second asymmetric RC network, so that the first asymmetric RC network and the second asymmetric RC network output a first voltage signal pair and a second voltage signal pair, respectively; the clock signal includes a first clock signal and a second clock signal with opposite phases; the first asymmetric RC network and the second asymmetric RC network have the same structure. Based on the phase of the clock signal, the voltage pair with the higher common-mode voltage among the first voltage signal pair and the second voltage signal pair is selected as the first target voltage signal pair; The amplitudes of the two voltage signals in the first target voltage signal pair are compared with preset thresholds, and the clock signal is adjusted according to the comparison results.

10. A self-powered Internet of Things (IoT) device, characterized in that, include: The relaxation oscillator according to any one of claims 1 to 8.

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