Differential sampling circuit

Abstract

This disclosure relates to a differential sampling circuit. A differential sampling circuit is configured to sample a differential circuit including a first output and a second output. The differential sampling circuit includes an amplifier and a switching circuit. The switching circuit includes a capacitor, a pair of sampling switches, and a pair of output switches. One end of the capacitor is coupled to the first output of the differential circuit through one of the pair of sampling switches and to a reference terminal through one of the pair of output switches. The other end of the capacitor is coupled to the second output of the differential circuit through the other of the pair of sampling switches and to the input terminal of the amplifier through the other of the pair of output switches.

Description

Technical Field

[0001] This disclosure relates to a sampling circuit, and more particularly to a sampling circuit suitable for sampling differential circuits. Background Technology

[0002] In a previous study (Publication No. TWI456894B), the applicant proposed a switched capacitor circuit. This switched capacitor circuit includes multiple first capacitors, multiple second capacitors, and a switching circuit. The switching circuit includes multiple switches, each composed of elements based on a bootstrapped switch circuit. When the switched capacitor circuit is applied to differential signal sampling, the multiple first capacitors correspond to one signal input terminal, while the multiple second capacitors correspond to the other signal input terminal. Thus, the first and second capacitors can sample the differential pair of the differential signal amplifier separately.

[0003] However, in a switched capacitor circuit, whether it's multiple first capacitors or multiple second capacitors, each capacitor can only accumulate a signal potential difference of one time (i.e., the potential difference between the input signal and the reference potential) during differential sampling. Therefore, to achieve sufficient amplification, switched capacitor circuits use multiple first or second capacitors to accumulate charge to compensate for the circuit's low feedback factor. However, this also leads to higher production costs and circuit complexity for switched capacitor circuits. Summary of the Invention

[0004] In view of this, the applicant proposes a differential sampling circuit configured to sample a differential circuit including a first output and a second output. The differential sampling circuit includes an amplifier and a first switching circuit. The first switching circuit includes a first capacitor, a pair of first sampling switches, and a pair of first output switches. One end of the first capacitor is coupled to the first output of the differential circuit through one of the pair of first sampling switches and to a first reference terminal through one of the pair of first output switches. The other end of the first capacitor is coupled to the second output of the differential circuit through the other of the pair of first sampling switches and to a first input terminal of the amplifier through the other of the pair of first output switches. Attached Figure Description

[0005] Figure 1A This is a circuit diagram of the differential sampling circuit in the first phase according to the first embodiment.

[0006] Figure 1B This is a circuit diagram of the differential sampling circuit in the second phase according to the first embodiment.

[0007] Figure 2A This is a circuit diagram of the differential sampling circuit in the first phase according to the second embodiment.

[0008] Figure 2B This is a circuit diagram of the differential sampling circuit in the second phase according to the second embodiment.

[0009] Figure 3A This is a circuit diagram of the differential sampling circuit in the first phase according to the third embodiment.

[0010] Figure 3B This is a circuit diagram of the differential sampling circuit in the second phase according to the third embodiment.

[0011] Figure 4A This is a circuit diagram of the differential sampling circuit in the first phase according to the fourth embodiment.

[0012] Figure 4B This is a circuit diagram of the differential sampling circuit in the second phase according to the fourth embodiment. Detailed Implementation

[0013] To make the objectives, means, and effects of the technical means disclosed in the different embodiments of this disclosure more readily understood, the following description, in conjunction with the accompanying drawings, provides a detailed explanation of specific embodiments of the proposed technical means. The descriptions of technical means in the following embodiments of this disclosure are for illustrative purposes only and do not represent all embodiments of this disclosure, nor do they limit this disclosure to specific embodiments. Unless otherwise defined, all technical and technical terms used in this disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. The terminology used in this disclosure is for the purpose of describing specific implementations only and is not intended to limit this disclosure.

[0014] The terms "left," "right," "up," "down," and similar expressions used in this disclosure are merely to indicate relative positional relationships based on diagrams and do not limit the elements using these terms to only being implemented in a representational manner. When the absolute position of the described object changes, the description of the relative position may also change accordingly. The terms "a" or "an" used in this disclosure are used to describe the elements and components of this creation. These terms are only for ease of description and to provide the basic concept of this creation. This description should be understood as including one or at least one, and unless explicitly stated otherwise, the singular includes the plural. The term "including" is an open-ended term and should therefore be interpreted as "including but not limited to."

[0015] Figure 1A This is a circuit diagram of the differential sampling circuit in the first phase according to the first embodiment. Please refer to it. Figure 1ADifferential sampling circuit 10 is configured to sample differential circuit 20. Differential circuit 20 can be a conventional differential amplifier having a differential output pair (hereinafter referred to as "first output" and "second output"). This disclosed embodiment is illustrated by way of a phase state where the first output has a positive signal voltage v and the second output has a negative signal voltage v. However, those skilled in the art will understand that differential circuit 20 can have different output voltages and polarities in different phase states; for example, the first output may have a negative signal voltage v and the second output may have a positive signal voltage v. Differential sampling circuit 10 includes amplifier 12 and one or more switching circuits coupled to the input of amplifier 12. This coupling allows voltage or current transfer between components and is not limited to direct connection or indirect connection through other intermediate components.

[0016] like Figure 1A As shown, the differential sampling circuit 10 of the first embodiment includes an amplifier 12, a first switching circuit 111, and a second switching circuit 112. The first switching circuit 111 is coupled to a first input terminal of the amplifier 12, and the second switching circuit 112 is coupled to a second input terminal of the amplifier 12. The amplifier 12 can be an operational transconductance amplifier (OTA) or a voltage amplifier. In this embodiment, the amplifier 12 has a first output terminal vo1 and a second output terminal vo2 to output paired differential sampling signals. The amplifier 12 of this disclosed embodiment is illustrated by using the first input terminal as an inverting input terminal and the second input terminal as a non-inverting input terminal, while the first output terminal vo1 is a non-inverting output terminal and the second output terminal vo2 is an inverting output terminal. However, the configuration can also be reversed.

[0017] The first switching circuit 111 includes a first capacitor C1, first sampling switches SW3 and SW4, and first output switches SW1 and SW2. The sampling switches and output switches can be, but are not limited to, insulated-gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs), SiC junction transistors (SiC junction transistors), field-effect transistors (FETs), SiC switches, gallium nitride (GaN) switches, photoconductive switches, and bipolar transistors (BJTs). In this embodiment, the terminal C1_a of the first capacitor C1 is coupled to the first sampling switch SW3 and the first output switch SW1. The first capacitor C1 is coupled to the first output of the differential circuit 20 through the first sampling switch SW3 and to the first reference terminal VREF1 through the first output switch SW1. "Through" can refer to the voltage or current transfer between two components being allowed through an intermediate component; therefore, the intermediate component can directly or indirectly connect the two components. For example, an intermediate element, such as a resistor (not shown), may be provided between the first sampling switch SW3 and the differential circuit 20, or between the first sampling switch SW3 and the first capacitor C1; in addition, an intermediate element may be provided between the first output switch SW1 and the reference terminal, or between the first output switch SW1 and the first capacitor C1.

[0018] The first reference terminal VREF1 provides a reference voltage level for the first switching circuit 111. In some embodiments, the first reference terminal VREF1 is configured as a DC voltage source to provide a stable DC reference potential. Alternatively, the first reference terminal VREF1 shares a common ground with the differential circuit 20. In other embodiments, the output of a pipeline analog-to-digital converter circuit or a switched-capacitor (SC) circuit is coupled to the first reference terminal VREF1, thereby allowing the reference voltage level of the first reference terminal VREF1 to be adjusted via the preceding stage circuitry to regulate the output of the differential sampling circuit 10. In some embodiments, two or more differential sampling circuits 10 may be connected in series. Specifically, the output of the amplifier 12 of the first differential sampling circuit 10 (first output vo1 or second output vo2) is coupled to the first reference terminal VREF1 of the second differential sampling circuit 10. Thus, the reference voltage level of the second differential sampling circuit 10 can be adjusted via the preceding first differential sampling circuit 10.

[0019] In this embodiment, the terminal C1_b of the first capacitor C1 is coupled to the first sampling switch SW4 and the first output switch SW2. The first capacitor C1 is coupled to the second output of the differential circuit 20 through the first sampling switch SW4, and to the first input terminal of the amplifier 12 through the first output switch SW2. As mentioned above, an intermediate element may be provided between the first sampling switch SW4 and the differential circuit 20, or between the first sampling switch SW4 and the first capacitor C1; or, an intermediate element may be provided between the first output switch SW2 and the amplifier 12, or between the first output switch SW2 and the first capacitor C1.

[0020] In some embodiments, the sampling switches and output switches are inverses of each other. For example, when the first sampling switches SW3 and SW4 are in a short-circuit state (conducting state), the first output switches SW1 and SW2 are in an open-circuit state (disconnecting state); conversely, when the first sampling switches SW3 and SW4 are in an open-circuit state (disconnecting state), the first output switches SW1 and SW2 are in a short-circuit state (conducting state). In some embodiments, the differential sampling circuit 10 includes a controller (not shown) coupled to each sampling switch and each sampling switch. The controller can generate a first switching signal to control the sampling switches and a second switching signal to control the output switches, the first and second switching signals being inverses of each other. In other embodiments, the sampling switches and output switches use complementary elements. For example, the sampling switches use N-type field-effect transistors, and the output switches use P-type field-effect transistors; the controller can control both the sampling switches and the output switches based on the same switching signal. In other embodiments, the controller is coupled to the sampling switch and, via an inverter, to the output switch; or, the controller is coupled to the sampling switch and, via an inverter, to the output switch. Therefore, the controller can control both the sampling switch and the output switch based on the same switch signal. The controller can be, but is not limited to, a SoC chip, a central processing unit (CPU), a microcontroller unit (MCU), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or a logic circuit.

[0021] Figure 1AThis displays the state of the differential sampling circuit 10 in the first phase, which is the signal sampling stage. At this time, the first sampling switches SW3 and SW4 are short-circuited, and the first output switches SW1 and SW2 are open-circuited. Therefore, the positive signal voltage v generated by the first output of the differential circuit 20 and the negative signal voltage v generated by the second output cause the first capacitor C1 to be charged to twice the signal voltage v (in this embodiment, the potential on the left side of the first capacitor C1 is higher than that on the right side). Figure 1B This is a circuit diagram of the differential sampling circuit in the second phase according to the first embodiment. Please refer to it again. Figure 1B . Figure 1B The differential sampling circuit 10 is displayed in the second phase, which is the signal output stage. At this time, the first sampling switches SW3 and SW4 are open, and the first output switches SW1 and SW2 are short-circuited. Therefore, the voltage sampled from the first capacitor C1 is superpositioned on the potential reference of the first reference terminal VREF1 and output to the first input terminal of the amplifier 12. The amplifier 12 amplifies the voltage difference between the first and second input terminals to generate a differential output signal, which is output to the first output terminal vo1 and the second output terminal vo2. In some embodiments, the second input terminal of the amplifier 12 is coupled to a reference power supply (not shown), and the amplifier 12 generates a differential output signal based on the potential difference between the output signal of the first switching circuit 111 and the reference power supply. In this embodiment, the second input terminal of the amplifier 12 is coupled to the second switching circuit 112.

[0022] The second switching circuit 112 includes a second capacitor C2, second sampling switches SW7 and SW8, and second output switches SW5 and SW6. The second switching circuit 112 can be adapted to the circuit configuration of the first switching circuit 111 in different embodiments of this disclosure. Specifically, the terminal C2_a of the second capacitor C2 is coupled to the second sampling switch SW7 and the second output switch SW5. The second capacitor C2 is coupled to the second output of the differential circuit 20 through the second sampling switch SW7 and to the second reference terminal VREF2 through the second output switch SW5. The terminal C2_b of the second capacitor C2 is coupled to the second sampling switch SW8 and the second output switch SW6. The second capacitor C2 is coupled to the first output of the differential circuit 20 through the second sampling switch SW8 and to the second input terminal of the amplifier 12 through the second output switch SW6. The main configuration difference between the first switching circuit 111 and the second switching circuit 112 compared to this embodiment is that they are interleaved and coupled to the first and second outputs of the differential circuit 20. The second reference terminal VREF2 provides a reference voltage level for the second switching circuit 112. The second reference terminal VREF2 can be adapted to the circuit configuration of the first reference terminal VREF1 in different embodiments of this disclosure. In some embodiments, the first reference terminal VREF1 is coupled to the second reference terminal VREF2, and both receive the same reference potential or ground.

[0023] As previously mentioned, in some embodiments, the sampling switches (first sampling switches SW3, SW4 and second sampling switches SW7, SW8) and the output switches (first output switches SW1, SW2 and second output switches SW5, SW6) are inverse phases. Furthermore, the first sampling switches SW3, SW4 and the second sampling switches SW7, SW8 may be in phase, and the first output switches SW1, SW2 and the second output switches SW5, SW6 may be in phase. For example, please refer to... Figure 1A In the first phase (signal sampling stage), the second sampling switches SW7 and SW8 are short-circuited, and the second output switches SW5 and SW6 are open-circuited. Therefore, the positive signal voltage v generated by the first output of the differential circuit 20 and the negative signal voltage v generated by the second output cause the second capacitor C2 to be charged to twice the signal voltage v (in this embodiment, the potential on the right side of the second capacitor C2 is higher than that on the left side). Therefore, in the first phase of this embodiment, the potential polarities of the first capacitor C1 and the second capacitor C2 are opposite. Please refer again... Figure 1B In the second phase (signal output stage), the second sampling switches SW7 and SW8 are open, and the second output switches SW5 and SW6 are short-circuited. Therefore, the voltage sampled from the second capacitor C2 is superimposed on the potential reference at the second reference terminal VREF2, and then output to the second input terminal of amplifier 12. Figure 1A and Figure 1B As shown, in the first embodiment, the first capacitor C1 (or the second capacitor C2) of the differential sampling circuit 10 samples the differential circuit 20 in the first phase and charges it to twice the signal voltage v of the differential signal. Based on this, the amplifier 12 can achieve at least twice the signal amplification through a single capacitor.

[0024] Figure 2A This is a circuit diagram of the differential sampling circuit in the first phase according to the second embodiment. Figure 2B This is a circuit diagram of the differential sampling circuit in the second phase according to the second embodiment. Please refer to it as well. Figure 2A and Figure 2BThe differential sampling circuit 10 of the second embodiment includes a first switching circuit 111, a second switching circuit 112, an amplifier 12, a first feedback circuit 131, and a second feedback circuit 132. The circuit configurations of the first switching circuit 111, the second switching circuit 112, and the amplifier 12 in the second embodiment can at least refer to the first embodiment disclosed herein, and will not be repeated here. In this embodiment, the first feedback circuit 131 includes a third capacitor C3, and the terminal C3_a of the third capacitor C3 is coupled to the first input terminal of the amplifier 12, and the terminal C3_b of the third capacitor C3 is coupled to the first output terminal vo1 of the amplifier 12; the second feedback circuit 132 includes a fourth capacitor C4, and the terminal C4_a of the fourth capacitor C4 is coupled to the second input terminal of the amplifier 12, and the terminal C4_b of the fourth capacitor C4 is coupled to the second output terminal vo2 of the amplifier 12. The circuit configuration of the first feedback circuit 131 (or the second feedback circuit 132) and the amplifier 12 serves as an integrator circuit. The output signal generated by the first switching circuit 111 (or the second switching circuit 112) after sampling the signal voltage v is amplified and stored in the integrating capacitors (i.e., the third capacitor C3 and the fourth capacitor C4 in this embodiment), which can then be used for low-pass filtering or other applications of the output signal. In some embodiments, the differential sampling circuit 10 is configured with only one of the first feedback circuit 131 and the second feedback circuit 132. Therefore, the differential sampling circuit 10 can process the output signal of only one of its output terminals using an integrator circuit.

[0025] Figure 3A This is a circuit diagram of the differential sampling circuit in the first phase according to the third embodiment. Figure 3B This is a circuit diagram of the differential sampling circuit in the second phase according to the third embodiment. Please refer to it as well. Figure 3A and Figure 3BThe differential sampling circuit 10 of the third embodiment includes a first switching circuit 111, a second switching circuit 112, an amplifier 12, a first feedback circuit 131, and a second feedback circuit 132. The circuit configurations of the first switching circuit 111, the second switching circuit 112, and the amplifier 12 of the third embodiment can at least refer to the first embodiment disclosed herein, and will not be described again here. In this embodiment, the first feedback circuit 131 includes a third capacitor C5, third sampling switches SW11 and SW12, and third output switches SW9 and SW10. The terminal C5_a of the third capacitor C5 is coupled to the third sampling switch SW11 and the third output switch SW9. The third capacitor C5 is coupled to the second output of the differential circuit 20 through the third sampling switch SW11, and is coupled to the first input terminal of the amplifier 12 through the third output switch SW9. The terminal C5_b of the third capacitor C5 is coupled to the third sampling switch SW12 and the third output switch SW10. The third capacitor C5 is coupled to the first output of the differential circuit 20 through the third sampling switch SW12, and to the first output terminal vo1 of the amplifier 12 through the third output switch SW10. The second feedback circuit 132 includes a fourth capacitor C6, fourth sampling switches SW15 and SW16, and fourth output switches SW13 and SW14. The terminal C6_a of the fourth capacitor C6 is coupled to the fourth sampling switch SW15 and the fourth output switch SW13. The fourth capacitor C6 is coupled to the first output of the differential circuit 20 through the fourth sampling switch SW15, and to the second input terminal of the amplifier 12 through the fourth output switch SW13. The terminal C6_b of the fourth capacitor C6 is coupled to the fourth sampling switch SW16 and the fourth output switch SW14. The fourth capacitor C6 is coupled to the second output of the differential circuit 20 through the fourth sampling switch SW16, and is coupled to the second output terminal vo2 of the amplifier 12 through the fourth output switch SW14.

[0026] As previously mentioned, in some embodiments, the sampling switches (third sampling switches SW11, SW12 and fourth sampling switches SW15, SW16) and the output switches (third output switches SW9, SW10 and fourth output switches SW13, SW14) are inverse phases. Furthermore, the first sampling switches SW3, SW4 and the third sampling switches SW11, SW12 may be in phase, and the first output switches SW1, SW2 and the third output switches SW9, SW10 may be in phase. For example, please refer to... Figure 3AIn the first phase (signal sampling stage), the first sampling switches SW3 and SW4, the second sampling switches SW7 and SW8, the third sampling switches SW11 and SW12, and the fourth sampling switches SW15 and SW16 are short-circuited, while the first output switches SW1 and SW2, the second output switches SW5 and SW6, the third output switches SW9 and SW10, and the fourth output switches SW13 and SW14 are open-circuited. Therefore, the positive signal voltage v generated by the first output and the negative signal voltage v generated by the second output of the differential circuit 20 cause the first capacitor C1 to be charged to twice the signal voltage v (in this embodiment, the left side potential of the first capacitor C1 is higher than the right side), and the third capacitor C5 to be charged to twice the signal voltage v (in this embodiment, the right side potential of the third capacitor C5 is higher than the left side); additionally, the second capacitor C2 is charged to twice the signal voltage v (in this embodiment, the right side potential of the second capacitor C2 is higher than the left side), and the fourth capacitor C6 is charged to twice the signal voltage v (in this embodiment, the left side potential of the fourth capacitor C6 is higher than the right side). Therefore, in the first phase of this embodiment, the potential polarities of the first capacitor C1 and the third capacitor C5 are opposite, and the potential polarities of the second capacitor C2 and the fourth capacitor C6 are opposite. Please refer to... Figure 3B In the second phase (signal output stage), the first sampling switches SW3 and SW4, the second sampling switches SW7 and SW8, the third sampling switches SW11 and SW12, and the fourth sampling switches SW15 and SW16 are open, while the first output switches SW1 and SW2, the second output switches SW5 and SW6, the third output switches SW9 and SW10, and the fourth output switches SW13 and SW14 are short-circuited.

[0027] like Figure 3A and Figure 3B As shown, in the third embodiment, the first capacitor C1 of the first switching circuit 111 (or the second capacitor C2 of the second switching circuit 112) samples the differential circuit 20 in the first phase and charges it to twice the signal voltage v of the differential signal. Furthermore, the third capacitor C5 of the first feedback circuit 131 (or the fourth capacitor C6 of the second feedback circuit 132) samples the differential circuit 20 and charges it to twice the signal voltage v of the differential signal. Since the potential polarities of the first capacitor C1 and the third capacitor C5 are opposite, the first capacitor C1 attracts positive charge from the third capacitor C5 in the second phase. Based on charge conservation, the potential stored in the third capacitor C5 becomes four times the signal voltage v. Similarly, since the potential polarities of the second capacitor C2 and the fourth capacitor C6 are opposite, the second capacitor C2 attracts negative charge from the fourth capacitor C6 in the second phase, causing the potential stored in the fourth capacitor C6 to become four times the signal voltage v. Therefore, the amplifier 12 can achieve at least four times signal amplification through a pair of capacitors.

[0028] Traditional switched capacitor circuits use three first capacitors C1 and the capacitor of the differential signal amplifier 12 itself to achieve a fourfold amplification, resulting in a feedback factor of 1 / 4. In contrast, the differential sampling circuit 10 of the third embodiment achieves a fourfold amplification through the first capacitor C1 and the third capacitor C5 (or the second capacitor C2 and the fourth capacitor C6), resulting in a feedback factor of 1 / 2. Therefore, in this embodiment, the differential sampling circuit 10 benefits from a higher feedback factor, reducing the power consumption and gain requirements of the amplifier 12. In other embodiments, the differential sampling circuit 10 is configured with only one of the first feedback circuit 131 and the second feedback circuit 132. Therefore, the differential sampling circuit 10 can adjust the amplification factor only for the output signal at one of its output terminals.

[0029] Figure 4A This is a circuit diagram of the differential sampling circuit in the first phase according to the fourth embodiment. Figure 4B This is a circuit diagram of the differential sampling circuit in the second phase according to the fourth embodiment. Please refer to it as well. Figure 4A and Figure 4B The differential sampling circuit 10 of the fourth embodiment includes a first switching circuit 111, a second switching circuit 112, an amplifier 12, a first feedback circuit 131, and a second feedback circuit 132. The circuit configurations of the first switching circuit 111, the second switching circuit 112, and the amplifier 12 in the fourth embodiment can at least refer to the first embodiment disclosed herein, and will not be repeated here. In this embodiment, the first feedback circuit 131 includes a third capacitor C7, a third sampling switch SW18, a third output switch SW17, and a first voltage source V1. Terminal C7_a of the third capacitor C7 is coupled to the third sampling switch SW18 and the third output switch SW17. The third capacitor C7 is coupled to the first voltage source V1 through the third sampling switch SW18 and to the first output terminal vo1 of the amplifier 12 through the third output switch SW17. Terminal C7_b of the third capacitor C7 is coupled to the first input terminal of the amplifier 12. The second feedback circuit 132 includes a fourth capacitor C8, a fourth sampling switch SW20, a fourth output switch SW19, and a second voltage source V2. Terminal C8_a of the fourth capacitor C8 is coupled to the fourth sampling switch SW20 and the fourth output switch SW19. The fourth capacitor C8 is coupled to the second voltage source V2 through the fourth sampling switch SW20 and to the second output terminal vo2 of the amplifier 12 through the fourth output switch SW19. Terminal C8_b of the fourth capacitor C8 is coupled to the second input terminal of the amplifier 12.

[0030] The first voltage source V1 (second voltage source V2) can function as a DC voltage source to provide a DC bias, or as a signal source to generate DC or AC signals. For example, the first voltage source V1 (second voltage source V2) can act as a stable DC voltage source, resetting the third capacitor C7 (fourth capacitor C8) at each first phase. As another example, the first voltage source V1 (second voltage source V2) can receive the output signal from an external analog-to-digital converter circuit; therefore, the amplifier 12 can receive the output signals from the first switching circuit 111 (second switching circuit 112) and the digital converter at different phases, amplify them, and then generate an output signal. In some embodiments, the first voltage source V1 and the second voltage source V2 have opposite polarities to correspond to the inverted signals output by the first switching circuit 111 and the second switching circuit 112. For example, the first voltage source V1 provides a +3.3V DC bias, and the second voltage source V2 provides a -3.3V DC bias. For example, a first voltage source V1 provides a first AC signal, and a second voltage source V2 provides a second AC signal, with a phase difference of 180 degrees between the first and second AC signals. In some embodiments, the output terminal (first output terminal vo1 or second output terminal vo2) of the amplifier 12 of the first differential sampling circuit 10 serves as the first voltage source V1 (or second voltage source V2) of the second differential sampling circuit 10. Thus, the amplifier 12 of the second differential sampling circuit 10 can be controlled by the preceding first differential sampling circuit 10.

[0031] As previously mentioned, in some embodiments, the sampling switches (third sampling switch SW18 and fourth sampling switch SW20) and the output switches (third output switch SW17 and fourth output switch SW19) are inverse phases. Furthermore, the first sampling switches SW3 and SW4 and the third sampling switch SW18 may be in phase, and the first output switches SW1 and SW2 and the third output switch SW17 may be in phase. For example, please refer to... Figure 4A In the first phase (signal sampling stage), the first sampling switches SW3 and SW4, the second sampling switches SW7 and SW8, the third sampling switch SW18, and the fourth sampling switch SW20 are short-circuited, while the first output switches SW1 and SW2, the second output switches SW5 and SW6, the third output switch SW17, and the fourth output switch SW19 are open-circuited. Therefore, the positive signal voltage v generated by the first output of the differential circuit 20 and the negative signal voltage v generated by the second output cause the first capacitor C1 and the second capacitor C2 to be charged to twice the signal voltage v. Furthermore, the first voltage source V1 charges the third capacitor C7, and the second voltage source V2 charges the fourth capacitor C8. Please refer to... Figure 4BIn the second phase (signal output stage), the first sampling switches SW3 and SW4, the second sampling switches SW7 and SW8, the third sampling switch SW18, and the fourth sampling switch SW20 are open, while the first output switches SW1 and SW2, the second output switches SW5 and SW6, the third output switch SW17, and the fourth output switch SW19 are short-circuited.

[0032] like Figure 4A and Figure 4B As shown, in the fourth embodiment, the first capacitor C1 of the first switching circuit 111 (or the second capacitor C2 of the second switching circuit 112) samples the differential circuit 20 in the first phase and charges it to twice the signal voltage v of the differential signal. Furthermore, the third capacitor C7 of the first feedback circuit 131 (or the fourth capacitor C8 of the second feedback circuit 132) receives an external DC bias voltage (or signal) and charges it to the DC bias voltage (or signal) potential. Due to the potential difference between the first capacitor C1 and the third capacitor C7, the first capacitor C1 attracts charge from the third capacitor C7 in the second phase, changing the potential stored in the third capacitor C7 and thus affecting the output signal. Similarly, based on the potential difference between the second capacitor C2 and the fourth capacitor C8, the second capacitor C2 attracts charge from the fourth capacitor C8 in the second phase, changing the potential stored in the fourth capacitor C8 and thus affecting the output signal. Therefore, the differential sampling circuit 10 of this embodiment can adjust the output signal through the first voltage source V1 and the second voltage source V2.

[0033] Although this disclosure has been made by way of embodiments above, it is not intended to limit this disclosure. Anyone skilled in the art may make some modifications and refinements without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the claims of the appended patent application.

[0034] [Symbol Explanation]

[0035] 10: Differential Sampling Circuit

[0036] 111: First switching circuit

[0037] 112: Second switching circuit

[0038] 12: Amplifier

[0039] 131: First Feedback Circuit

[0040] 132: Second Feedback Circuit

[0041] 20: Differential circuit

[0042] SW1, SW2: First output switches

[0043] SW3, SW4: First sampling switches

[0044] SW5, SW6: Second output switches

[0045] SW7, SW8: Second sampling switches

[0046] SW9, SW10, SW17: Third output switches

[0047] SW11, SW12, SW18: Third sampling switches

[0048] SW13, SW14, SW19: Fourth output switches

[0049] SW15, SW16, SW20: Fourth sampling switches

[0050] C1: First capacitor

[0051] C2: Second capacitor

[0052] C3, C5, C7: Third capacitor

[0053] C4, C6, C8: Fourth capacitor

[0054] C1_a, C1_b: Endpoints

[0055] C2_a, C2_b: Endpoints

[0056] C3_a, C3_b: Endpoints

[0057] C4_a, C4_b: Endpoints

[0058] C5_a, C5_b: Endpoints

[0059] C6_a, C6_b: Endpoints

[0060] C7_a, C7_b: Endpoints

[0061] C8_a, C8_b: Endpoints

[0062] VREF1: First Reference End

[0063] VREF2: Second Reference End

[0064] vo1: First output terminal

[0065] vo2: Second output terminal

[0066] v: Signal voltage

[0067] V1: First voltage source

[0068] V2: Second voltage source

Claims

1. A differential sampling circuit configured to sample a differential circuit including a first output and a second output, the differential sampling circuit comprising: An amplifier; and A first switching circuit includes a first capacitor, a pair of first sampling switches, and a pair of first output switches. One end of the first capacitor is coupled to the first output of the differential circuit through one of the first sampling switches and to a first reference terminal through one of the first output switches. The other end of the first capacitor is coupled to the second output of the differential circuit through the other of the first sampling switches and to a first input terminal of the amplifier through the other of the first output switches.

2. The differential sampling circuit according to claim 1, wherein, The first reference terminal is coupled to the output of an analog-to-digital converter circuit.

3. The differential sampling circuit according to claim 1, wherein, The first reference terminal is coupled to the output of a switching capacitor circuit.

4. The differential sampling circuit according to claim 1, wherein, The first reference terminal is coupled to an output terminal of the amplifier of the other differential sampling circuit.

5. The differential sampling circuit according to claim 1, wherein, This amplifier is a transconducting amplifier.

6. The differential sampling circuit according to claim 1 further includes a second switching circuit, the second switching circuit including a second capacitor, a pair of second sampling switches and a pair of second output switches, one end of the second capacitor being coupled to the second output of the differential circuit through one of the pair of second sampling switches and coupled to a second reference terminal through one of the pair of second output switches, the other end of the second capacitor being coupled to the first output of the differential circuit through the other of the pair of second sampling switches and coupled to a second input terminal of the amplifier through the other of the pair of second output switches.

7. The differential sampling circuit according to claim 1 further includes a first feedback circuit, the first feedback circuit including a third capacitor, one end of the third capacitor being coupled to the first input terminal of the amplifier, and the other end of the third capacitor being coupled to a first output terminal of the amplifier.

8. The differential sampling circuit according to claim 7 further includes a second feedback circuit, the second feedback circuit including a fourth capacitor, one end of the fourth capacitor being coupled to a second input terminal of the amplifier, and the other end of the fourth capacitor being coupled to a second output terminal of the amplifier.

9. The differential sampling circuit according to claim 1, further comprising a first feedback circuit, the first feedback circuit comprising a third capacitor, a pair of third sampling switches and a pair of third output switches, one end of the third capacitor being coupled to the second output of the differential circuit through one of the pair of third sampling switches and coupled to the first input terminal of the amplifier through one of the pair of third output switches, the other end of the third capacitor being coupled to the first output of the differential circuit through the other of the pair of third sampling switches and coupled to a first output terminal of the amplifier through the other of the pair of third output switches.

10. The differential sampling circuit according to claim 1 further includes a first feedback circuit, the first feedback circuit including a third capacitor, a third sampling switch and a third output switch, one end of the third capacitor being coupled to a first voltage source through the third sampling switch and coupled to a first output terminal of the amplifier through the third output switch, and the other end of the third capacitor being coupled to the first input terminal of the amplifier.

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