Pulse width modulation dimming in light emitting diode drivers

Abstract

This application relates to pulse width modulation dimming in a light-emitting diode driver. The device includes a sample-and-hold circuit (310) having inputs and outputs. A switch-converter (110) has an output and an amplifier (112). The amplifier (112) has first and second inputs. The output of the switch-converter (110) is coupled to the input of the sample-and-hold circuit (310). A switch circuit (320) has a first switch input, a first switch output, and a second switch output. The first switch output is coupled to the first input of the amplifier (112), and the second switch output is coupled to the second input of the amplifier (112). The first switch input is coupled to the output of the sample-and-hold circuit (310).

Description

Technical Field

[0001] This application relates to pulse width modulation dimming in light-emitting diode drivers. Background Technology

[0002] The brightness (intensity) of light produced by a light-emitting diode (LED) can be controlled by an LED driver. One technique used by LED drivers to control the brightness of LED light is pulse-width modulation (PWM) dimming. In PWM dimming, a PWM signal is provided to the LED driver. The frequency and duty cycle of the PWM control the on and off states of the LED. For example, when the PWM signal is logic high, the switching converter within the LED driver supplies current to the LED, and when the PWM signal is logic low, the switching converter decouples from the LED, thus turning the LED off. The frequency of the PWM signal is greater than the time frequency of the human eye, meaning that the human eye does not perceive LED flicker. Instead, the human eye perceives continuous light produced by the LED, but the brightness level is proportional to the duty cycle of the PWM signal. Summary of the Invention

[0003] In one example, a device includes a sample-and-hold circuit having inputs and outputs. A switching converter has an output and an amplifier. The amplifier has first and second inputs. The output of the switching converter is coupled to the input of the sample-and-hold circuit. The switching circuit has a first switching input, a first switching output, and a second switching output. The first switching output is coupled to the first input of the amplifier, and the second switching output is coupled to the second input of the amplifier. The first switching input is coupled to the output of the sample-and-hold circuit.

[0004] In another example, a device includes an amplifier with an output. A sample-and-hold circuit has an input and an output. The input of the sample-and-hold circuit is coupled to the output of the amplifier. A first switch has first and second switch terminals. The first switch terminal is coupled to the output of the amplifier. A second switch has third and fourth switch terminals. The third switch terminal is coupled to the output of the sample-and-hold circuit. The fourth switch terminal is coupled to the second switch terminal.

[0005] In another example, a light-emitting diode (LED) driver includes a switch-changeover having first and second inputs and terminals. A sample-and-hold circuit has an input and an output. The input of the sample-and-hold circuit is coupled to the terminals of the switch-changeover. A switch has a switching terminal and a control terminal. The switching terminal is coupled to the output of the sample-and-hold circuit. The LED driver has a pulse-width modulation (PWM) input, and the control terminal is coupled to the PWM input. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of an LED driver coupled to one or more LEDs in an example.

[0007] Figure 2 Includes shown in the example Figure 1 The waveform of the LED driver operation.

[0008] Figure 3 This is a schematic diagram of an LED driver that includes a sample-and-hold circuit in an example.

[0009] Figure 4 Includes shown in the example Figure 3 The waveform of the LED driver operation.

[0010] Figure 5 This is a schematic diagram of an LED driver that includes a sample-and-hold circuit, in another example.

[0011] Figure 6 Includes shown in the example Figure 5 The waveform of the LED driver operation. Detailed Implementation

[0012] Use the same reference numerals or other reference indicators in the drawings to indicate the same or similar features (functionally and / or structurally).

[0013] Figure 1 This is a schematic diagram of a lighting system 100, which includes an LED driver 102, a switch 140, an LED 120, a capacitor COUT, and a current sensing circuit 150. The LED 120 may comprise a single LED or multiple LEDs coupled in series. The LED driver 102 has an input 102a and an output 102b. The switch 140 may be implemented as a transistor (e.g., a field-effect transistor) and may be external to or part of the LED driver 102. The switch 140 has switch terminals 140a and 140b and a control input 140c. The output 102b of the LED driver 102 is coupled to switch terminal 140a and one terminal of capacitor COUT. The other terminal of capacitor COUT is coupled to ground. Switch terminal 140b is coupled to LED 120. The current sensing circuit 150 may be coupled between switch 140 and LED 120, or may be part of switch 140 or LED 120. When switch 140 is closed, current ILED flows through LED to ground, and LED 120 emits light.

[0014] The current sensing circuit 150 has an output 150a and generates a current 151 proportional to the current ILED at its output 150a. The LED driver 102 includes a switch converter 110, a current-to-voltage (I2V) converter 130, and a reference voltage circuit 160. The I2V converter 130 has an input 130a and an output 130b. Input 130a is coupled to input 102a of the LED driver 102, and thus to the output 150a of the current sensing circuit 150. The switch converter 110 has inputs 110a and 110b and an output 110c. Input 110a is coupled to the output 130b of the I2V converter 130. Input 110b is coupled to the reference voltage circuit 160, which generates a reference voltage VREF at input 110b of the switch converter 110. The switch converter 110 generates an output voltage VOUT at its output 110c, which is coupled to the output 102b of the LED driver 102. The switching converter 110 can be a buck converter, a boost converter, a buck-boost converter, or other types of switching converters.

[0015] The PWM signal 165 can be generated by an external device, such as a microcontroller unit (MCU). The PWM signal 165 is provided to the control input 140c of the switch 140 via the PWM input to the LED driver. In one example, the switch 140 is closed when the PWM signal 165 is logic high, and open when the PWM signal 165 is logic low. The opening and closing of the switch 140 correspond to a transistor, which can be used to implement the on and off states of the switch 140, respectively.

[0016] Figure 2 Includes showing Figure 1 The waveform of the operation of LED driver 102. Figure 2 The problem with LED driver 102 is also shown. Figure 2The waveform includes the PWM signal 165, the output voltage VOUT, and the LED current ILED. In response to the PWM signal 165 being logic low, switch 140 opens and the output voltage VOUT drops to approximately 0 V. In response to the rising edge 202 of the PWM signal 165, switch 140 closes and current from the switch converter 110 begins charging capacitor COUT. Therefore, the output voltage VOUT rises, as indicated at 204. Eventually, VOUT becomes large enough to turn on LED 120. For example, when the output voltage VOUT is greater than the sum of the turn-on voltages of the individual LEDs, the series-connected LED string will turn on. When the output voltage VOUT reaches this level, current ILED begins to flow. Therefore, due to the ramp-up of the output voltage VOUT, LED 120 turns on after a time delay DELTA following the rising edge 202 of the PWM signal 165. Following the falling edge 206 of the PWM signal 165, switch 140 opens, current ILED stops flowing, LED 120 turns off, and the output voltage VOUT decreases, as shown at 208. The time delay DELTA causes the duty cycle of current ILED to be less than the duty cycle of the PWM signal 165. Therefore, the brightness level of the light produced by LED 120 is less than the target level otherwise specified by the duty cycle of the PWM signal 165.

[0017] Figure 3 This is a schematic diagram of an LED driver 302 coupled to LED 120 in another example. The LED driver 302 samples and holds the output voltage VOUT when LED 120 is turned on, and then causes the switching converter 110 to continue outputting VOUT when LED 120 is turned off. Therefore, the output voltage VOUT does not experience [further details needed]. Figure 2 The decrease is shown. Since the output voltage VOUT remains constant, the duty cycle of the LED current ILED roughly matches the duty cycle of the PWM signal 165.

[0018] exist Figure 3 In this embodiment, LED driver 302 includes a switch converter 110, an I2V converter 130, and a reference voltage circuit 160, as described above. The descriptions of switch converter 110, I2V converter 130, and reference voltage circuit 160 have been provided above and will not be repeated here. LED driver 302 also includes an inverter 170, a sample-and-hold circuit 310, and a switching circuit 320. Inverter 170 receives a PWM signal 165 at its input and generates the logical inverse of the PWM signal (PWM_n) at its output.

[0019] Switching circuit 320 has switch inputs 320a, 320b, 320c, and 320d, and switch outputs 320e and 320f. Switch outputs 320e and 320f are coupled to inputs 110a and 110b of switching converter 110, respectively. Sample-and-hold circuit 310 has input 310a and output 310b. The signal at input 310a is OVFB, and the signal at output 310b is VREF_OV, as explained below. Input 310a of sample-and-hold circuit 310 is coupled to switch input 320c. Output 310b of sample-and-hold circuit 310 is coupled to switch input 320a. Reference voltage circuit 160 is coupled to switch input 320b. Output 130b of I2V converter 130 is coupled to switch input 320d. Switching circuit 320 includes switches 321, 322, 323, and 324 (e.g., transistors). Switch 321 has switch terminals 321a and 321b. Switch terminal 321a is coupled to switch input 320a. Switch terminal 321b is coupled to switch output 320f. Switch 322 has switch terminals 322a and 322b. Switch terminal 322a is coupled to switch input 320b. Switch terminal 322b is coupled to switch output 320f. Switch 323 has switch terminals 323a and 323b. Switch terminal 323a is coupled to switch input 320c. Switch terminal 323b is coupled to switch output 320e. Switch 324 has switch terminals 324a and 324b. Switch terminal 324a is coupled to switch input 320d. Switch terminal 324b is coupled to switch output 320e.

[0020] The control inputs of switches 321-324 receive PWM signal 165 or its logical inverse PWM_n. Switches 321 and 323 receive PWM_n, and switches 322 and 324 receive PWM signal 165. In one example, when PWM signal 165 is logic high and PWM_n is logic low, switches 322 and 324 are closed and switches 321 and 323 are open. Similarly, when PWM signal 165 is logic low and PWM_n is logic high, switches 321 and 323 are closed and switches 322 and 324 are open. Therefore, in one logic state of PWM signal 165 (e.g., logic high), the output signal from I2V converter 130 and VREF are provided to inputs 110a and 110b of switch converter 110, respectively, and in another logic state (e.g., PWM signal logic low), OVFB and VREF_OV are provided to inputs 110a and 110b of switch converter 110, respectively.

[0021] The sample-and-hold circuit 310 includes a comparator 331, an AND gate 334, a counter 335, and a digital-to-analog converter (DAC) 336. The AND gate 334 has inputs 334a and 334b. Input 334a receives a clock signal CLK1, and input 334b ​​receives a PWM signal 165. In some instances, a delayed version of the PWM signal 165 is provided to input 334b. The clock signal CLK1 can be, for example, an externally supplied clock or a clock derived from the switching converter 110. The AND gate 334 performs a logical AND operation on CLK1 and the PWM signal 165, thereby turning off CLK1 when the PWM signal 165 is logic low, and allowing the PWM signal 165 as signal CLK2 to reach the clock input of the counter 335 via the AND gate 334 when the PWM signal 165 is logic high.

[0022] exist Figure 3 In this example, counter 335 is an increment / decrement counter. In addition to the clock input, counter 335 also has a control input 335a and an output 335b. The output of comparator 331 is coupled to the control input 335a of counter 335. In response to a first logic state (e.g., logic high) of the signal at control input 335a, counter 335 increments its output count value CODE upon receiving a pulse (e.g., rising edge) of CLK2. In response to a second logic state (e.g., logic low) of the signal at control input 335a, counter 335 decrements its output count value CODE upon receiving a pulse of CLK2. The output 335b of counter 335 is coupled to input 336a of DAC 336. DAC 336 converts the input CODE into a signal (e.g., voltage) VREF_OV.

[0023] LED driver 302 also includes a voltage divider comprising, for example, resistors R1 and R2 coupled in series between the output 110c of switching converter 110 and ground. The connection between resistors R1 and R2 provides a signal (e.g., voltage) OVFB to the input 310a of sample-and-hold circuit 310 and the positive input of comparator 331. OVFB is a frequency-divided version of VOUT (e.g., ...). The negative input of comparator 331 is coupled to the output 310b of sample-and-hold circuit 310. Comparator 331 compares OVFB with VREF_OV. The signal at control input 335a of counter 335 is in a logic state based on whether OVFB is greater than or less than VREF_OV. For example, if VREF_OV is less than OVFB, comparator 331 outputs logic high to control input 335a, and counter 335 increments its output CODE upon receiving the pulse of CLK2, thereby increasing VREF_OV in DAC 336. If VREF_OV is greater than OVFB, comparator 331 outputs logic low to control input 335a, and counter 335 decrements its output CODE upon receiving the pulse of CLK2, thereby decreasing VREF_OV in DAC 336.

[0024] The sample-and-hold circuit 310 and the switching circuit 320 operate collaboratively in two different states. The first state is when the PWM signal 165 is logic high, and the second state is when the PWM signal 165 is logic low. In the first state (PWM signal 165 logic high), switch 140 is closed, and voltage VOUT is supplied to LED 120, causing current ILED to flow through the LED and the LED to emit light. In the first state, AND gate 334 allows CLK1 to pass through the AND gate as CLK2, thereby clocking counter 335. Each pulse of CLK2 causes counter 335 to increment or decrement its output CODE based on whether VREF_OV is greater than or less than OVFB. As VREF_OV increments up or down, eventually VREF_OV becomes approximately equal to OVFB. Therefore, the sample-and-hold circuit 310 samples and holds the output voltage VOUT during the first state. Moreover, during the first state, switches 322 and 324 are closed, and switches 321 and 323 are open. With the switching circuit 320 in this configuration, the output of the I2V converter is electrically coupled to the input 110a of the switching converter 110, thereby providing the signal from the I2V converter 130 to the input 110a, and the reference voltage circuit 160 is electrically coupled to the input 110b of the switching converter, thereby providing VREF to the input 110b.

[0025] The switching converter 110 includes an amplifier 112 (e.g., an error amplifier), control logic 114, and a driver and power stage 116. The positive input of amplifier 112 is coupled to input 110a, and the negative input of amplifier 112 is coupled to input 110b. During a first state (PWM signal 165 logic high), amplifier 112 amplifies the difference between the output signal from I2V converter 130 and VREF. The output of amplifier 112 is coupled to the input of control logic 114. Resistor R31 and capacitor C31 are coupled in series between the output of amplifier 112 and ground. The control logic generates a PWM signal (DUTY) different from PWM signal 165 based on the output of amplifier 112. DUTY is provided to the driver and power stage 116, which may include gate drivers, transistors, and / or inductors. The components of the driver and power stage 116 may implement a buck converter, boost converter, or buck-boost converter power stage. The control loop formed by the I2V converter 130, amplifier 112 and control logic 114 operates to generate VOUT at a level approximately equal to VREF of the output signal from the I2V 130.

[0026] During the second state (PWM signal 165 is logic low), switch 140 is open, thereby cutting off the current ILED to LED 120, and the LED is off. Furthermore, during the second state, switches 321 and 323 are closed, and switches 322 and 324 are open. With switch circuit 320 in the aforementioned configuration, the output 310b of sample-and-hold circuit 310 is electrically coupled to input 110b of switch converter 110, thereby providing input 110b with a sample-and-hold voltage VREF_OV that is approximately equal to VOUT during the first state, and providing input 110a of switch converter 110 with OVFB. During the second state (PWM signal 165 is logic low), the control loop formed by I2V converter 130, amplifier 112, and control logic 114 operates to maintain VOUT at approximately the same level as VOUT during the first state, thereby avoiding the aforementioned reduction 208. Therefore, when the first state is reactivated (PWM signal 165 becomes logic high), the output voltage VOUT from the switch converter is already at the target level.

[0027] Figure 4 The waveforms include those illustrating the operation of LED driver 302. The waveforms include example waveforms for PWM signals 165, VOUT, and ILED. The first set of waveforms 410 for VOUT and ILED corresponds to the waveforms without... Figure 3 In the case of the sample-and-hold circuit 310, it is used for Figure 2 The waveforms for VOUT and ILED. The second set of 420 waveforms for VOUT and ILED corresponds to the waveforms used for... Figure 3The waveforms of VOUT and ILED of LED driver 302. Instead of the decrease 208 of VOUT during the second state (PWM signal 165 logic low), VOUT in group 420 is maintained at a substantially constant level and does not experience a decrease. Therefore, the LED current ILED of group 420 also does not experience the delay DELTA of group 410 because VOUT is maintained at a substantially constant level.

[0028] Figure 5 This is a schematic diagram of another example including LED driver 502. LED driver 502 also includes switch converter 110, I2V converter 130 and sample-and-hold circuit 310. Figure 5 The sample-and-hold circuit 310 in the middle is coupled to the switching converter 110 and Figure 3 The sample-and-hold circuit 310 in the example has different terminals. Instead of, for example... Figure 3 Input 310a is coupled to output 110c of switching converter 110 via voltage dividers (R1 and R2). Figure 5 Input 310a is coupled to the output of amplifier 112, which generates the output signal COMP. Therefore, sample-and-hold circuit 310 samples the output signal from amplifier 112. LED driver 502 includes switches 411 and 412 (e.g., transistors). Switch 411 has switching terminals 411a and 411b and a control terminal 411c. Switch 412 has switching terminals 412a and 412b and a control terminal 412c. Terminal 411a is coupled to the output of DAC 336 and the negative input of comparator 331. Terminal 412a is coupled to the output of amplifier 112 and the positive input of comparator 331. Terminals 411b and 412b are coupled together and to the inputs of control logic 114 and resistor R31. A PWM signal 165 is provided to the control terminal 412c of switch 412. A signal PWM_n is provided to the control terminal 411c of switch 411. Therefore, when the PWM signal 165 is at a logic high level, switch 411 is closed and switch 412 is open, and when the PWM signal 165 is at a logic low level, switch 411 is open and switch 412 is closed.

[0029] When the PWM signal 165 is logic high, switch 140 closes as described above. Furthermore, when the PWM signal 165 is logic high, switch 412 closes and switch 411 opens, causing the sample-and-hold circuit 310 to sample the output signal COMP from amplifier 112. As described above, the sample-and-hold circuit 310 generates an output signal from DAC 336, which is approximately equal to the sampled input signal. Figure 5In this example, the DAC's output signal is VPARKING. Therefore, VPARKING is approximately equal to the amplifier's output voltage (COMP). When PWM dimming is on (PWM signal 165 is logic high), the sample-and-hold circuit 310 samples the amplifier's output signal. When PWM dimming is off (PWM signal 165 is logic low), switch 412 is open and switch 411 is closed. With switch 411 closed, the sample-and-hold signal VPARING is provided to resistor R31 and the input to control logic 114. Therefore, when PWM signal 165 is logic high, the COMP signal to the input of control logic 114 is the output signal from amplifier 112, or when PWM signal 165 is logic low, the COMP signal to the input of control logic 114 is the signal VPARING from the sample-and-hold circuit 310.

[0030] By sampling and holding the output signal from the amplifier when the PWM signal 165 is logic high, the sample-and-hold circuit 310 can maintain the signal to the control logic 114 at approximately the same level as the signal generated by the amplifier 112. This behavior is technically advantageous because otherwise, when the PWM signal 165 is logic low, the output signal from the amplifier 112 would decrease. By maintaining the COMP signal at the same level when the switch 140 is open, the transient response of the LED driver 502 is faster than without the sample-and-hold circuit 310.

[0031] Figure 6 The waveforms include those illustrating the operation of LED driver 502. The waveforms include example waveforms for PWM signal 165, COMP, and ILED. The first set of waveforms 610 for COMP and ILED corresponds to the waveforms without... Figure 5 The waveforms used for COMP and ILED in the case of the sample-and-hold circuit 310. The second set of waveforms 620 used for COMP and ILED corresponds to the waveforms used for... Figure 5 The waveforms of COMP and ILED of LED driver 502. Instead of the decrease of COMP 608 during the second state (PWM signal 165 logic low), COMP in group 620 is maintained at a substantially constant level and does not experience a decrease. Therefore, the LED current ILED of group 620 also does not experience the delay DELTA of group 610 because COMP is maintained at a substantially constant level.

[0032] In this specification, the term "coupled" may encompass a connection, transmission, or signal path that achieves a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.

[0033] Furthermore, in this description, the statement "based on" means "at least partially based on". Therefore, if X is based on Y, then X may depend on Y and any number of other factors.

[0034] A device “configured to” perform a task or function may be configured by the manufacturer at manufacturing time (e.g., programmed and / or hardwired) to perform the function and / or may be configured (or reconfigured) by the user after manufacturing to perform the function and / or other additional or alternative functions. Such configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of hardware components and the interconnection of the device, or a combination thereof.

[0035] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” are used interchangeably. Unless specifically stated otherwise, these terms are generally used to refer to interconnections or ends between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0036] The circuits or devices described herein as containing certain components may be substantially adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as containing one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may conversely contain semiconductor elements within only a single physical device (e.g., semiconductor dies and / or integrated circuit (IC) packages) and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure, for example, during or after manufacture by an end user and / or a third party.

[0037] While the use of specific transistors is described herein, other transistors (or equivalent devices) may be used alternatively with little or no change to the rest of the circuit system. For example, field-effect transistors (“FETs”) (e.g., n-channel FETs (NFETs) or p-channel FETs (PFETs)), bipolar junction transistors (BJTs, such as NPN or PNP transistors), insulated-gate bipolar transistors (IGBTs), and / or junction field-effect transistors (JFETs) may be used in place of or in combination with the devices described herein. Transistors may be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, the devices may be implemented in or above a silicon (Si) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs) substrate.

[0038] Reference may be made to the control input and current terminals of the transistor in the claims. In the context of a FET, the control input is the gate, and the current terminals are the drain and source. In the context of a BJT, the control input is the base, and the current terminals are the collector and emitter.

[0039] In this article, "FET on" or "enabled" means that a conductive channel exists in the FET and drain current can flow through it. "FET off" or "disabled" means that no conductive channel exists and drain current does not flow through the FET. However, a "disabled" FET can have current flowing through the body diode of the transistor.

[0040] The circuits described herein can be reconfigured to include additional or different components to provide functionality at least partially similar to that available before the component replacement. Unless otherwise stated, a component shown as a resistor generally represents one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may actually be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0041] While some elements of the described examples are contained within the integrated circuit and others are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all of the features described as external to the integrated circuit may be contained within the integrated circuit, and / or some features described as internal to the integrated circuit may be incorporated externally. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / above a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0042] The use of the phrase "grounding" in the foregoing description includes chassis grounding, ground wire grounding, floating grounding, virtual grounding, digital grounding, general grounding, and / or any other form of grounding connection applicable to or suited to the teachings herein. In this specification, unless otherwise stated, "about," "approximately," or "substantially" preceding a parameter means within + / - 10% of the parameter, or, if the parameter is zero, within a reasonable range of approximately zero.

[0043] Within the scope of the claims, modifications to the described instances are possible, and other instances are also possible.

Claims

1. An apparatus comprising: A sample-and-hold circuit having an input and an output; A switching converter having an output and an amplifier having first and second inputs, the output of the switching converter being coupled to the input of the sample-and-hold circuit; as well as A switching circuit having a first switch input, a first switch output, and a second switch output, the first switch output being coupled to the first input of the amplifier, and the second switch output being coupled to the second input of the amplifier, the first switch input being coupled to the output of the sample-and-hold circuit.

2. The device of claim 1, wherein the switching circuit has a second switching input and the switching circuit is configured to receive a signal, and the device further includes a reference voltage circuit having an output coupled to the second switching input, and the switching circuit is configured to electrically couple the output of the sample-and-hold circuit to the second input of the amplifier in response to the signal being in a first logic state, and to electrically couple the output of the reference voltage circuit to the second input of the amplifier in response to the signal being in a second logic state.

3. The device of claim 2, wherein the switching circuit has a third switching input and a fourth switching input, the third switching input being coupled to the input of the sample-and-hold circuit, and the switching circuit is configured to electrically couple the input of the sample-and-hold circuit to the first input of the amplifier in response to the signal being in the first logic state, and to electrically couple the fourth switching input to the first input of the amplifier in response to the signal being in the second logic state.

4. The device of claim 1, wherein the switching circuit comprises a switch having first and second switching terminals, the first switching terminal being coupled to the output of the sample-and-hold circuit, and the second switching terminal being coupled to the second input of the amplifier.

5. The device according to claim 1, wherein the sample-and-hold circuit comprises: A comparator having a first comparator input, a second comparator input, and an output, the first comparator input being coupled to the input of the sample-and-hold circuit and the second comparator input being coupled to the output of the sample-and-hold circuit; A counter having a control input and an output, the control input being coupled to the output of the comparator; as well as A digital-to-analog converter having an input coupled to the output of the counter and an output coupled to the output of the sample-and-hold circuit.

6. The device according to claim 5, wherein the counter is an increment / decrement counter.

7. The device of claim 1, wherein the amplifier has an output, and wherein the switching converter includes a driver having an input coupled to the output of the amplifier.

8. An apparatus comprising: An amplifier having an output; A sample-and-hold circuit having an input and an output, the input of the sample-and-hold circuit being coupled to the output of the amplifier; A first switch having first and second switch terminals, the first switch terminals being coupled to the output of the amplifier; as well as A second switch having a third and a fourth switch terminal, the third switch terminal being coupled to the output of the sample-and-hold circuit and the fourth switch terminal being coupled to the second switch terminal.

9. The device of claim 8, wherein the first switch is configured to close when the second switch is open, and the second switch is configured to close when the first switch is open.

10. The device of claim 8, further comprising a switch converter, wherein the switch converter includes the amplifier.

11. The device of claim 8, wherein the sample-and-hold circuit comprises: A comparator having a first comparator input, a second comparator input, and an output, the first comparator input being coupled to the input of the sample-and-hold circuit and the second comparator input being coupled to the output of the sample-and-hold circuit; A counter having a control input and an output, the control input being coupled to the output of the comparator; as well as A digital-to-analog controller having an input coupled to the output of the counter and an output coupled to the output of the sample-and-hold circuit.

12. The device of claim 11, wherein the counter is an increment / decrement counter.

13. A light-emitting diode (LED) driver, comprising: A switch converter having first and second inputs and terminals; A sample-and-hold circuit having an input and an output, the input of the sample-and-hold circuit being coupled to the terminal of the switching converter; as well as A switch having a switch terminal and a control terminal, the switch terminal being coupled to the output of the sample-and-hold circuit; The LED driver has a pulse width modulation (PWM) input, and the control terminal is coupled to the PWM input.

14. The LED driver of claim 13, further comprising an inverter having an input and an output, the input of the inverter being coupled to the PWM input, and the output of the inverter being coupled to a control terminal.

15. The LED driver of claim 13, wherein the switch is a first switch, the switch terminal is a first switch terminal, the control terminal is a first control terminal, the first switch has a second switch terminal coupled to one of the first and second inputs of the switch converter, and the LED driver further comprises: A second switch having a third and a fourth switch terminal, the fourth switch terminal being coupled to the second switch terminal; as well as A reference voltage circuit having an output coupled to the third switch terminal.

16. The LED driver of claim 13, wherein the switch converter is configured to generate an output voltage at the terminal of the switch converter.

17. The LED driver of claim 13, wherein the switch converter includes an amplifier having an output, and the terminals of the switch converter are coupled to the output of the amplifier.

18. The LED driver of claim 17, wherein the switch is a first switch, the switch terminal is a first switch terminal, the first switch has a second switch terminal, and the LED driver further comprises: A second switch having a third and a fourth switch terminal, the third switch terminal being coupled to the output of the amplifier, and the fourth switch terminal being coupled to the second switch terminal.

19. The LED driver of claim 18, wherein the first switch is configured to close when the second switch is open, and the second switch is configured to close when the first switch is open.

20. The LED driver of claim 13, wherein the sample-and-hold circuit comprises: A comparator having a first comparator input, a second comparator input, and an output, the first comparator input being coupled to the terminal of the switch-converter, and the second comparator input being coupled to the output of the sample-and-hold circuit; A counter having a control input and an output, the control input being coupled to the output of the comparator; as well as A digital-to-analog converter having an input coupled to the output of the counter and an output coupled to the output of the sample-and-hold circuit.

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