Three-dimensional NAND-type oxide ferroelectric memory and methods of fabrication and operation

By employing a direct contact structure between an ultrathin ferroelectric dielectric layer and an oxide semiconductor layer in a three-dimensional NAND flash memory, combined with atomic layer deposition technology, the problems of high voltage, slow speed, and poor durability of three-dimensional NAND flash memory have been solved, achieving high-performance multi-level data storage at low temperatures.

CN122373356APending Publication Date: 2026-07-10SHANGHAI JIAOTONG UNIV
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
SHANGHAI JIAOTONG UNIV
Filing Date
2026-04-13
Publication Date
2026-07-10

AI Technical Summary

Technical Problem

Existing 3D NAND flash memory technology suffers from problems such as high operating voltage, slow write speed, and poor durability. Furthermore, traditional perovskite ferroelectric materials are incompatible with standard CMOS processes, making them difficult to integrate in a 3D structure.

Method used

By directly contacting an ultrathin ferroelectric dielectric layer and an oxide semiconductor layer (with thicknesses of 3-7 nm and 0.5-5 nm, respectively), a metal-ferroelectric-semiconductor structure without an interface layer is formed. This structure is prepared at low temperature using atomic layer deposition and polarization switching is achieved by applying a voltage pulse of less than 2.5 V.

Benefits of technology

It achieves excellent performance such as ultra-low operating voltage (<5 V), high endurance (>10¹⁰ cycles), ultra-fast write speed (<100 ns), and multi-level storage, breaking through the voltage limitations of traditional devices and possessing extreme miniaturization, ultra-low power consumption, and high reliability.

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Abstract

This application provides a three-dimensional NAND-type oxide ferroelectric memory, its fabrication method, and its operation method. The three-dimensional NAND-type oxide ferroelectric memory includes: a substrate layer; a word line layer disposed on the substrate layer; a stacked layer disposed on the word line layer, including multiple isolation layers and multiple gate electrode layers, with the isolation layers and gate electrode layers alternately disposed; multiple vertical channel structures, each vertical channel structure penetrating the stacked layer; and a bit line layer disposed above the vertical channel structures. The inner walls of the vertical channel structures are sequentially provided with a ferroelectric dielectric layer, an oxide semiconductor layer, and a filling layer. The thickness of the ferroelectric dielectric layer is 3-7 nm, and the thickness of the oxide semiconductor layer is 0.5-5 nm. The ferroelectric dielectric layer and the oxide semiconductor layer are in direct contact, forming a metal-ferroelectric-semiconductor structure without an interface layer. The device of this application has excellent performance characteristics such as ultra-low operating voltage, high durability, ultra-fast write speed, and multi-level storage.
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