High-density magnetoresistive random access memory and method of manufacturing the same

Abstract

This document discloses a three-dimensional (3D) magnetoresistive random access memory (MRAM) device comprising a plurality of stacked cells, a plurality of stacked insulating layers, and a first interconnect structure of a first type. The plurality of cells are stacked in a direction perpendicular to the main surface of a substrate of the 3D MRAM device. Each of the plurality of cells is separated from another cell of the plurality of cells by an insulating layer among the plurality of insulating layers. Each of the plurality of cells includes a magnetic tunnel junction (MTJ) structure and a second interconnect structure of a second type, the second interconnect structure being configured to interface with the MTJ structure of the cell. The orientation of the first interconnect structure is orthogonal to the second interconnect structure of each of the plurality of cells, and extends through the plurality of cells to interface with the MTJ structure in each cell.

Description

Technical Field

[0001] It involves memory. Background Technology

[0002] Magnetoresistive random access memory (MRAM) is a non-volatile memory technology that offers a combination of fast write speeds, high durability, and non-volatility, making it suitable for a wide range of applications. Unlike some other memory technologies, such as dynamic random access memory (DRAM), MRAM retains data even when no power is applied, while providing endurance that withstands frequent read and write cycles. These characteristics position MRAM as a suitable option for storage, computing, and embedded systems where reliable, high-speed data retention is critical.

[0003] Despite its advantages, conventional MRAM architectures face limitations in terms of memory density. The two-dimensional (2D) layout commonly used in MRAM systems limits the amount of memory that can be stored per unit area, resulting in higher cost per bit compared to other memory technologies. This lower memory density poses challenges for applications requiring large amounts of data storage, especially as the demand for higher performance and smaller form factors continues to grow. Summary of the Invention

[0004] An embodiment provides a three-dimensional (3D) magnetoresistive random access memory (MRAM) device, comprising: a first plurality of cells stacked in a direction perpendicular to the main surface of a substrate of the MRAM device, each of the first plurality of cells including a magnetic tunnel junction (MTJ) structure and a first interconnect structure of a first type configured to interface with the MTJ structure of the cell, and each of the first plurality of cells being separated from another cell of the first plurality of cells by an insulating layer of a first plurality of insulating layers; and a second interconnect structure of a second type oriented orthogonal to the first interconnect structure of each of the first plurality of cells, the second interconnect structure extending through the first plurality of cells to interface with the MTJ structure in each of the first plurality of cells.

[0005] In one or more embodiments, the MTJ structure of each unit includes: a first magnetic layer having a variable magnetization state; a second magnetic layer having a fixed magnetization state; and an insulating layer disposed between the first magnetic layer and the second magnetic layer.

[0006] In one or more embodiments, for each of the first plurality of cells, the first interconnect structure is a word line connector that directly interfaces with the first magnetic layer and further with the access lines of the MRAM device, and the second interconnect structure is a bit line that directly interfaces with the second magnetic layer.

[0007] In one or more embodiments, for each of the first plurality of cells, the first interconnect structure is a word line connector that directly interfaces with the second magnetic layer, and the second interconnect structure is a bit line that directly interfaces with the first magnetic layer.

[0008] In one or more embodiments, for each of the first plurality of cells, the first interconnect structure is a bit line connector that directly interfaces with the first magnetic layer, and the second interconnect structure is a word line that directly interfaces with the second magnetic layer.

[0009] In one or more embodiments, for each of the first plurality of cells, the first interconnect structure is a bit line connector that directly interfaces with the second magnetic layer, and the second interconnect structure is a word line that directly interfaces with the first magnetic layer.

[0010] In one or more embodiments, each of the first magnetic layer, the second magnetic layer, and the insulating layer of the MTJ structure of each unit has at least one main surface, the at least one main surface being parallel to each other and oriented perpendicular to the main surface of the substrate.

[0011] In one or more embodiments, it further includes: a selector transistor coupled to the second interconnect structure and a selector line configured to activate the selector transistor.

[0012] In one or more embodiments, it further includes: a sense amplifier coupled to the second interconnect structure via the selector transistor.

[0013] In one or more embodiments, the system further includes: a second plurality of cells stacked in a direction perpendicular to the main surface of the substrate, each of the second plurality of cells including an MTJ structure and a third interconnect structure of the first type, the third interconnect structure being configured to interface with the MTJ structure of the cell, and each of the second plurality of cells being separated from another cell of the second plurality of cells by an insulating layer in a second plurality of insulating layers; and a fourth interconnect structure of the second type orthogonal to each access interconnect of each of the second plurality of cells, the fourth interconnect structure extending through the second plurality of cells to interface with the MTJ structure in each of the second plurality of cells.

[0014] In one or more embodiments, it further includes an isolation layer disposed between the second interconnect structure and the fourth interconnect structure.

[0015] According to another aspect of the embodiments, a three-dimensional (3D) magnetoresistive random access memory (MRAM) device is provided, comprising: a first plurality of cells stacked in a direction perpendicular to the main surface of a substrate of the MRAM device, each of the first plurality of cells being separated from another cell of the first plurality of cells by an insulating layer of a first plurality of insulating layers, and each of the first plurality of cells including a word line connector and a magnetic tunnel junction (MTJ) structure, the MTJ structure including: a first magnetic layer having a variable magnetization state and directly interfacing with the word line connector; a second magnetic layer having a fixed magnetization state; and an insulating layer disposed between the first magnetic layer and the second magnetic layer; and a first bit line oriented orthogonal to each word line connector of each of the first plurality of cells, the first bit line extending through the first plurality of cells and directly interfacing with the second magnetic layer of the MTJ structure in each of the first plurality of cells.

[0016] In one or more embodiments, the system further includes: a second plurality of cells stacked in a direction perpendicular to the main surface of the substrate, each of the second plurality of cells being separated from another cell of the second plurality of cells by an insulating layer in a second plurality of insulating layers, and each of the second plurality of cells including an MTJ structure and a word line connector configured to directly interface with the MTJ structure of the cell; and a second bit line orthogonal to each access interconnect of each of the second plurality of cells, the second bit line extending through the second plurality of cells to interface with the MTJ structure in each of the second plurality of cells.

[0017] In one or more embodiments, it further includes an isolation layer disposed between the first bit line and the second bit line.

[0018] According to another aspect of the embodiments, a method for manufacturing a three-dimensional (3D) magnetoresistive random access memory (MRAM) structure includes: forming a multilayer stack of alternating first and second sacrificial layers; forming at least one trench in the multilayer stack; forming a lateral magnetic tunnel junction (MTJ) layer on the vertical sidewall of the at least one trench; forming a first interconnect structure of a first type in contact with a first layer in the lateral MTJ layer in the at least one trench; and forming a plurality of MRAM cells within the multilayer stack, each of the plurality of MRAM cells including a second interconnect structure of a second type and a lateral MTJ structure, the lateral MTJ structure being constituted by a portion of each layer in the lateral MTJ layer, the second interconnect structure contacting a second layer in the lateral MTJ layer.

[0019] In one or more embodiments, forming the transverse MTJ layer includes: forming a second layer in contact with the vertical sidewall of the at least one trench; forming a third layer in contact with the vertical sidewall of the second layer; and forming a first layer in contact with the vertical sidewall of the third layer.

[0020] In one or more embodiments, the first layer is a magnetic layer with a fixed magnetization state, the second layer is a magnetic layer with a variable magnetization state, and the third layer is an insulating layer.

[0021] In one or more embodiments, forming the plurality of MRAM cells within the multilayer stack includes: etching away adjacent portions of the first sacrificial layer and the lateral MTJ layer, the etching forming a first cavity between the second sacrificial layer and exposing a corresponding portion of the first interconnect structure in each of the first cavities, the etching leaving the remaining portion of the lateral MTJ layer, thereby forming the lateral MTJ structure of each of the plurality of MRAM cells; and forming an insulating layer in each of the first cavities that contacts the corresponding portion of the first interconnect structure.

[0022] In one or more embodiments, forming the plurality of MRAM cells within the multilayer stack further includes: etching away the second sacrificial layer to define each of the plurality of MRAM cells, the etching forming a second cavity between each insulating layer and exposing the lateral MTJ structure of the MRAM cell; and for each second cavity, forming a second interconnect structure in the second cavity that contacts the lateral MTJ structure exposed by the second cavity.

[0023] In one or more embodiments, the method further includes: forming a stepped structure in a portion of the multilayer stack; depositing a dielectric layer over the stepped structure; forming vias within the dielectric layer to expose the second interconnect structure of each of the plurality of MRAM cells; and filling the vias with a conductive material to form a plurality of electrical contacts, each contacting the second interconnect structure of one of the plurality of MRAM cells. Attached Figure Description

[0024] This disclosure will be better understood by referring to the accompanying drawings, which will make its many features and advantages clear to those skilled in the art. The same reference numerals are used in different drawings to indicate similar or identical items.

[0025] Figure 1A This is a perspective view of a three-dimensional (3D) magnetoresistive random access memory (MRAM) device according to some embodiments.

[0026] Figure 1B According to some embodiments Figure 1A Cross-sectional view of the device's 3D MRAM.

[0027] Figure 2 It is coupled to the selector transistor and select line according to some embodiments. Figure 1A A cross-sectional view of a 3D MRAM device.

[0028] Figure 3 It is coupled to the sense amplifier according to some embodiments. Figure 1A A cross-sectional view of a 3D MRAM device.

[0029] Figure 4 According to some embodiments, it is used for Figure 1A Cross-sectional views of different configurations of the magnetic tunnel junction (MTJ) layer in a 3D MRAM device.

[0030] Figure 5 This is a cross-sectional view of a structure after a complementary metal-oxide-semiconductor (CMOS) layer has been formed on a substrate, according to some embodiments.

[0031] Figure 6 This is a cross-sectional view of a structure following a multilayer stack with alternating sacrificial layers formed on a CMOS layer, according to some embodiments.

[0032] Figure 7 It is a cross-sectional view of a structure after a stepped structure has been formed in a portion of a multilayer stack, according to some embodiments.

[0033] Figure 8 This is a cross-sectional view of the structure after an oxide layer has been formed on the stepped structure according to some embodiments.

[0034] Figure 9 This is a cross-sectional view of a structure after trenches have been formed in a multilayer stack, according to some embodiments.

[0035] Figure 10 This is a cross-sectional view of a structure after trenches have been formed in a multilayer stack, according to some embodiments.

[0036] Figure 11 It is a cross-sectional view of a structure after a vertical MTJ layer has been formed on the sidewall of a trench, a vertical bit line has been formed in the trench, and an isolation trench has been formed in a multilayer stack, according to some embodiments.

[0037] Figure 12 This is a cross-sectional view of the structure after the first set of sacrificial layers within the multilayer stack has been etched away to form a cavity and define the MTJ structure, according to some embodiments.

[0038] Figure 13 This is a cross-sectional view of the structure after an insulating layer has been formed in the cavity, according to some embodiments.

[0039] Figure 14 This is a cross-sectional view of the structure after a second set of sacrificial layers within an etched multilayer stack has been used to form a cavity and expose the MTJ structure, according to some embodiments.

[0040] Figure 15 This is a cross-sectional view of the structure after a second letter line has been formed in the cavity to contact the MTJ structure, according to some embodiments.

[0041] Figure 16 This is a cross-sectional view of the structure after an inner oxide lining layer has been formed on the vertical sidewall of the isolation trench according to some embodiments.

[0042] Figure 17 This is a cross-sectional view of a structure after stress-relief filler material has been deposited in an isolation trench, according to some embodiments.

[0043] Figure 18 This is a cross-sectional view of a structure after contact vias have been formed in a stepped oxide layer according to some embodiments.

[0044] Figure 19 This is a cross-sectional view of the structure after electrical contacts have been formed in the through-hole, according to some embodiments.

[0045] Figure 20 and Figure 21 Together they form a flowchart illustrating an example of the entire process for forming a 3DMRAM device according to at least some embodiments. Detailed Implementation

[0046] Conventional MRAM architectures typically employ a two-dimensional (2D) memory cell layout, where memory cells are arranged horizontally on a single plane. While this layout offers simplicity, it limits the overall memory density achievable in a device, leading to a trade-off between memory capacity and physical space. Therefore, scaling MRAM density in this configuration to meet the ever-growing demand for high-capacity storage becomes challenging and costly.

[0047] Therefore, this paper describes a three-dimensional (3D) MRAM architecture configured to increase memory density and reduce manufacturing costs while maintaining the inherent advantages of MRAM, such as relatively fast write speeds, relatively high persistence, and non-volatility. In this 3D MRAM configuration, memory cells are arranged in a vertically stacked configuration to achieve significantly higher memory density compared to conventional 3D layouts. In at least some embodiments, each memory cell includes a magnetic tunnel junction (MTJ) structure comprising a pinned ferroelectric layer, an insulating tunnel barrier layer, and a free ferroelectric layer. In at least some embodiments, this MTJ is configured using either an in-plane or vertical configuration, thereby providing flexibility in optimizing the performance characteristics of the memory.

[0048] It should be noted that, in the following text, certain orientation terms, such as top, bottom, front, back, etc., are used in a relative sense to describe the positional relationship of the various components. These terms are used with reference to the relative positions of the components shown in the corresponding drawings or as conventionally used in the art, and are not intended to be interpreted in an absolute sense with reference to a gravitational field. Thus, for example, the surface shown in the figures and referred to as the top surface of the component will still be properly understood as the top surface of the component, even if, in an embodiment, the component is placed in a position inverted relative to the position shown in the corresponding drawings and described in this disclosure. Furthermore, certain references to primary and secondary surfaces should be understood to describe positional relationships relative to the primary surface of the substrate or another reference plane, rather than absolute spatial orientation. Additionally, positional terms such as coplanar or parallel will be understood to be interpreted in the context of manufacturing tolerances or industry standards. For example, coplanar should be understood to mean coplanar within applicable tolerances, because one or more manufacturing processes affect components that are indicated as coplanar or coplanar within tolerances utilized in appropriate industrial or manufacturing techniques. Furthermore, it should be understood that, for simplicity and clarity, the components shown in the figures are not necessarily drawn to scale. For example, the dimensions of some components may be enlarged relative to other components.

[0049] It should also be noted that the terms “contact,” “contacts,” “contacting,” or their equivalents refer to a situation where components (e.g., layers, features, or surfaces) are in physical (direct) contact or indirect contact through one or more intermediate layers, features, or surfaces. Furthermore, a component may be in direct or indirect “electrical contact” with one or more other components, depending on the conductivity of the intermediate material between the components.

[0050] Figure 1A and Figure 1B An example 3D MRAM device 100 is shown. Figure 1A This is a perspective view of the 3D MRAM device 100, and Figure 1B It is intercepted along line AA. Figure 1AA cross-sectional view of the 3D MRAM device 100 shown. Figure 1A and Figure 1B In this document, they are collectively referred to as "Figure 1". It should be understood that certain features, layers, or components shown and labeled in some diagrams may not be shown or labeled in other diagrams to simplify the illustration and to more clearly depict the underlying layers and features. In addition, the diagrams are not necessarily drawn to scale, and some elements may be enlarged or omitted to emphasize specific structural or functional details.

[0051] In the example shown in Figure 1, the 3D MRAM device 100 is illustrated in a first configuration, which includes a plurality of 3D MRAM arrays 102 (shown as MRAM arrays 102-1 to MRAM arrays 102-4). Each MRAM array 102 includes cells 106 (in... Figure 1B The 3D stack 104 shown in the figure (as cells 106-1 and 106-2) or rows (in) Figure 1B (Seen as stack 104-1 and stack 104-2). Although Figure 1A and Figure 1B A specific number of elements 106 is shown, but other numbers of elements 106 are also applicable. For example, in Figure 1, five elements 106 are shown in 3D stack 104-1, and five elements 106 are shown in 3D stack 104-2. However, in other configurations, each of the 3D stacks 104 may include more or fewer elements. Furthermore, for ease of illustration and readability, the features of a single element 106 in one of the 3D stacks 104 will be described. However, it should be understood that this description also applies to other elements 106 within the 3D stack 104, as well as to each element 106 in other 3D stacks 104. Additionally, for clarity in the figures, the same features of different elements 106 may be referenced in separate instances in different figures. For example, reference numerals for specific features may be used in one element of Figure 1 and... Figure 2 As shown in another unit, even though the feature exists in every unit 106 throughout the structure.

[0052] Cells 106 of an MRAM array 102 are stacked one on top of the other in the z-direction, as shown below. Figure 1A and 1B As depicted, the z-direction is generally perpendicular to the substrate 504 ( Figure 1A and Figure 5 The main surface 144 of the stack 106. Each stacked unit 106 includes a magnetic tunnel junction (MTJ) 108. Figure 1A(Not shown in Figure 1). In the view shown in Figure 1, the MTJ 108 are stacked one on top of the other in the z-axis direction (e.g., the vertical direction depicted in Figure 1). In other words, the MTJ 108 are stacked one on top of the other in the z-direction, which is generally perpendicular to the main surface 144 of the substrate 504. Each MTJ 108 in the 3D stack 104 (also referred to herein as "MTJ structure 108") includes multiple layers, including a first magnetic layer (e.g., free layer 110) and a second magnetic layer (e.g., pinned layer 112 (or reference layer)), which are separated by an insulating layer (e.g., tunnel barrier 114) disposed between the first and second magnetic layers. The free layer 110, pinned layer 112, and tunnel barrier 114 are not in the same plane. Figure 1A As shown in the diagram. In at least some embodiments, the free layer 110 and the pinned layer 112 comprise magnetic materials, such as cobalt (Co), iron (Fe), boron (B), CoFeB alloys, Co / platinum (Pt) multilayers, Co / nickel (Ni) multilayers, other ferromagnetic multilayer materials, alloys having transition metals or rare earth metals, or any combination thereof. In at least some embodiments, the tunnel barrier 114 providing quantum tunneling is composed of one or more materials, such as magnesium oxide (MgO), aluminum oxide (AlO), or similar insulating materials. Additional insulating or barrier layers (not shown) may also be included in the MTJ structure 108.

[0053] In at least some configurations, pinned layer 112 has a fixed magnetization state with a high magnetization level and remains stable during operation, serving as a reference point for free layer 110. Free layer 110 has a variable magnetization state, meaning it is not pinned or fixed like the reference layer and has a lower magnetization, allowing its magnetic orientation to rotate freely in response to an external magnetic field. Depending on the operating state, the magnetization of free layer 110 can be aligned parallel or antiparallel to pinned layer 112. When the magnetizations of free layer 110 and pinned layer 112 are parallel, electrons are able to tunnel through tunnel barrier 114, resulting in low resistance. Conversely, when the magnetizations are antiparallel, tunneling is suppressed, resulting in high resistance. This change in resistance allows MTJ 108 to store and represent binary data (0 or 1).

[0054] In at least some embodiments, the magnetization of the free layer 110 is controlled in different ways. One method involves passing a current through an adjacent copper wire to generate a magnetic field that affects the free layer 110. Another method involves injecting a spin-polarized current directly into the MTJ 108, generating a torque that rotates the magnetic orientation of the free layer 110. These mechanisms enable switching between parallel and antiparallel states, facilitating read and write operations of the MRAM device 100.

[0055] like Figure 1BAs depicted, the free layer 110, the pinned layer 112, and the tunnel barrier 114 are arranged in a horizontal direction (i.e., as shown in the figure). Figure 1A and Figure 1B Instead of being stacked vertically (in the z-direction) in a cross-sectional view, the MTJ layers 108 are arranged adjacent to each other in the y-direction (as depicted). In at least some embodiments, the MTJ layers 108 have main surfaces (e.g., top surface 124 and bottom surface 128) that are parallel to each other and perpendicular to the main surface 144 of the substrate 504 in the x-direction. This lateral arrangement optimizes the layout of 3D MRAM by enabling more efficient wiring of bit lines (BL) and word lines (WL), which improves memory density and minimizes interference between adjacent cells. Additionally, this configuration enhances scalability while addressing the lithographic challenges associated with vertical stacking. In at least some embodiments, the top surface 124 of the MTJ layers (free layer 110, tunnel barrier 114, and pinned layer 112) is coplanar.

[0056] In at least some embodiments, each unit 106 has an in-plane MTJ configuration or a perpendicular MTJ configuration. In an in-plane MTJ configuration, the magnetization of both the free layer 110 and the pinned layer 112 is parallel to the plane of the layers. The magnetic moment switches between parallel and antiparallel states within this plane. When the magnetization directions are aligned parallel, the MTJ 108 is in its low-resistance state, resulting in lower resistance due to efficient electron tunneling through the insulating layer. Conversely, when the magnetization is antiparallel, the MTJ 108 enters a high-resistance state, where electron tunneling is less efficient due to the misalignment of the magnetic moment, resulting in increased resistance.

[0057] In contrast, the vertical MTJ configuration has a magnetization orientation perpendicular to the plane of the layers. In this configuration, when the magnetization directions of the free layer 110 and the pinned layer 112 are perpendicularly aligned in the same direction, the MTJ 108 achieves a low-resistance state, which facilitates easier electron tunneling. When the magnetization of the free layer 110 is opposite to that of the pinned layer 112, a high-resistance state occurs, hindering electron tunneling due to the antiparallel alignment of the magnetic moments. Both the in-plane MTJ configuration and the vertical MTJ configuration operate based on the principle of tunneling magnetoresistance (TMR), where the relative orientation of the magnetic moments in the free layer and the pinned layer determines the resistance of the MTJ 108.

[0058] Each MTJ 108 in the 3D stack 104 is associated with a first interconnect structure of a first type, such as a word line (WL) connector 116. In the example shown in FIG1, each word line connector 116 (e.g., a contact) is a horizontal connector extending in the x and y directions relative to the view shown in FIG1. ​​In at least some embodiments, each word line connector 116 is connected via a metal wiring layer (e.g., Figure 19The vertical direct points (e.g., M1 layer 1904, M2 layer 1906 and M3 layer 1908) that connect to the M3 layer are the vertical direct points (e.g., Figure 19 The contact 1902 is electrically connected to an access line, such as a word line. In at least some embodiments, the word line itself is a horizontal conductor in one of these metal layers that transmits signals from the drive circuitry to the word line connector 116.

[0059] In at least some embodiments, each cell 106 has a separate word line connector 116 that does not intersect with any other cell 106 of any other MRAM array 102. In the view depicted in FIG1, the word line connector 116 is positioned adjacent to the free layer 110 and to the end or end surface 118 of the free layer 110. Figure 1A (Not shown in the figure) The end or end surface 118 of the word connector 116 is opposite to the surface of the tunnel barrier 114 that contacts the MTJ 108. This direct contact between the word connector 116 and the end surface 118 of the free layer 110 enables efficient transmission of electrical signals, allowing precise control of the MTJ 108 during read and write operations. In the configuration shown in FIG1, the word connector 116 acts as an access interconnect for selecting or accessing the associated cell 106.

[0060] In this context, "horizontal" refers to the arrangement of the word line connector 116 along the sides of the MTJ 108 in the x and y axes of the view shown in FIG. 1, where the MTJ 108 is stacked vertically along the z-axis. However, it should be understood that the terms "horizontal" and "vertical" are relative to the depicted orientation. Regardless of the physical orientation of the device, the word line connector 116 is uniformly arranged along the sides of the MTJ 108 in both the horizontal (x-axis) and depth (y-axis) directions relative to the 3D stack 104.

[0061] This lateral arrangement of the word line connector 116, combined with the word lines and their vertical direct points wired in the metal layer, allows selective control of each MTJ 108 within the 3D stack 104 during read and write operations. Furthermore, the word line connector 116, due to its lateral placement and material properties, ensures that the 3D MRAM structure maintains a high level of scalability while reducing interference between adjacent cells. This efficient wiring system enhances the device's ability to process large amounts of data at high speeds, making it suitable for modern memory applications requiring high density and performance. In at least some embodiments, the word line connector 116 is made of a conductive material, such as tungsten (W), copper (Cu), aluminum (Al), etc.

[0062] Additionally, word line connector 116 is connected to access transistors (not shown in FIG. 1) via word lines routed in metal layers (e.g., M1 layer 1904, M2 layer 1906, M3 layer 1908). This connection is established via contact 1902 or a trace forming the word line, which electrically connects word line connector 116 to the gate of the access transistor. The access transistor acts as a switch, allowing the word line to selectively enable or disable current through MTJ 108 via word line connector 116, thereby facilitating precise access to individual cells 106 during operation.

[0063] The 3D MRAM device 100 also includes a plurality of stacked insulating layers 120. Each cell 106 of an MTJ 108 and its associated word line connector 116 is separated from each other in the z-direction (e.g., the vertical direction in the view depicted in FIG. 1) by insulating layers 120 of the plurality of stacked insulating layers 120, which provide electrical isolation between vertically stacked cells 106 within the 3D stack 104. In at least some embodiments, the insulating layer 120 comprises one or more materials such as silicon dioxide (SiO2) or silicon nitride (Si3N4) and acts both as an electrical insulator and as a structural spacer between the cells 106 of the stacked MTJ 108. The insulation ensures that electrical signals applied to a word line connector 116 and its associated MTJ 108 do not interfere with MTJ 108 in adjacent stacks above or below, allowing precise control of each MTJ 108 within the 3D stack 104.

[0064] In the view shown in Figure 1, the insulating layer 120 contacts the top surface 122 of the word line connector 116 in the lower unit 106 of the 3D stack 104 and the top surface 124 of each layer of the MTJ 108. Figure 1A (Not shown in Figure 1), and also contacts the bottom surface 126 of the word line connector 116 and the bottom surface 128 of the MTJ 108 in the overlying unit 106. These references to the “top” and “bottom” surfaces are relative to the orientation depicted in Figure 1. However, if the MRAM device 100 is rotated, the insulating layer 120 continues to function in the same manner by contacting the surfaces of the word line connector 116 and the MTJ 108 positioned between adjacent units 106, whether they are positioned above, below, or laterally. In any orientation, the insulating layer 120 ensures electrical isolation between the units 106 of the MTJ 108 and the word line connector 116, preventing unwanted electrical signals from crossing between adjacent units 106.

[0065] Furthermore, the insulating layer 120 supports the scalability of the 3D MRAM architecture, allowing for efficient vertical stacking of the MTJ 108 and word line connector 116 while minimizing interference between layers. In at least some embodiments, the insulating layer 120 also serves as a thermal barrier, helping to mitigate heat transfer between stacked layers and improve the durability and lifespan of the MRAM device 100.

[0066] Each MRAM array 102 is associated with a second interconnect structure of a second type, such as a bit line (BL) 130 or another access line, which extends in the z-direction (e.g., vertically) relative to the orientation depicted in FIG1, and in at least some embodiments, the orientation is orthogonal to the word line connector 116. The bit line 130 extends through the stack cell 106 and contacts the pinning layer 112 and the insulating layer 120. In at least some embodiments, the free layer 110, pinning layer 112, and tunnel barrier 114 of the MTJ 108 in the MRAM array 102 surround the corresponding bit line 130. In at least some embodiments, the bit line 130 is made of a conductive metal, such as copper (Cu) or aluminum (Al), which has low resistance and the ability to carry the high-speed current required for memory access. In at least some embodiments, a diffusion barrier layer (not shown) made of a material such as tantalum (Ta) or titanium nitride (TiN) surrounds the bit line 130 to prevent metal diffusion into the surrounding layers, thereby maintaining the integrity of the MRAM array 102. In at least some embodiments, each bit line 130 is configured to interface with, directly interface with, or directly contact the sidewall 132 of each pinned layer 112 in the MRAM array 102.

[0067] In the configuration shown in Figure 1, bit line 130 provides the electrical path required for both read and write operations of the MTJ 108 within the stack 104. Bit line 130 is responsible for supplying the current required for spin-transfer torque (STT) operation in the MTJ 108, which allows the free layer 110 to switch its magnetic orientation between a parallel and antiparallel state. During a write operation, word line connector 116 is activated to select a specific row of the MTJ. Drive current then flows from bit line 130 through the MTJ 108, starting from pinned layer 112, through tunnel barrier 114, and affects the free layer 110. This current causes the STT effect, changing the orientation of the free layer 110. During a read operation, a smaller sense current flows from bit line 130 through the MTJ 108 to word line connector 116. This current allows the system to measure the resistance state of the MTJ 108 to determine the stored data.

[0068] In the configuration shown in Figure 1, bit line 130 acts as a bottom electrode, connecting to the pinned layer 112 of each MTJ 108 in the stack 104. In at least some embodiments, word line connector 116 acts as a top electrode and is configured to interface, directly interface, or directly contact the free layer 110 of the MTJ 108, providing a current path during read and write operations. In the view shown in Figure 1, bit line 130, in conjunction with the selected word line connector 116, facilitates both writing and reading data, allowing current to flow through the MTJ 108 to achieve STT for writing or to sense resistance state for reading. Thus, in the configuration shown in Figure 1, bit line 130 acts as a signal interconnect by providing paths for writing data to and reading data from cell 106.

[0069] In at least some embodiments, isolation layer 134 ( Figure 1A (Not shown) is positioned or disposed between adjacent MRAM cells 106. This isolation layer 134 electrically isolates the bit lines 130 of adjacent MRAM cells 106, preventing unwanted electrical interference and crosstalk that could otherwise degrade the performance of the memory array. In this configuration, the isolation layer 134 contacts the end surface 136 of the word line connector 116 ( Figure 1A (not shown in the image) and the end surface 138 of the insulating layer 120 ( Figure 1A (Not shown in the diagram), thus forming an insulating barrier that electrically separates them, with the end surfaces 136 and 138 adjacent to the adjacent bit lines 130. The isolation layer 134 ensures electrical isolation between adjacent bit lines 130, thereby reducing the risk of leakage current or interference that could affect read and write operations of the MRAM cell 106. Regardless of the orientation of the MRAM device 100, the isolation layer 134 serves to isolate the bit lines 130 that are laterally positioned adjacent to each other within the 3D stack 104.

[0070] In at least some embodiments, the isolation layer 134 includes an inner oxide layer 140 that contacts the end surface 136 of the word line connector 116 and the end surface 138 of the insulating layer 120. In at least some embodiments, the inner oxide layer 140 includes a dielectric material, such as silicon oxide (SiO2) or silicon nitride (Si3N4). These materials effectively prevent electrical signals from propagating between adjacent bit lines 130, ensuring that signals remain confined to the selected bit line during read and write operations. In at least some embodiments, the isolation layer 134 also includes a stress-relieving filler 142 between the inner sidewalls of the inner oxide layer 140. The stress-relieving filler 142 compensates for stress and prevents wafer warpage. In at least some embodiments, the stress-relieving filler 142 includes a trench filler material, such as a metal (e.g., tungsten, titanium nitride, combinations thereof) or polysilicon. These materials are deposited in trench regions around the bit lines 130 and the isolation layer 134 to alleviate mechanical stress and maintain the structural integrity of the memory array.

[0071] In at least some embodiments, to ensure accurate writing and prevent creeping current, selector transistors 202 (shown as transistors 202-1 and 202-2) are connected to each MRAM array 102, acting as bit line selectors, such as... Figure 2 As shown. The gate of this transistor 202 is controlled by a select line (SL) 204, which manages whether bit lines 130, 230 are connected to ground. During a write operation, a specific cell 106 is selected for writing by applying an on-state voltage (Von) to the select line (SL) 204 associated with the desired MRAM array 102. This activates the selector transistor 202, grounding the corresponding bit lines 130, 230. By grounding the bit lines 130, 230, a current path is established through the MTJ 108 of the selected cell 106. Simultaneously, a write voltage (Vw) is applied to the word line connector 116 of the selected cell 106. This voltage is sufficient to generate the current required to induce the STT effect, allowing the free layer 110 to switch its magnetic orientation between a parallel state and an antiparallel state relative to the pinned layer 112.

[0072] In at least some embodiments, a reduced voltage of Vw / 2 is applied to all unselected word line connectors 116 to prevent unintentional writes to other cells 106 in the MRAM array 102. This reduced voltage is precisely calibrated to be insufficient to cause any magnetization change in the first magnetic layer 110 of these unselected cells 106, thereby preventing accidental writes. Furthermore, the unselected select lines 204 are set to float (F), effectively isolating their corresponding bit lines 130, 230 and preventing any creeping currents.

[0073] During a write operation, current flows from the word line connector 116 of the selected cell 106 through the MTJ 108, starting from the free layer 110, passing through the tunnel barrier 114, and entering the pinned layer 112. The current then exits to enter the grounding bit line 130. This current flow through the MTJ 108 generates the necessary spin-transfer torque to change the magnetization state of the free layer, effectively writing the desired data bits into the selected MRAM cell 106. By managing these voltage levels (Von for the select bit line, Vw for writing, Vw / 2 for the unselected word line, and allowing the unselected select line to float), the write operation is precisely positioned, ensuring reliable data storage in the MRAM array 102 while preventing unintentional alterations in other cells 106.

[0074] During a read operation, cell 106 is selected within the MRAM array 102 by applying a read voltage (Vr) to the word line connector 116 of the selected cell 106. The application of Vr ensures that the correct cell 106 is addressed for reading, thereby creating a current path through the MTJ 108 in cell 106. The select line 204 of the MRAM array 102 with the selected cell 106 is turned on. This action activates the selector transistor 202, connecting the corresponding bit lines 130, 330 to the sense amplifiers 302 (shown as sense amplifiers 302-1 and 302-2) and allowing current to flow through the MTJ 108 of the selected cell 106, as shown. Figure 3 As shown.

[0075] Current flows from word line connector 116 in selected cell 106 into the free layer 110 of MTJ 108, through tunnel barrier 114, and into pinned layer 112. The current then exits through bit lines 130, 330 connected to sense amplifier 402. This current is precisely controlled to ensure it is small enough to sense the resistive state of MTJ 108 without altering the magnetization state of free layer 110, thus preserving the stored data.

[0076] The sense amplifier 302 detects the resistance of the MTJ 108 in the selected cell 106 by measuring the voltage drop as current flows. The resistance state indicates the data stored in cell 106, where a lower resistance indicates parallel alignment of the free layer 110 and pinned layer 112 (indicating a binary state), and a higher resistance indicates anti-parallel alignment (indicating the opposite binary state). The data in the selected cell 106 is read out by applying a read voltage (Vr) to the selected word line connector 116, activating the selector transistor 202 by turning on the select line 204, and connecting bit lines 130, 330 to the sense amplifier 302. This coordination process ensures accurate access to the selected cell 106 and efficient retrieval of data from the MRAM array 102.

[0077] It should be understood that other configurations of the MTJ structure 108, word line connector 116, and bit line 130 are also applicable. For example, Figure 4 Additional configurations 400 of these components in MRAM cell 106 are shown (shown as configurations 400-1 to 400-3). In the second configuration 400-1, the positions of free layer 110 and pinned layer 112 are swapped, such that free layer 110 is now the innermost layer of MTJ 108 (the layer closest to bit line 130), and pinned layer 112 is now the outermost layer (the layer furthest from bit line 130). Figure 4 In the view shown, the word line connector 116 extends in the x direction, similar to the configuration described above with respect to Figure 1.

[0078] In this configuration, bit line 130 still provides the electrical path for accessing MTJ 108 for read and write operations, but the role of the layers is reversed. Bit line 130 is now connected to free layer 110. During a write operation, current is supplied from bit line 130, through free layer 110, tunnel barrier 114, and pinned layer 112, and then exits through word line connector 116. This reversal in the current path alters how the spin-transfer torque (STT) effect interacts with free layer 110, as the current now originates from the bit line connected to free layer 110 and travels toward pinned layer 112. During a read operation, bit line 130 supplies a sense current that flows through MTJ 108 in the same manner, starting from free layer 110 and passing through pinned layer 112 to word line connector 116. This allows the system to measure the resistance state of MTJ 108 to determine the stored data.

[0079] Bit line 130 still acts as the bottom electrode, but in this configuration, it is connected to free layer 110. Word line connector 116 now interfaces with pinned layer 112 and acts as the top electrode. Unlike the configuration shown in Figure 1, word line connector 116 facilitates the exit path of current through pinned layer 112 during read and write operations. This reversal means that current enters through bit line 130 connected to free layer 110 and exits through word line connector 116 after passing through MTJ 108, thus completing the circuit.

[0080] In the third configuration 400-2, the positions of the free layer 110 and the pinned layer 112 remain the same as in FIG. 1, but the physical orientation of the word line connector 116 and the component previously referred to as bit line 130 is reversed. Therefore, in this configuration, the components previously designated as word line connector 116 and bit line 130 are now designated as word line 416 and bit line connector 430, reflecting their changed placement and function within the MRAM array 102. For example, each cell 106 now includes a separate bit line connector 430 arranged horizontally (along the x and y directions), which contacts the end of the pinned layer 112. Unlike continuous bit lines extending across multiple cells, each bit line connector 430 is located through a vertical through-hole (…). Figure 4 (not shown) and one or more metal wiring layers (e.g., Figure 19 The M1 layer (1904), M2 layer (1906), and M3 layer (1908) are connected. These vias ensure proper signal routing and electrical functionality.

[0081] During a write operation, bit line connector 430 supplies the necessary current to flow through the MTJ 108 of the selected cell 106. The current travels from bit line connector 430 into the free layer 110, through tunnel barrier 114, to pinned layer 112, and finally exits through vertical word line 416. As the current passes through pinned layer 112, it becomes spin-polarized, allowing a spin-transfer torque (STT) effect to switch the magnetic orientation of free layer 110. During a read operation, bit line connector 430 supplies a sense current following the same path, starting from free layer 110, passing through tunnel barrier 114 to pinned layer 112, and exiting through word line 416. The sense current allows determination of the resistance state of the MTJ, and thus the stored data.

[0082] In this configuration, the bit line connector 430 acts as an electrode connecting to the free layer 110, while the vertical word line 416 acts as an electrode interfacing with the pinned layer 112. This arrangement alters how current interacts with the MTJ structure while still allowing for efficient MRAM operation. Each cell 106 now has its own dedicated bit line connector 430 leading to the metal wiring layer, ensuring isolation and scalability, and facilitating targeted read / write operations within the 3D MRAM array 102.

[0083] In the fourth configuration 400-3, the positions of the free layer 110 and the pinned layer 112 are the same as in the second configuration 400-1, and the relative orientation of the word line and bit line structures follows the relative orientation in the third configuration 400-2. For example, in each cell 106, the free layer 110 is now the innermost layer of the MTJ 108 (the layer closest to the center of cell 106), and the pinned layer 112 is now the outermost layer (the layer furthest from the center of cell 106). Furthermore, each cell 106 now includes a bit line connector 430, which is a horizontal interconnect (extending in the x and y directions) and contacts the end of the free layer 110. Unlike the continuous bit lines shared among multiple cells, the bit line connector 430 of each cell individually interfaces with the free layer 110 and is connected via a vertical through-hole (…). Figure 4 (not shown) connected to the metal wiring layer (e.g., Figure 19 (M1 layer 1904, M2 layer 1906, and M3 layer 1908 in the MRAM array). Additionally, the MRAM array 102 now includes vertical word lines 416 extending in the z-direction, which contact the free layer 110 and the insulating layer 120. Therefore, in this configuration, the pinned layer 112 is accessed via the horizontal bit line connector 130, while the free layer 110 is accessed via the word lines 416.

[0084] During a write operation, bit line connector 430 supplies current flowing through MTJ 108. The current enters MTJ 108 at pinned layer 112, passes through tunnel barrier 114, and then reaches free layer 110 before exiting through word line 416. As current flows from pinned layer 112 to free layer 110, it becomes spin-polarized due to the fixed magnetic orientation of pinned layer 112, allowing a spin-transfer torque (STT) effect to switch the magnetic orientation of free layer 110. During a read operation, bit line connector 430 again supplies sense current following the same path, for example, starting from pinned layer 112, passing through tunnel barrier 114 to free layer 110, and exiting through word line 416. The stored data can be determined by measuring the resistance of the MTJ.

[0085] In this fourth configuration 400-3, the bit line connector 430 acts as an electrode connected to the pinned layer 112, while the word line 416 interfaces with the free layer 110, acting as the electrode through which current leaves the MTJ 108. Therefore, current enters the MTJ 108 from the pinned layer 112 side (via the bit line connector 430) and leaves from the free layer 110 side (via the word line 416). Conversely, in the third configuration 400-2, the bit line connector 430 is connected to the free layer 110, such that current interacts with the free layer 110 before reaching the pinned layer 112. By reversing the positions of the free layer and pinned layer in the fourth configuration 400-3, current now flows from the pinned layer 112 to the free layer 110. Despite these changes, both configurations achieve proper MRAM operation. The word line 116 maintains a common exit path for the current, while a dedicated bit line connector 430 in each cell supplies incoming current to the MTJ 108.

[0086] Figures 5 to 19 Various processes for manufacturing a 3D MRAM device 100 according to one or more embodiments are illustrated. Figure 5 , 6 And 9-17 shows along Figure 1A The cross-section of the MRAM device 100 is taken by line AA, and Figure 7 , 8 18 and 19 show along Figure 1A The image shows a cross-section of the MRAM device 100 taken from line BB. It should be understood that, for clarity and illustration purposes, Figures 5 to 19 The number of layers and features depicted may differ from the number of layers and features shown in Figures 1 to 4. In at least some embodiments, the fabrication process is carried out on a silicon substrate 504 (also in...). Figure 1A A complementary metal-oxide-semiconductor (CMOS) layer 502 is formed on the substrate (as shown in the diagram). Figure 1A (as shown in the image) begins, as Figure 5 As shown. CMOS layer 502 serves as the base layer of 3D MRAM device 100. CMOS layer 502 includes the necessary logic and control circuitry to manage MRAM operations, including data read, write, and addressing functions.

[0087] In at least some embodiments, a series of photolithography, doping, and deposition processes are used to form the CMOS layer 502. The process begins with a series of chemical treatments to clean and prepare the silicon substrate 504 to remove any surface contaminants. A thin layer of silicon dioxide (SiO2) is then grown on the wafer surface by thermal oxidation. This oxide layer serves as the initial gate dielectric for the MOS transistor. Next, a photolithography process is used to pattern the silicon substrate 504. A photoresist layer is applied, and specific areas of the wafer are exposed through a mask using ultraviolet (UV) light, thereby transferring the circuit pattern. After exposure, the photoresist is developed, leaving a patterned layer that protects certain areas of the wafer during subsequent etching steps. Reactive ion etching (RIE) is used to remove the unprotected silicon dioxide and define the active areas where transistors will form.

[0088] Next, ion implantation is performed to introduce dopant into the silicon substrate 504, creating n-type and p-type regions for the source and drain terminals of the MOS transistor. Thermal annealing is used to drive the implanted ions into the substrate, activating the dopant and repairing any lattice damage caused during implantation. After forming the source and drain regions, the gate structure (not shown) is created. A thin gate oxide layer is grown over the transistor channel region, followed by the deposition of a polysilicon layer. This polysilicon layer is then patterned using a second photolithography step to form the transistor gate (not shown).

[0089] Subsequently, interconnect layers are formed to connect various transistors and other circuit elements. This involves depositing an interlayer dielectric (ILD) material (typically silicon dioxide), followed by photolithography and etching processes to create vias and trenches. Then, a metal layer, such as copper or tungsten, is deposited using physical vapor deposition (PVD) or chemical vapor deposition (CVD) techniques to fill these vias and trenches, thereby forming the interconnects. Chemical mechanical planarization (CMP) is used to form planar surfaces for subsequent processing steps.

[0090] The CMOS fabrication process creates a layer 502 on the substrate of the MRAM array 102, including the circuitry required for the control and addressing of the MRAM cells 106. This configuration, known as under-array CMOS (CUA), integrates the CMOS circuitry directly beneath the MRAM array 102. CUA reduces the area consumed by the access circuitry, allowing for a more compact and efficient layout. This arrangement optimizes space utilization by placing the control circuitry directly beneath the MRAM cells 106, thereby increasing overall device density without compromising performance.

[0091] It should be understood that other processes for forming the CMOS layer 502 are also applicable. For example, a CMOS proximity array (CNA) configuration can be implemented, which places the CMOS access circuitry system near, rather than beneath, the MRAM array 102. In another example, a CMOS bonding array (CBA) configuration can be implemented. In this configuration, the CMOS logic is processed and formed on a separate wafer, and then bonded to the MRAM wafer.

[0092] After forming the CMOS layer 502, a multilayer stack 602 of alternating sacrificial layers 604, 606 is formed on the CMOS layer 502. In at least some embodiments, the stack 602 is formed by depositing a first sacrificial material (e.g., silicon dioxide) layer onto the CMOS layer 502 to form a first sacrificial layer 604. This silicon dioxide layer is deposited using, for example, a CVD process. In this process, a silicon-containing precursor (e.g., tetraethyl orthosilicate (TEOS)) is introduced into the reaction chamber along with an oxidant (e.g., oxygen (O2)). The precursor is decomposed at a high temperature (e.g., approximately 400°C-500°C) to form a conformal layer of silicon dioxide on the surface of the CMOS layer 502. The thickness of this silicon dioxide layer can be precisely controlled by adjusting the deposition time and the flow rate of the precursor gas.

[0093] After depositing the first sacrificial layer 604, another insulating material (e.g., silicon nitride) layer is deposited on top of the first sacrificial layer 604 to form a second sacrificial layer 606. The second sacrificial layer 606 is deposited using, for example, a low-pressure chemical vapor deposition (LPCVD) process. In LPCVD, silane (SiH4) and ammonia (NH3) gases are introduced into a reaction chamber, where the gases react at elevated temperatures (e.g., approximately 700°C-800°C) to form a silicon nitride film. The process of alternating sacrificial and insulating material deposition is repeated to form multiple layers in the stack 602.

[0094] Figure 7 This illustration shows that after forming an alternating sacrificial layers 604, 606 in a stack 602, a stepped structure 702 is formed in different portions 704 of the stack 602. However, in other embodiments, the stepped structure 702 is formed at a later stage, such as during the formation of... Figure 10 The vertical position line 130 is formed after that. Figure 11 This occurs before the isolation trench 1104 (e.g., a "staircase last" process). In these embodiments, after the bit line 130 is in place, a step is formed by selectively etching through the multilayer stack 602, thereby ensuring alignment of the step with the vertical bit line connector.

[0095] The purpose of the stepped structure 702 is to provide a connection path from the underlying peripheral circuitry to the layers of the MRAM device 100. This selective stepped formation involves partially removing the multilayer stack 602 to allow for subsequent metallization. In at least some embodiments, the stepped structure 702 is formed by applying a photoresist layer 706 over the entire stack 602. The photoresist is then patterned in the area where the first step of the stepped structure 702 will be formed using photolithography. A photomask defines the area to be etched, and UV light exposure through this mask alters the properties of the photoresist in the designated area. After development, the patterned photoresist exposes the specific sections of the stack 602 to be etched for the first step.

[0096] In at least some embodiments, re-etching (RIE) is employed to remove exposed portions of stack 602, thereby forming initial steps of stepped structure 702. During RIE, a reactive gas, such as carbon tetrafluoride (CF4) or sulfur hexafluoride (SF6), generates plasma that etches away the exposed layers of stack 602, stopping at a controlled depth. After forming the first step, a photoresist trimming process is performed to reduce the size of existing photoresist 706, thereby exposing additional areas of stack 602 for the next etching step. Another round of RIE is then performed to form the next step of stepped structure 702. This process of photoresist trimming and subsequent RIE etching is repeated for each step, thereby gradually exposing more layers of stack 602. Each cycle reduces the size of photoresist 706, allowing iterative formation of the stepped pattern until a complete stepped structure 702 is created, where each step provides a flat landing area for future electrical contacts.

[0097] After the final steps are formed, the stepped structure 702 is ready to form the oxide layer 802 and planarize, as follows: Figure 8 As shown. The oxide layer 802 is used to further define the stepped structure 702 and ensure proper isolation and the creation of a flat surface for subsequent processing steps. In at least some embodiments, a material such as silicon dioxide is deposited over the entire stack 602, covering both the newly formed stepped structure 702 and the area where the MTJ layer 108 will later form. This oxide deposition is performed again using, for example, a CVD process. During CVD, a silicon precursor gas (e.g., TEOS) reacts with an oxidant in a chamber, thereby depositing a uniform silicon dioxide layer across the surface. This layer 802 fills any remaining gaps in the stepped structure 702, thereby providing a smooth transition between steps and ensuring electrical isolation between layers.

[0098] After depositing the oxide layer 802, a CMP process is performed to planarize the surface. CMP involves polishing the surface of the stack 602 using a rotating pad and a slurry containing abrasive particles. The combination of mechanical action and chemical reaction removes excess oxide and any morphological variations, creating a flat, smooth surface essential for the next manufacturing stage. The planarized oxide layer 802 ensures that the stepped structure 702 is clearly defined, with each step providing a clean, isolated landing pad for forming electrical contacts.

[0099] Return to reference Figure 6 The portion of stack 602 shown is shown. Figure 9 The diagram illustrates that after the formation of the stepped structure 702 is complete, trenches 902 or vias (e.g., trenches 902-1 and 902-2) are etched through the stack 602. These trenches 902 define the vertical paths that will later form the MTJ 108 and bit line 130. In at least some embodiments, the etching process involves depositing a new photoresist layer across the surface of the stack 602. Photolithography is used to pattern the photoresist, thereby defining the locations where the trenches 902 will be etched. A photomask is used to selectively expose the photoresist to UV light in regions corresponding to the desired trench locations. After exposure, the photoresist is developed, thereby creating openings in the resist layer that define the trench etch pattern.

[0100] With the photoresist pattern in place, a re-etching process (RIE) is used to etch trenches 902 through stack 602. During this process, a reactive gas (e.g., CF4, SF6, or trifluoromethane (CHF3)) is introduced into the etching chamber to generate plasma. Ions in the plasma are accelerated toward the wafer surface, where they react with exposed areas of sacrificial layers 604, 606, thereby removing material and creating vertical channels. The anisotropic nature of the RIE allows for highly directional etching, resulting in channels with well-defined vertical sidewalls. In at least some embodiments, the etching process extends down through the entire thickness of stack 602 to the underlying CMOS layer 502.

[0101] After etching trenches 902, residual photoresist is removed using a stripping process, which involves, for example, a plasma ashing step followed by wet chemical cleaning. The result is an array of trenches (vertical channels) within stack 602, extending downwards from the top of stack 602 to CMOS layer 502. These trenches 902 define the locations where MTJ structures 108 will be formed in subsequent steps, thereby allowing the creation of a dense, vertically integrated 3D MRAM array 102.

[0102] Figure 10 This illustrates the deposition of an MTJ film within the trenches 902 after they have been etched into the stack 602. Unlike conventional planar processes, this deposition involves depositing an MTJ film on the vertical sidewalls of the trenches 902. Figure 9 The MTJ layer is formed on the z-direction in the depicted view. This method allows for the vertical integration of the MTJ 108 within a 3D MRAM structure. The process involves sequentially depositing free layers 110 (shown as free layers 110-1 and 110-2), pinned layers 112 (shown as pinned layers 112-1 and 112-2), and tunnel barriers 114 (shown as tunnel barriers 114-1 and tunnel barriers 114-2) along a vertical wall.

[0103] In at least some embodiments, deposition begins with conformal deposition of a free layer 110. In at least some embodiments, this layer 110 is composed of a ferromagnetic material such as CoFeB. Conformal deposition techniques, such as atomic layer deposition (ALD) or sputtering with specific parameters, are employed to ensure uniform coverage over the vertical and horizontal surfaces within the trench 902. During ALD, alternating pulses of, for example, cobalt and boron precursors are introduced into the reaction chamber to react with the surface to form a thin, uniform CoFeB layer.

[0104] Next, tunnel barrier 114 is deposited. Similarly, a conformal coating is achieved on the vertical sidewalls of free layer 110 using ALD. In at least some embodiments, the process involves alternating pulses of tunnel barrier material (e.g., a magnesium precursor and an oxidant (e.g., water vapor or oxygen plasma)) to form, for example, a uniform magnesium oxide layer. Pinned layer 112 is then conformally deposited over tunnel barrier 114. In at least some embodiments, tunnel barrier 114 comprises a synthetic antiferromagnetic (SAF) structure, which may include materials such as cobalt iron (CoFe) and ruthenium (Ru). The conformal deposition process, including ALD or sputtering, ensures that pinned layer 112 forms a uniform coating over tunnel barrier 114.

[0105] In at least some embodiments, after conformal deposition of all three layers, an anisotropic etching process is performed to remove the films from the horizontal surface, leaving the layers only on the vertical sidewalls of trench 902. RIE can be used for this etching process because it provides highly directional etching. During RIE, a reactive gas (e.g., a combination of argon or fluorine-based chemicals) is introduced into the chamber. Ions in the plasma are directed vertically toward stack 602, selectively removing material from the horizontal surface while retaining the MTJ films on the vertical walls of trench 902. The result is a vertical stack of free layers 110, tunnel barriers 114, and pinned layers 112 within each trench 902. These MTJ structures are now confined to the vertical sidewalls, where no material is present on the horizontal surface of stack 602.

[0106] Figure 10It is also shown that after forming the MTJ layer on the vertical sidewalls of the trench 902, bit lines 130 (shown as bit lines 130-1 and 130-2) are formed within the trench 902. In at least some embodiments, this process begins with the deposition of a thin adhesive layer (not shown), such as titanium or titanium nitride. This layer promotes adhesion between the MTJ structure and subsequent metal layers, thereby ensuring a stable interface and reducing the risk of delamination. In other embodiments, no adhesive layer is formed. In at least some embodiments, sputtering is used to deposit the adhesive layer.

[0107] Once the adhesive layer is in place, a conductive material, such as tungsten or copper, is deposited for bit line 130. In at least some embodiments, PVD or CVD methods are used for this deposition process. After the bit line material is deposited, a planarization step is performed to ensure a flat and smooth surface. For example, CMP is used to remove excess material and achieve a uniform surface. The CMP process stops at the top of stack 602.

[0108] Figure 11 The diagram illustrates an isolation etching process performed after the formation of bit lines 130 (bottom electrodes) to define and isolate MRAM array structures 1102 (shown as structures 1102-1 and 1102-2). In at least some embodiments, this process involves applying a photoresist layer over the entire stack 602. Photolithography is used to pattern the photoresist, creating a mask that exposes only the areas where material needs to be removed. The photomask used in this process defines the boundaries of each MRAM array 102, ensuring that the etching process selectively removes material from the space between bit lines 130 while maintaining the integrity of the MTJ material and bit lines 130. After UV light exposure through the photomask and subsequent development, the patterned photoresist acts as a protective layer for areas that should not be etched.

[0109] With the photoresist mask in place, an anisotropic RIE process is used to remove unwanted material. The highly oriented nature of the RIE ensures that etching occurs primarily in the vertical direction, thus preserving the lateral dimensions of the MTJ and bit line material and providing clear, well-defined edges. After etching, the remaining photoresist mask is stripped away using a plasma ashing process or wet chemical cleaning. This leaves a well-defined array of isolated MRAM array structures 1102, each separated by isolation trenches 1104.

[0110] Figure 12The diagram illustrates a selective etching process performed after trench 1104 is formed to remove adjacent portions of the second sacrificial layer 606 of stack 602 and the MTJ layers (free layer 110, tunnel barrier 114, and pinned layer 112) within stack 602, while preserving the vertical bit line 130. The etching chemicals are configured to be highly selective for the material of the second sacrificial layer 606 and for the material of the bit line. These metals are typically resistant to certain etchants, allowing the etching process to remove the targeted second sacrificial material and MTJ material while maintaining the integrity of the bit line 130 and the first sacrificial layer 604.

[0111] In at least some embodiments, anisotropic RIE processes are used for selective etching. This process utilizes a previously formed trench 1104 to guide etching, targeting only the second sacrificial layer 604 and its adjacent MTJ portions exposed by the trench 1104. Due to the inherent resistance of the materials of the first sacrificial layer 604 and bit line 130 to the etching chemicals used, the first sacrificial layer 604 and bit line 130 remain unaffected by this etching process. Therefore, the etching selectively removes the second sacrificial layer 606 and its adjacent portions of the MTJ layer on either side of the bit line 130, thereby creating well-defined cavities 1202 (shown as cavities 1202-1 and 1202-2) and isolated MTJ stacks 108.

[0112] Figure 13 The diagram illustrates the encapsulation and isolation process performed after the formation of cavity 1202. This process deposits material to fill cavity 1202 around MTJ structure 108 and forms insulating layers 120. These insulating layers 120 provide electrical isolation and protection for MTJ structure 108. In at least some embodiments, this process involves depositing a conformal dielectric layer, such as silicon nitride or silicon dioxide, using techniques such as CVD or ALD. This material acts as both an encapsulation layer and an isolation layer. Filling material is deposited instead of maintaining the second sacrificial layer 606 because if the second sacrificial material 606 is not completely removed, adjacent portions of MTJ structure 108 will remain connected or shorted together. This would prevent proper electrical isolation, leading to interference between adjacent MTJ cells. By removing the sacrificial material and replacing it with dielectric material, the process ensures that each MTJ structure 108 is encapsulated and electrically isolated from its neighbors. Dielectric material fills the cavity 1202 created by removing the second sacrificial layer 606 and adjacent MTJ portions. After deposition, excess dielectric material is removed from unwanted areas. For example, a CMP process is performed to selectively remove dielectric material from the top of the stack 602 and from within the trench 1104, thereby leaving an insulating layer 120 (shown as insulating layer 120-1 and insulating layer 120-2) only within the cavity 1202 around the MTJ structure 108.

[0113] Figure 14Following the packaging and isolation of the MTJ 108, a further selective etching process is shown to selectively remove the first sacrificial layer 604 to form cavities 1402 (shown as cavities 1402-1 and 1402-2) within the stack 602. These cavities 1402 will later be filled with material to create word line connectors 116 for the MRAM cell 106 (shown as word line connectors 116-1 and 116-2). In at least some embodiments, this involves an etching technique with high selectivity for the material of the first sacrificial layer 604, thereby allowing the removal of these layers 604 without affecting the surrounding insulating layer 120, the MTJ structure 108, or the bit lines 130.

[0114] Instead of depositing word line material, a first sacrificial layer 604 is used, comprising a material such as silicon dioxide. This approach is implemented because if word line material (typically metal) were used, challenges could arise during the removal of the second sacrificial layer and adjacent MTJ portions. Specifically, since the word line material would resemble the metal used in the MTJ structure 108, it could be attacked or damaged during the etching process targeting the second sacrificial layer. Using a non-metallic sacrificial material (e.g., silicon dioxide) in conjunction with additional processing steps ensures that the word line metal remains intact and unaffected. Dry plasma etching, wet chemical etching, or another process is configured to selectively remove the first sacrificial layer 604, targeting its material while preserving the surrounding structure. When the first sacrificial layer 604 is removed, the resulting cavity 1402 provides the necessary space for the subsequent formation of the word line connector 116.

[0115] Figure 15 The diagram shows the selective removal of the first sacrificial layer 604, forming a word connector 116 within the cavity 1402. In at least one embodiment, this process involves depositing a conductive material into the cavity 1402. Examples of conductive materials include tungsten, titanium nitride, or combinations of metals, such as titanium followed by tungsten. In at least some embodiments, techniques such as CVD or PVD are used to perform the deposition to deposit a conformal material layer within the cavity 1402.

[0116] Once the conductive material has been deposited and the cavity 1402 filled, an anisotropic dry etching process, such as RIE, is used to remove the conductive material from the trench 1104. This process is highly directional, targeting the vertical sidewalls and bottom of the trench 1104 to remove the conductive material without disturbing the material within the cavity 1402. Following the dry etching process, a planarization process, such as CMP, is performed to remove excess conductive material from the surface of the stack 602. These etching and polishing processes leave only the word line connector 116 within the cavity 1402 and in direct contact with the free layer 110 of the MTJ structure 108. At this point in the fabrication, the MRAM array 102 is now formed.

[0117] Figure 16 The diagram illustrates the formation of an inner oxide layer 140 in an isolation trench 1104 after the word line connector 116 has been formed. The inner oxide layer 140 electrically isolates the bit lines 130 of adjacent MRAM arrays 102. In at least some embodiments, this process involves depositing a cap oxide material, such as silicon dioxide, using conformal deposition techniques such as CVD or ALD. After conformal oxide deposition, excess oxide material is removed from the top surface of stack 602 using CMP. In at least some embodiments, the portion of the MTJ structure 108 and the bit lines 130 covered by oxide material at the top of stack 602 is removed by a CMP process.

[0118] Following CMP, an anisotropic dry etching process, such as RIE, is performed to selectively remove oxide from the bottom of trench 1104, leaving oxide only on the vertical sidewalls. These processes ensure that oxide remains only where electrical isolation is required between bit lines 130 of adjacent MRAM arrays 102. The result of these processes is an inner oxide layer 140 on the vertical sidewalls of the isolation trench 1104.

[0119] Figure 17 The diagram illustrates the deposition of a stress-relieving filler 142 in contact with the oxide liner 140 within a trench 1104 after the oxide liner 140 has been formed. The oxide liner 140 and the stress-relieving filler 142 form an isolation layer 134. In at least some embodiments, one or more materials, such as titanium nitride and tungsten, are deposited over the entire structure using, for example, PVD or ALD, to fill the isolation trench 1104.

[0120] After depositing the stress-relieving filler 142, a CMP and selective etching process is performed. For example, CMP is performed to remove excess stress-relieving filler 142 from the top of the stack 602, thereby leaving the material within the trench 1104. After CMP, a selective etching process is used to remove any residual stress-relieving filler 142 that may still remain on the top surface or at the trench edges. This step ensures that the stress-relieving filler 142 is completely confined within the trench 1104 between the liner oxide layers 140.

[0121] Figure 18 This shows that after isolation layer 134 has been completed, in Figure 7 A contact etching process is performed on the stepped structure 702. In at least some embodiments, this process involves applying a photoresist layer 1802 over the entire MRAM array 102, including the stepped structure 702. The photoresist is patterned using photolithography to expose specific areas where contact vias need to be formed. A photomask with the desired pattern is aligned over the stepped structure 702, and UV light is used to expose the photoresist 1802. The exposed areas of the photoresist 1802 are then developed, revealing the areas of the stepped structure 702 that will be etched to create contact vias.

[0122] Following the photolithography process, an anisotropic RIE process is used to etch the exposed layer, i.e., the insulating layer 120, through the stepped structure. The anisotropic nature of the RIE ensures that etching occurs primarily in the vertical direction, thereby creating well-defined contact vias 1804 through layer 120 and oxide layer 802. As etching proceeds, the contact vias 1804 are formed through each step of the stepped structure 702, down to the word line connector 116 where electrical contacts will form. Once etching is complete, the photoresist 1802 is removed using a plasma ashing process or wet chemical cleaning. This leaves a stepped structure 70 with well-defined contact vias 1804 extending through the insulating layer 120 to the intended connection point on the word line connector 116.

[0123] like Figure 19 As shown, back-end processes are performed to form electrical contacts 1902 to word connector 116. Figure 1A and Figure 19 In at least some embodiments, this process includes depositing a barrier and an adhesive layer material, such as titanium nitride. For example, using PVD or ALD, a conformal layer of titanium nitride is deposited over the entire structure, including the exposed contact vias 1804 etched in the stepped structure 702. The TiN layer ensures strong adhesion between the conductive material to be deposited subsequently and the underlying material, and also acts as a diffusion barrier.

[0124] Next, a conductive material (e.g., tungsten) layer is deposited on the TiN-coated structure using, for example, CVD. This conductive layer fills the contact vias 1804, forming a robust electrical path to the word connector 116 exposed in the stepped structure 702. After depositing the adhesive and conductive layers, excess material covers the top of the structure, including the surface of the stepped structure 702. To isolate the contacts 1902 and ensure they remain only within the defined vias 1804, a CMP process is performed to remove excess material from the top surface of the structure, leaving conductive material only within the contact vias 1804.

[0125] Upon completion of this process, the word line connector 116 can now be accessed from the top of the device (in...). Figure 19 (As shown, facing upwards) Electrical access. Above this planarized surface, one or more metal interconnect layers are formed, for example, M1 layer 1904, M2 layer 1906, and M3 layer 1908. Within these metal layers, word lines ( Figure 19 Horizontal wiring (not shown in the image) Figure 19 (As shown, facing upwards). Word line connector 116 interfaces with these word lines via vertical direct point 1902, thereby providing a direct electrical connection from the top metal wiring structure down to the side of MTJ cell 106. Therefore, signals can be routed from the drive circuitry (not shown) through the M1 / M2 / M3 metal layers to these word lines, and then through contact vias 1804 to word line connector 116, enabling precise control of individual cells during read / write operations.

[0126] Figure 20 and Figure 21 Together, they form a schematic diagram illustrating an example method 2000 for manufacturing a 3DMRAM device according to one or more embodiments. It should be understood that the above description has been referenced to Figures 1 to 2000. Figure 19 The process described below with respect to Method 2000 is described in more detail. Method 2000 is not limited to... Figure 20 and Figure 21 The order of operations shown is because at least some of the operations can be performed in parallel or in a different order. Furthermore, in at least some embodiments, method 200 may include... Figure 20 and Figure 21 One or more operations that are different from the operations shown.

[0127] At frame 2002, a CMOS layer 502 is formed on substrate 504. At frame 2004, a multilayer stack 602 of alternating sacrificial layers 604, 606 is formed on the CMOS layer 502. At frame 2006, a stepped structure 702 for electrical contacts is formed in a portion 704 of the stack 602. In other embodiments, the stepped structure is formed after bit line 130 is formed at frame 2012 and before isolation trench 1104 is formed at frame 2014. At frame 2008, at least one trench 902 is formed within the stack 602. At frame 2010, a lateral MTJ layer (free layer 110, tunnel barrier 114, and pinning layer 112) is formed on the vertical sidewall of at least one trench 902. At frame 2012, bit line 130 is formed between pinning layers 112 within at least one trench 902. At frame 214, an isolation trench 1104 is formed within stack 602 to define and isolate multiple 3D MRAM arrays 102.

[0128] At frame 2016, the second sacrificial layer 606 of stack 602 and adjacent portions of the MTJ layer are etched away to form a cavity 1202 within stack 602 and define the MTJ structure 108. This etching process also exposes corresponding portions of bit lines 130 in each cavity 1202. At frame 2018, cavities 1202 are filled with insulating material to form an insulating layer that contacts the corresponding portions of bit lines 130. At frame 2020, the first sacrificial layer 604 of stack 602 is etched away to form a cavity 1402, thereby exposing at least a first layer (e.g., free layer 110) of the MTJ structure 108. At frame 2022, word line connectors 116 that contact the first layer of the MTJ structure 108 are formed within each of these cavities 1402. At frame 2024, an isolation layer 134 is formed within an isolation trench 1104. At frame 2026, a contact through-hole 1804 is formed within the stepped structure 702 formed at frame 2006. Then, at frame 2028, an electrical contact 1902 is formed within the through-hole 1804.

[0129] It should be noted that not all activities or elements described in the general description above are necessary. A portion of a particular activity or apparatus may be unnecessary and may perform one or more additional activities besides those described, or may include one or more additional elements besides those described. Furthermore, the listed order of activities is not necessarily the order in which the activities are performed. In addition, concepts have been described with reference to specific embodiments. However, those skilled in the art will understand that various modifications and changes can be made without departing from the scope of this disclosure as set forth in the appended claims. Therefore, the specification and drawings should be considered illustrative rather than restrictive, and all such modifications are contemplated to be included within the scope of this disclosure.

[0130] The foregoing description of specific embodiments has described benefits, other advantages, and solutions to problems. However, these benefits, advantages, solutions, and any features that may bring about or make more significant any benefit, advantage, or solution should not be construed as key, essential, or necessary features of any or all claims. Furthermore, the specific embodiments disclosed above are merely illustrative, as the disclosed subject matter can be modified and practiced in different but equivalent ways that will be apparent to those skilled in the art from the teachings herein. No limitation is intended to be made on the details of the constructions or designs shown herein other than those described in the appended claims. It is therefore apparent that the specific embodiments disclosed above can be altered or modified, and all such changes are considered to be within the scope of the disclosed subject matter. Therefore, the protection sought herein is as set forth in the appended claims.

Claims

1. A three-dimensional (3D) magnetoresistive random access memory (MRAM) device, characterized in that, include: A plurality of cells are stacked in a direction perpendicular to the main surface of the substrate of the MRAM device. Each of the plurality of cells includes a magnetic tunnel junction (MTJ) structure and a first interconnect structure of a first type, the first interconnect structure being configured to interface with the MTJ structure of the cell. Each of the plurality of cells is separated from another cell of the plurality of cells by an insulating layer in a plurality of insulating layers. as well as The second interconnect structure of the second type is oriented orthogonally to the first interconnect structure of each of the first plurality of cells, and the second interconnect structure extends through the first plurality of cells to interface with the MTJ structure in each of the first plurality of cells.

2. The 3D MRAM device according to claim 1, characterized in that, The MTJ structure of each unit includes: The first magnetic layer has a variable magnetization state; A second magnetic layer having a fixed magnetization state; and An insulating layer is disposed between the first magnetic layer and the second magnetic layer.

3. The 3D MRAM device according to claim 2, characterized in that, For each of the first plurality of cells, the first interconnect structure is a word line connector that directly interfaces with the first magnetic layer and further with the access lines of the MRAM device, and the second interconnect structure is a bit line that directly interfaces with the second magnetic layer.

4. The 3D MRAM device according to claim 2, characterized in that, For each of the first plurality of cells, the first interconnect structure is a word line connector that directly interfaces with the second magnetic layer, and the second interconnect structure is a bit line that directly interfaces with the first magnetic layer.

5. The 3D MRAM device according to claim 2, characterized in that, For each of the first plurality of cells, the first interconnect structure is a bit line connector that directly interfaces with the first magnetic layer, and the second interconnect structure is a word line that directly interfaces with the second magnetic layer.

6. The 3D MRAM device according to claim 2, characterized in that, For each of the first plurality of cells, the first interconnect structure is a bit line connector that directly interfaces with the second magnetic layer, and the second interconnect structure is a word line that directly interfaces with the first magnetic layer.

7. The 3D MRAM device according to claim 2, characterized in that, Each of the first magnetic layer, the second magnetic layer, and the insulating layer of the MTJ structure of each unit has at least one main surface, the at least one main surface being parallel to each other and oriented perpendicular to the main surface of the substrate.

8. The 3D MRAM device according to claim 1, characterized in that, Further includes: A selector transistor coupled to the second interconnect structure and a selector line configured to activate the selector transistor.

9. A three-dimensional (3D) magnetoresistive random access memory (MRAM) device, characterized in that, include: A first plurality of cells are stacked in a direction perpendicular to the main surface of the substrate of the MRAM device. Each of the first plurality of cells is separated from another cell in the first plurality of cells by an insulating layer in a first plurality of insulating layers. Each of the first plurality of cells includes a word line connector and a magnetic tunnel junction (MTJ) structure, the MTJ structure comprising: A first magnetic layer, having a variable magnetization state, directly interfaces with the word line connector. The second magnetic layer has a fixed magnetization state, and An insulating layer is disposed between the first magnetic layer and the second magnetic layer; as well as The first bit line is oriented orthogonally to each word line connector of each of the first plurality of units, and the first bit line extends through the first plurality of units and directly interfaces with the second magnetic layer of the MTJ structure in each of the first plurality of units.

10. A method for manufacturing a three-dimensional (3D) magnetoresistive random access memory (MRAM) structure, characterized in that, include: This forms a multi-layered stack of alternating first and second sacrificial layers; At least one trench is formed in the multilayer stack; A transverse magnetic tunnel junction (MTJ) layer is formed on the vertical sidewall of the at least one trench; A first interconnect structure of a first type is formed in the at least one trench to contact the first layer in the lateral MTJ layer; and Multiple MRAM cells are formed within the multilayer stack. Each MRAM cell includes a second interconnect structure of the second type and a lateral MTJ structure. The lateral MTJ structure is formed by a portion of each layer in the lateral MTJ layer. The second interconnect structure contacts the second layer in the lateral MTJ layer.

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