Method for manufacturing vertical double-diffused metal oxide semiconductor field effect transistor

Abstract

This application provides a method for fabricating a vertically double-diffused metal-oxide-semiconductor field-effect transistor (MOSFET), relating to the field of semiconductor technology. The method includes: providing a substrate, the substrate including a first surface and a second surface; forming a field oxide layer on the first surface, the field oxide layer including a first ion implantation window and a second ion implantation window; performing ion implantation through the second ion implantation window to form multiple field-limiting rings; performing ion implantation through the first ion implantation window with a first implantation energy and a first implantation dose; performing ion implantation through the first ion implantation window with a second implantation energy and a second implantation dose to form a junction field-effect transistor region; wherein the first implantation energy is less than the second implantation energy, and the first implantation dose is greater than the second implantation dose; forming a gate oxide layer and forming a polycrystalline gate; and forming a P-type body region, an N+ type source region, and a P+ type deep body region in the active region. This achieves a synergistic effect of low on-resistance and high avalanche capability, thereby improving single-pulse avalanche energy.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a method for fabricating a vertically double-diffused metal-oxide-semiconductor field-effect transistor. Background Technology

[0002] Vertical double diffused metal-oxide semiconductor (VDMOS) transistors have been widely used in various fields such as power management and drive circuits due to their characteristics such as fast switching speed, low loss, high input impedance, low drive power, good frequency characteristics, high transconductance and high linearity.

[0003] Single-pulsed avalanche energy (EAS) is the maximum energy a device can dissipate during a single avalanche event, and it is a crucial indicator of a VDMOS device's resistance to avalanche breakdown. In practical applications, when a VDMOS is in an avalanche state, excessively high energy can cause a rapid rise in device temperature, leading to thermal breakdown and other problems that affect the device's reliability and lifespan. However, traditional VDMOS fabrication methods have certain limitations in improving single-pulsed avalanche energy. Summary of the Invention

[0004] In order to at least overcome the above-mentioned deficiencies in the prior art, the purpose of this application is to provide a method for fabricating a vertical double-diffused metal-oxide-semiconductor field-effect transistor.

[0005] In a first aspect, embodiments of this application provide a method for fabricating a vertically double-diffused metal-oxide-semiconductor field-effect transistor, the method comprising:

[0006] A substrate is provided, the substrate including a first surface and a second surface disposed opposite to each other; A field oxide layer is formed on the first surface, and an active region and a terminal region are defined by the field oxide layer; the field oxide layer includes a first ion implantation window located in the active region and a second ion implantation window located in the terminal region; Ions are implanted into the terminal region through the second ion implantation window to form multiple field-confining rings; wherein the depths of the multiple field-confining rings are different. Ions are implanted into the active region through the first ion implantation window using a first implantation energy and a first implantation dose to form a first implantation region; Ion implantation is performed on the first implantation region through the first ion implantation window using a second implantation energy and a second implantation dose to form a junction field-effect transistor region; wherein, the first implantation energy is less than the second implantation energy, and the first implantation dose is greater than the second implantation dose; A gate oxide layer is formed within the first ion implantation window and the second ion implantation window, and a polycrystalline gate is formed on the side of the gate oxide layer and the field oxide layer away from the substrate. In the active region, a P-type body region, an N+ type source region, and a P+ type deep body region are formed sequentially.

[0007] In one possible implementation, the step of ion implanting the active region with a first implantation energy and a first implantation dose through the first ion implantation window to form a first implantation region includes: Phosphorus ions are implanted into the active region through the first ion implantation window using an ion implantation process with a first implantation energy and a first implantation dose, thereby forming a first implantation region. The first injection energy ranges from 60 keV to 80 keV, and the first injection dose ranges from 3 × 10⁻⁶. 12 cm -2 Up to 5×10 12 cm -2 ; The step of ion implanting the first implantation region with a second implantation energy and a second implantation dose through the first ion implantation window to form a junction field-effect transistor region includes: Phosphorus ions are implanted into the first implantation region through the first ion implantation window using an ion implantation process with a second implantation energy and a second implantation dose to form a junction field-effect transistor region. The second injection energy ranges from 120 keV to 180 keV, and the second injection dose ranges from 1 × 10⁻⁶. 12 cm -2 Up to 2×10 12 cm -2 .

[0008] In one possible implementation, the second ion implantation window is arranged around the first ion implantation window, and the second ion implantation window includes a first sub-window, a second sub-window, a third sub-window, and a fourth sub-window arranged sequentially in a direction away from the first ion implantation window. The step of performing ion implantation on the terminal region through multiple second ion implantation windows to form multiple field-confined rings includes: Boron ions are implanted into the terminal region through the first sub-window using an ion implantation process with a third implantation energy and a third implantation dose to form a first field-limited ring. Boron ions are implanted into the terminal region through the second sub-window using an ion implantation process with a fourth implantation energy and a fourth implantation dose to form a second field-limited ring. Boron ions are implanted into the terminal region through the third sub-window using an ion implantation process with a fifth implantation energy and a fifth implantation dose to form a third field-limited ring. Boron ions are implanted into the terminal region through the fourth sub-window using an ion implantation process with a sixth implantation energy and a sixth implantation dose to form a fourth field-limited ring. Wherein, the third injection energy is less than the fourth injection energy, the fourth injection energy is less than the fifth injection energy, and the fifth injection energy is less than the sixth injection energy; the third injection dose is greater than the fourth injection dose, the fourth injection dose is greater than the fifth injection dose, and the fifth injection dose is greater than the sixth injection dose; the depth of the first field limiting loop is less than the depth of the second field limiting loop, the depth of the second field limiting loop is less than the depth of the third field limiting loop, and the depth of the third field limiting loop is less than the depth of the fourth field limiting loop.

[0009] In one possible implementation, the third injection energy is 80 keV, the fourth injection energy is 100 keV, the fifth injection energy is 120 keV, and the sixth injection energy is 150 keV; the third injection dose is 2.0 × 10⁻⁶. 13 cm -2 The fourth injection dose is 1.5 × 10⁻⁶. 13 cm -2 The fifth injection dose is 1.0 × 10⁻⁶. 13 cm -2 The sixth injection dose is 5.0 × 10⁻⁶. 12 cm -2 .

[0010] In one possible implementation, after the steps of sequentially forming a P-type body region, an N+ type source region, and a P+ type deep body region in the active region, the method further includes: Impurity ions in the P-type body region, the N+ type source region, and the P+ type deep body region are activated using an annealing process; An interlayer dielectric layer is formed on the side of the polycrystalline gate away from the first surface; A first metal layer is formed on the side of the interlayer dielectric layer away from the first surface, and the first metal layer is patterned to form a first electrode; A second metal layer is formed on the second surface as a second electrode.

[0011] In one possible implementation, the step of forming a first metal layer on the side of the interlayer dielectric layer away from the first surface includes: The interlayer dielectric layer and the field oxide layer are etched to form contact holes; Platinum ions are implanted into the substrate through the contact holes to form a metal film. A first metal layer is formed on the side of the interlayer dielectric layer away from the first surface using a magnetron sputtering process, and at least a portion of the first metal layer is located within the contact hole.

[0012] In one possible implementation, the step of forming a second metal layer as a second electrode on the second surface includes: The second surface is thinned. Phosphorus ions are implanted into the second surface to form an N+ type buffer layer; Metal evaporation is performed on the side of the N+ type buffer layer away from the second surface to form a second metal layer as the second electrode.

[0013] In one possible implementation, after the step of implanting phosphorus ions into the second surface to form an N+ type buffer layer, the method further includes: A protective layer is formed on the side of the first electrode away from the first surface using a plasma-enhanced chemical vapor deposition process. The orthogonal projection of the protective layer on the substrate completely covers the orthogonal projections of the first electrode and the interlayer dielectric layer on the substrate.

[0014] Secondly, embodiments of this application also provide a vertically double-diffused metal-oxide-semiconductor field-effect transistor (MOSFET), which is manufactured by the fabrication method of a vertically double-diffused metal-oxide-semiconductor field-effect transistor as described in any of the above aspects.

[0015] Thirdly, embodiments of this application also provide an electronic device, the electronic device comprising a vertically double-diffused metal-oxide-semiconductor field-effect transistor as described in any of the above aspects.

[0016] Based on any of the above aspects, the fabrication method of the vertical double-diffused metal-oxide-semiconductor field-effect transistor provided in this application can achieve a synergistic effect of low on-resistance and high avalanche capability by using two ion implantations with different energies and doses to form a junction field-effect transistor region, thereby improving the single-pulse avalanche energy of the device and shifting the avalanche breakdown location to the active region, where it is uniformly distributed, avoiding device failure caused by edge breakdown and local overheating, thus improving the reliability of the device. It is suitable for the large-scale production of high-reliability VDMOS devices. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings required in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is one of the flowcharts illustrating the fabrication method of the vertical double-diffused metal-oxide-semiconductor field-effect transistor provided in this embodiment; Figure 2 This is one of the structural schematic diagrams of the vertical double-diffused metal-oxide-semiconductor field-effect transistor provided in this embodiment; Figure 3 This is the second schematic diagram of the vertical double-diffused metal-oxide-semiconductor field-effect transistor provided in this embodiment; Figure 4 This is the third schematic diagram of the vertical double-diffused metal-oxide-semiconductor field-effect transistor provided in this embodiment; Figure 5 This is the fourth schematic diagram of the vertical double-diffused metal-oxide-semiconductor field-effect transistor provided in this embodiment; Figure 6 This is the fifth schematic diagram of the vertical double-diffused metal-oxide-semiconductor field-effect transistor provided in this embodiment; Figure 7 This is the sixth schematic diagram of the vertical double-diffused metal-oxide-semiconductor field-effect transistor provided in this embodiment; Figure 8 This is a schematic diagram of the sub-steps of step S130 provided in this embodiment; Figure 9 This is the second schematic flowchart of the fabrication method of the vertical double-diffused metal-oxide-semiconductor field-effect transistor provided in this embodiment; Figure 10 This is the seventh schematic diagram of the vertical double-diffused metal-oxide-semiconductor field-effect transistor provided in this embodiment; Figure 11 This is a schematic diagram of the sub-steps of step S230 provided in this embodiment; Figure 12 This is the eighth schematic diagram of the vertical double-diffused metal-oxide-semiconductor field-effect transistor provided in this embodiment; Figure 13 This is the ninth schematic diagram of the vertical double-diffused metal-oxide-semiconductor field-effect transistor provided in this embodiment; Figure 14 This is the tenth schematic diagram of the vertical double-diffused metal-oxide-semiconductor field-effect transistor provided in this embodiment; Figure 15This is a schematic diagram of the sub-steps of step S240 provided in this embodiment; Figure 16 This is eleventh of the structural schematic diagrams of the vertical double-diffused metal-oxide-semiconductor field-effect transistor provided in this embodiment; Figure 17 This is the twelfth schematic diagram of the vertical double-diffused metal-oxide-semiconductor field-effect transistor provided in this embodiment; Figure 18 This is the thirteenth schematic diagram of the vertical double-diffused metal-oxide-semiconductor field-effect transistor provided in this embodiment.

[0019] Icons: 100 - Substrate; 110 - First surface; 120 - Second surface; 200 - Field oxide layer; 210 - First ion implantation window; 220 - Second ion implantation window; 221 - First sub-window; 222 - Second sub-window; 223 - Third sub-window; 224 - Fourth sub-window; 300 - Photoresist layer; 410 - Field confinement ring; 411 - First field confinement ring; 412 - Second field confinement ring; 413 - Third field confinement ring; 414 - Fourth field confinement ring; 420 - Junction field-effect transistor region; 510 - Gate oxide layer; 520 - Polycrystalline gate; 430 - P-type body region; 440 - N+ type source region; 450 - P+ type deep body region; 600 - Interlayer dielectric layer; 710 - Contact hole; 720 - Metal film layer; 810 - First electrode; 820 - Second electrode; 910 - N+ type buffer layer; 920 - Protective layer. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0022] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0023] In the description of this application, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. In addition, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0024] Furthermore, terms such as "horizontal," "vertical," and "sag" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal relative to "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0025] In the description of this application, it should also be noted that, unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0026] It should be noted that, where there is no conflict, different features in the embodiments of this application can be combined with each other.

[0027] The inventors discovered that in traditional VDMOS fabrication processes, the uneven electric field distribution in the terminal region of VDMOS devices easily leads to electric field concentration, causing localized overheating during avalanche events and reducing single-pulse avalanche energy. Furthermore, the junction field-effect transistor region of VDMOS devices is formed through a single ion implantation, resulting in uneven impurity distribution and affecting the device's control over channel current, thus negatively impacting single-pulse avalanche energy. Holes generated during avalanche accumulate in the P-type body region, triggering parasitic transistor activation and making the device prone to latch-up, further reducing single-pulse avalanche energy. Moreover, the lack of minority carrier lifetime control during VDMOS fabrication makes it difficult to achieve a balance between avalanche tolerance and on-resistance.

[0028] In view of this, this embodiment provides a solution that can reduce the risks of the above-mentioned problems. The solution provided in this embodiment will be described in detail below.

[0029] Please refer to Figure 1 , Figure 1Example: A schematic flowchart of the fabrication method of the vertical double-diffused metal-oxide-semiconductor field-effect transistor provided in this embodiment is shown. The fabrication method of the vertical double-diffused metal-oxide-semiconductor field-effect transistor includes the following steps.

[0030] Step S110: Provide a substrate 100, the substrate 100 including a first surface 110 and a second surface 120 disposed opposite to each other.

[0031] In this embodiment, the substrate 100 may include a substrate layer and an epitaxial layer located on one side of the substrate layer. The surface of the epitaxial layer away from the substrate layer is the first surface 110, and the surface of the substrate layer away from the epitaxial layer is the second surface 120. In some examples, both the substrate layer and the epitaxial layer are N-type doped, and the doping concentration of the substrate layer may be higher than that of the epitaxial layer; that is, the substrate layer may be an N+ type substrate, and the epitaxial layer may be an N- type epitaxial layer. The thickness of the epitaxial layer may range from 50 micrometers to 55 micrometers, and the resistivity of the epitaxial layer may range from 12 Ω·cm to 16 Ω·cm.

[0032] In some cases, vapor phase epitaxy (VPE) can be used on crystals with a crystal orientation of [missing information]. <111> An epitaxial layer is grown on a substrate, and after the epitaxial layer is formed, it is annealed in a nitrogen protective atmosphere to repair lattice defects. The annealing temperature can be 1100℃, and the annealing time can be 30 minutes.

[0033] Step S120: A field oxide layer 200 is formed on the first surface 110, and an active region and a terminal region are determined by the field oxide layer 200; the field oxide layer 200 includes a first ion implantation window 210 located in the active region and a second ion implantation window 220 located in the terminal region.

[0034] In this embodiment, a high-temperature thermal oxidation process combining dry and wet oxygen can be used to grow a field oxide layer 200 on the first surface 110, serving as an isolation layer and ion implantation masking layer in subsequent processes. A photoresist layer 300 is formed on the side of the field oxide layer 200 away from the first surface 110 using photolithography. Then, a buffered oxide etchant (BOE) is used to wet etch the field oxide layer 200 based on the photoresist layer 300 to remove a predetermined area, defining the active and termination regions of the device for subsequent ion implantation processes. Specifically, please refer to... Figure 2 When performing ion implantation on the terminal region, the photoresist layer 300 can define only the corresponding terminal region. Based on the terminal region defined by the photoresist layer 300, the field oxide layer 200 is etched to form a second ion implantation window 220 located in the terminal region, facilitating ion implantation on the terminal region. After ion implantation of the terminal region is completed, the photoresist layer 300 is removed. Please refer to... Figure 3 When performing ion implantation on the active region, a photoresist layer 300 can be re-formed on the side of the field oxide layer 200 away from the substrate. This photoresist layer 300 can define only the corresponding active region, thereby etching the field oxide layer 200 based on the active region defined by the photoresist layer 300 to form a first ion implantation window 210 located in the active region, which facilitates ion implantation on the active region. After the ion implantation on the active region is completed, the photoresist layer 300 is removed.

[0035] Both the first ion implantation window 210 and the second ion implantation window 220 expose the first surface 110. The first ion implantation window 210 can be located at the geometric center of the field oxide layer 200. The cross-sectional shape of the first ion implantation window 210 can be rectangular. The second ion implantation window 220 is arranged around the first ion implantation window 210. The shape of the second ion implantation window 220 can be annular.

[0036] In some examples, the growth temperature of the field oxide layer 200 can be 1050°C, and the thickness of the field oxide layer 200 can be from 8000 angstroms to 13000 angstroms. When etching the field oxide layer 200, the etching rate can be 100 Å / s to avoid damaging the first surface 110.

[0037] In step S130, ion implantation is performed on the terminal region through the second ion implantation window 220 to form multiple field confinement rings 410; wherein the depths of the multiple field confinement rings 410 are different.

[0038] In this embodiment, please refer to Figure 4 Ions can be implanted into the terminal region through the second ion implantation window 220 to form multiple field confinement rings 410. The depth of the multiple field confinement rings 410 increases sequentially along the direction away from the active region. In this way, the electric field distribution in the terminal region can be made more uniform, effectively alleviating the phenomenon of electric field concentration.

[0039] In some examples, the number of field limiting loops 410 can be four.

[0040] Step S140: Ion implantation is performed on the active region through the first ion implantation window 210 with a first implantation energy and a first implantation dose to form a first implantation region.

[0041] In this embodiment, a first implantation energy and a first implantation dose are used to perform a first ion implantation on the active region through the first ion implantation window 210 to form a first implantation region, thereby controlling the on-resistance and channel potential of the device surface. Specifically, a lower first implantation energy and a higher first implantation dose result in a shallower depth of the formed first implantation region.

[0042] Step S150: Ion implantation is performed on the first implantation region through the first ion implantation window 210 with the second implantation energy and the second implantation dose to form a junction field-effect transistor region 420; wherein, the first implantation energy is less than the second implantation energy, and the first implantation dose is greater than the second implantation dose.

[0043] In this embodiment, please refer to Figure 5 A second ion implantation can be performed on the active region through the first ion implantation window 210 using a second implantation energy and a second implantation dose to form a junction field-effect transistor region 420 based on the first implantation region. The second implantation energy is higher, and can be greater than the first implantation energy; the second implantation dose is lower, and can be less than the first implantation dose. The junction field-effect transistor region 420 has a relatively deep depth.

[0044] In the above design, by implanting ions with different energies and dosages twice to form the junction field-effect transistor region 420, longitudinal gradient doping can be achieved, the electric field distribution can be optimized, the avalanche current can be evenly distributed in the active region, local overheating can be avoided, the conduction probability of parasitic transistors can be reduced, and the single-pulse avalanche energy can be increased.

[0045] In step S160, a gate oxide layer 510 is formed in the first ion implantation window 210 and the second ion implantation window 220, and a polysilicon gate 520 is formed on the side of the gate oxide layer 510 and the field oxide layer 200 away from the substrate 100.

[0046] In this embodiment, please refer to Figure 6 A gate oxide layer 510 can be grown on the surfaces of the field limiting ring 410 and the junction field-effect transistor region 420 using a composite oxidation process of dry oxygen → wet oxygen → dry oxygen. Then, annealing is performed in a nitrogen protective atmosphere. The growth temperature of the gate oxide layer 510 ranges from 1000℃ to 1050℃, and the thickness of the gate oxide layer 510 is less than the thickness of the field oxide layer 200, ranging from 500 angstroms to 1200 angstroms. The annealing time can be 30 minutes, and the interface state density after annealing can be less than or equal to 1 × 10⁻⁶. 10 cm -2 ·eV -1 .

[0047] After forming the gate oxide layer 510, a polysilicon layer can be deposited on the side of the gate oxide layer 510 and the field oxide layer 200 away from the first surface 110 using a low-pressure chemical vapor deposition (LPCVD) process. Phosphorus ion implantation is then used for heavy doping to reduce the gate resistance. Finally, photolithography and dry etching processes are used to define the gate pattern, forming the polysilicon gate 520. The polysilicon gate 520 can completely cover the gate oxide layer 510 located within the first ion implantation window 210.

[0048] When depositing a polycrystalline silicon layer, the deposition temperature can range from 620°C to 700°C, and the thickness of the resulting polycrystalline silicon layer can be 6000 angstroms. During phosphorus ion implantation, the implantation energy can range from 50 keV to 100 keV, and the implantation dose can range from 5 × 10⁻⁶. 15 cm -2 Up to 8×10 15 cm -2 The sheet resistance after doping can range from 15Ω / □ to 25Ω / □. After forming the polycrystalline gate 520, annealing can be performed in a nitrogen protective atmosphere, where the annealing temperature can be 950℃ and the annealing time can be 20min to repair etch lattice damage.

[0049] In step S170, a P-type body region 430, an N+ type source region 440, and a P+ type deep body region 450 are sequentially formed in the active region.

[0050] In this embodiment, please refer to Figure 7 A P-type body region 430 can be formed on the first surface 110 of the substrate 100 by boron ion implantation. The P-type body region 430 is disposed around the junction field-effect transistor region 420, and the edge of the P-type body region 430 contacts the edge of the junction field-effect transistor region 420. The polysilicon gate 520 can expose at least a portion of the P-type body region 430. In the direction perpendicular to the substrate 100, the depth of the P-type body region 430 can be greater than the depth of the junction field-effect transistor region 420.

[0051] Specifically, after boron ion implantation, propagation can be carried out in an atmosphere of nitrogen and oxygen to allow impurities to diffuse laterally and longitudinally, forming the desired impurity distribution. The energy range of boron ion implantation is 80 keV to 100 keV, and the implantation dose can range from 2 × 10⁻⁶. 13 cm -2 Up to 8×10 13 cm -2 The propulsion temperature range is from 1050℃ to 1200℃, and the propulsion time is from 60min to 300min.

[0052] After forming the P-type body region 430, arsenic ions can be implanted into the P-type body region 430 to form the N+ type source region 440. The implantation energy of arsenic ions can be from 80 keV to 120 keV, and the implantation dose can be in the range of 3 × 10⁻⁶. 15 cm -2 Up to 8×10 15 cm -2 .

[0053] After forming the N+ type source region 440, boron ions can be implanted into the P-type body region 430 to form a P+ type deep body region 450. The P+ type deep body region 450 can form a self-aligned structure with the N+ type source region 440 to achieve an ohmic short circuit between the source metal and the P-type body region 430, thereby suppressing latch-up effects. The boron ion implantation energy can be from 40 keV to 120 keV, and the implantation dose can range from 0.2 × 10⁻⁶. 15 cm -2 Up to 3×10 15 cm -2 .

[0054] Based on the above design, in the fabrication method of the vertical double-diffused metal-oxide-semiconductor field-effect transistor provided in this embodiment, by using two ion implantations with different energies and doses to form the junction field-effect transistor region 420, it is possible to achieve a synergistic effect of low on-resistance and high avalanche capability, increase the single-pulse avalanche energy of the device by more than 30%, and transfer the avalanche breakdown location to the active region, which is uniformly distributed in the active region, avoiding device failure caused by edge breakdown and local overheating, thereby improving the reliability of the device and making it suitable for the large-scale production of high-reliability VDMOS devices.

[0055] In one possible implementation, in step S140, an ion implantation process can be used to implant phosphorus ions into the active region through a first ion implantation window 210 with a first implantation energy and a first implantation dose to form a first implantation region; wherein the first implantation energy ranges from 60 keV to 80 keV, and the first implantation dose ranges from 3 × 10⁻⁶. 12 cm -2 Up to 5×10 12 cm -2 .

[0056] In this embodiment, when the active region is implanted with ions for the first time, the depth of the first implantation region is shallow due to the low implantation energy, and the doping concentration of the first implantation region can reach a high level due to the high implantation dose, so as to precisely control the on-resistance of the device surface and the potential distribution of the channel region.

[0057] In step S150, phosphorus ions can be implanted into the first implantation region through the first ion implantation window 210 using an ion implantation process with a second implantation energy and a second implantation dose to form a junction field-effect transistor region 420; wherein the second implantation energy ranges from 120 keV to 180 keV, and the second implantation dose ranges from 1 × 10⁻⁶. 12 cm -2 Up to 2×10 12 cm -2 .

[0058] In this embodiment, when the active region is implanted with ions for the second time, the impurities implanted in the second ion implantation are the same as those implanted in the first ion implantation, and the second implantation energy is greater than the first implantation energy, which enables the ion implantation to be deeper and form a deeper junction field-effect transistor region 420. In addition, the second implantation dose is less than the first implantation dose, which can form a relatively low doping concentration in the deeper region.

[0059] In the above design, by employing a low-energy, high-dose first ion implantation and a high-energy, low-dose second ion implantation to form the junction field-effect transistor region 420, a vertically gradient doping of the junction field-effect transistor region 420 can be achieved, thereby increasing the single-pulse avalanche energy and enhancing the reliability and stability of the device. Simultaneously, this vertically gradient doping structure also optimizes the electric field distribution, making the avalanche current more uniformly distributed within the active region, avoiding device damage due to localized overheating and reducing the probability of parasitic transistor conduction. Furthermore, the higher doping concentration on the side of the junction field-effect transistor region 420 closer to the first surface 110 is beneficial for controlling the on-resistance, while the lower doping concentration on the side farther from the first surface 110 improves the breakdown voltage and avalanche capability, thus achieving an optimal balance between low on-resistance and high avalanche energy.

[0060] In one possible implementation, please refer again. Figure 4 The second ion implantation window 220 is arranged around the first ion implantation window 210. The second ion implantation window 220 includes a first sub-window 221, a second sub-window 222, a third sub-window 223 and a fourth sub-window 224 arranged sequentially in a direction away from the first ion implantation window 210.

[0061] In this embodiment, in a direction parallel to the substrate 100, the first sub-window 221, the second sub-window 222, the third sub-window 223 and the fourth sub-window 224 are arranged sequentially in a direction away from the first ion implantation window 210. The shape of the first ion implantation window 210 can be rectangular, and the first sub-window 221, the second sub-window 222, the third sub-window 223 and the fourth sub-window 224 can be annular.

[0062] Please refer to Figure 8 Step S130 may include the following sub-steps.

[0063] Step S131: Boron ions are implanted into the terminal region through the first sub-window 221 using an ion implantation process with a third implantation energy and a third implantation dose to form a first field-limiting ring 411.

[0064] In this embodiment, photoresist can be used to cover the second sub-window 222, the third sub-window 223, and the fourth sub-window 224, exposing only the first sub-window 221. Boron ions are then implanted into the terminal region through the first sub-window 221 using an ion implantation process with a third implantation energy and a third implantation dose, forming a first field-limiting ring 411. The third implantation energy is 80 keV, and the third implantation dose is 2.0 × 10⁻⁶ keV. 13 cm -2 .

[0065] In step S132, boron ions are implanted into the terminal region through the second sub-window 222 using an ion implantation process with a fourth implantation energy and a fourth implantation dose to form a second field-limiting ring 412.

[0066] In this embodiment, photoresist can be used to cover the first sub-window 221, the third sub-window 223, and the fourth sub-window 224, exposing only the second sub-window 222. Ion implantation is then used with a fourth implantation energy and a fourth implantation dose to implant boron ions into the terminal region through the second sub-window 222, forming a second field-limiting ring 412. The second field-limiting ring 412 surrounds the first field-limiting ring 411 and is located on the side of the first field-limiting ring 411 away from the first ion implantation window 210. The fourth implantation energy is 100 keV, and the fourth implantation dose is 1.5 × 10⁻⁶ keV. 13 cm -2 Since the fourth implantation energy is greater than the third implantation energy, the depth of the second field confinement ring 412 can be greater than the depth of the first field confinement ring 411. Since the fourth implantation dose is less than the third implantation dose, the doping concentration of the second field confinement ring 412 can be less than the doping concentration of the first field confinement ring 411.

[0067] In step S133, boron ions are implanted into the terminal region through the third sub-window 223 using an ion implantation process with a fifth implantation energy and a fifth implantation dose, forming a third field-limiting ring 413.

[0068] In this embodiment, photoresist can be used to cover the first sub-window 221, the second sub-window 222, and the fourth sub-window 224, exposing only the third sub-window 223. Ion implantation is then used with a fifth implantation energy and a fifth implantation dose to implant boron ions into the terminal region through the third sub-window 223, forming a third field-limiting ring 413. The third field-limiting ring 413 surrounds the second field-limiting ring 412 and is located on the side of the second field-limiting ring 412 away from the first ion implantation window 210. The fifth implantation energy is 120 keV, and the fifth implantation dose is 1.0 × 10⁻⁶. 13 cm -2 Since the fifth implantation energy is greater than the fourth implantation energy, the depth of the third field confinement ring 413 can be greater than the depth of the second field confinement ring 412. Since the fifth implantation dose is less than the fourth implantation dose, the doping concentration of the third field confinement ring 413 can be less than the doping concentration of the second field confinement ring 412.

[0069] In step S134, boron ions are implanted into the terminal region through the fourth sub-window 224 using an ion implantation process with a sixth implantation energy and a sixth implantation dose to form a fourth field-limiting ring 414.

[0070] In this embodiment, photoresist can be used to cover the first sub-window 221, the second sub-window 222, and the third sub-window 223, exposing only the fourth sub-window 224. Ion implantation is then used with a sixth implantation energy and a sixth implantation dose to implant boron ions into the terminal region through the fourth sub-window 224, forming a fourth field-limiting ring 414. The fourth field-limiting ring 414 surrounds the third field-limiting ring 413 and is located on the side of the third field-limiting ring 413 furthest from the first ion implantation window 210. The sixth implantation energy is 150 keV, and the sixth implantation dose is 5.0 × 10⁻⁶ keV. 12 cm -2 Since the sixth implantation energy is greater than the fifth implantation energy, the depth of the fourth field confinement ring 414 can be greater than the depth of the third field confinement ring 413. Since the sixth implantation dose is less than the fifth implantation dose, the doping concentration of the fourth field confinement ring 414 can be less than the doping concentration of the third field confinement ring 413.

[0071] In the above design, the third, fourth, fifth, and sixth implantation energies increase sequentially, resulting in sequentially increasing depths of the first field-limiting ring 411, second field-limiting ring 412, third field-limiting ring 413, and fourth field-limiting ring 414, respectively. Conversely, the third, fourth, fifth, and sixth implantation doses decrease sequentially, resulting in sequentially decreasing doping concentrations of the first, second, third, and fourth field-limiting rings 411, 412, 413, and 414. This allows for the formation of multiple gradient-doped field-limiting rings 410 in the terminal region, leading to a more uniform electric field distribution and effectively improving the device's breakdown voltage. Furthermore, it prevents the electric field from concentrating at a single point, shifting the avalanche breakdown location from the edge to the active region, thereby reducing the risk of device breakdown under high voltage.

[0072] It should be noted that the number of sub-windows included in the second ion implantation window 220 is not limited to four, and the number of field confinement rings 410 formed is not limited to four. The number of sub-windows included in the second ion implantation window 220 and the number of field confinement rings 410 can also be three, five, etc., which can be adjusted according to actual needs, and no specific limitation is made here.

[0073] In one possible implementation, please refer to Figure 9 After step S170, and after the step of sequentially forming a P-type body region 430, an N+ type source region 440, and a P+ type deep body region 450 in the active region, the method for fabricating a vertical double-diffused metal-oxide-semiconductor field-effect transistor may further include the following steps.

[0074] Step S210: The impurity ions in the P-type body region 430, the N+ type source region 440 and the P+ type deep body region 450 are activated by annealing.

[0075] In this embodiment, a rapid thermal annealing (RTA) process can be used to activate impurity ions in the P-type body region 430, N+ type source region 440, and P+ type deep body region 450, and repair lattice damage. The annealing temperature can be 1050°C, and the annealing time can be 10 seconds.

[0076] In step S220, an interlayer dielectric layer 600 is formed on the side of the polycrystalline gate 520 away from the first surface 110.

[0077] In this embodiment, please refer to Figure 10An interlayer dielectric layer 600 can be formed on the side of the polycrystalline gate 520 away from the first surface 110 using plasma-enhanced chemical vapor deposition (PECVD) and atmospheric pressure chemical vapor deposition (APCVD) processes. The interlayer dielectric layer 600 can completely cover the polycrystalline gate 520 and the field oxide layer 200 exposed by the polycrystalline gate 520. The interlayer dielectric layer 600 can include a first sublayer and a second sublayer stacked sequentially in the direction away from the substrate 100. The material of the first sublayer can be silicon dioxide (SiO2), and the material of the second sublayer can be borosilicate glass (BPSG). The thickness of the first sublayer can be 2000 angstroms to 4000 angstroms, and the thickness of the second sublayer can be 8000 angstroms to 10000 angstroms.

[0078] In step S230, a first metal layer is formed on the side of the interlayer dielectric layer 600 away from the first surface 110, and the first metal layer is patterned to form a first electrode 810.

[0079] In this embodiment, a first metal layer can be formed on the side of the interlayer dielectric layer 600 away from the first surface 110. Then, the first metal layer is processed by photolithography and dry etching to form a source electrode and a gate electrode as the first electrode 810, so as to reduce the thermal resistance and conduction loss of the device.

[0080] Step S240: A second metal layer is formed on the second surface 120 as a second electrode 820.

[0081] In this embodiment, a second metal layer can be formed on the second surface 120 of the substrate 100 as a second electrode 820.

[0082] In one possible implementation, please refer to Figure 11 Step S230 may include the following sub-steps.

[0083] Step S231: Etch the interlayer dielectric layer 600 and the field oxide layer 200 to form contact holes 710.

[0084] In this embodiment, please refer to Figure 12 The contact hole 710 region can be defined using photolithography, and the interlayer dielectric layer 600 and field oxide layer 200 can be processed using dry etching to form the contact hole 710 that exposes the first surface 110.

[0085] In step S232, platinum ions are implanted into the substrate 100 through the contact hole 710 to form a metal film layer 720.

[0086] In this embodiment, please refer to Figure 13 Platinum ion implantation can be performed through contact hole 710 to control the lifetime of minority carriers, followed by low-temperature annealing to form stable deep-level recombination centers. The platinum ion implantation energy ranges from 0.5 MeV to 3 MeV, and the implantation dose is 1 × 10⁻⁶. 11 cm -2 Up to 8×10 11 cm -2 The annealing temperature was 430℃, and the annealing time was 30 minutes.

[0087] In the above design, by performing platinum ion implantation, the minority carrier lifetime can be precisely controlled, which helps to suppress the conduction of parasitic thyristors, block the positive feedback path of avalanche secondary breakdown, and significantly improve the single-pulse avalanche energy of the device.

[0088] Step S233: A first metal layer is formed on the side of the interlayer dielectric layer 600 away from the first surface 110 using a magnetron sputtering process, and at least a portion of the first metal layer is located within the contact hole 710.

[0089] In this embodiment, please refer to Figure 14 A first metal layer can be formed on the side of the interlayer dielectric layer 600 away from the first surface 110 using a magnetron sputtering process. The first metal layer can completely fill the contact hole 710. The material of the first metal layer can be an aluminum-silicon-copper alloy, and the thickness of the first metal layer can be 4 micrometers.

[0090] After the first metal layer is formed, it can be processed by photolithography and dry etching to form the source electrode and the gate electrode as the first electrode 810.

[0091] In one possible implementation, please refer to Figure 15 Step S240 may include the following sub-steps.

[0092] Step S241: Thinning treatment is performed on the second surface 120.

[0093] In this embodiment, a combination of mechanical grinding and chemical polishing can be used to thin the substrate 100, so that the thickness of the thinned substrate 100 is 180 micrometers to 300 micrometers, and the thinning uniformity is less than or equal to ±5 micrometers.

[0094] Step S242: Phosphorus ions are implanted into the second surface 120 to form an N+ type buffer layer 910.

[0095] In this embodiment, please refer to Figure 16 Phosphorus ions can be implanted into the second surface 120 of the thinned substrate 100 to form an N+ type buffer layer 910, followed by annealing in a nitrogen protective atmosphere to optimize the longitudinal electric field distribution of the device and improve its breakdown voltage. The phosphorus ion implantation energy is from 0.5 MeV to 1.5 MeV, and the implantation dose is 1 × 10⁻⁶. 15 cm -2 Up to 5×10 15 cm -2 The annealing temperature was 1100℃, and the annealing time was 30 minutes.

[0096] In step S243, metal evaporation is performed on the side of the N+ type buffer layer 910 away from the second surface 120 to form a second metal layer as the second electrode 820.

[0097] In this embodiment, please refer to Figure 17 A second metal layer, serving as the second electrode 820, can be formed on the side of the N+ type buffer layer 910 away from the second surface 120 using an evaporation process. This second metal layer can be composed of multiple layers of titanium, nickel, and silver. The thicknesses of the titanium, nickel, and silver metal layers are 1000 angstroms, 5000 angstroms, and 10000 angstroms, respectively.

[0098] In one possible implementation, please refer to Figure 18 After phosphorus ions are injected into the second surface 120 to form an N+ type buffer layer 910, a protective layer 920 can be formed on the side of the first electrode 810 away from the first surface 110 using a plasma enhanced chemical vapor deposition (PECVD) process. After deposition, alloying is performed to stabilize the ohmic contact between the metal and silicon. The orthogonal projection of the protective layer 920 on the substrate 100 completely covers the orthogonal projections of the first electrode 810 and the interlayer dielectric layer 600 on the substrate 100.

[0099] In this embodiment, the material of the protective layer 920 can be silicon nitride, the thickness of the protective layer 920 can be 5000 angstroms to 8000 angstroms, the alloying temperature is 450°C, and the alloying time is 30 minutes.

[0100] This application also provides a vertically double-diffused metal-oxide-semiconductor field-effect transistor (MOSFET), which can be manufactured using the method for manufacturing a vertically double-diffused metal-oxide-semiconductor field-effect transistor provided in this embodiment.

[0101] This application also provides an electronic device, which may include the vertical double-diffused metal-oxide-semiconductor field-effect transistor provided in this embodiment.

[0102] In summary, this embodiment provides a method for fabricating a vertical double-diffused metal-oxide-semiconductor field-effect transistor (VDMOS). By employing two ion implantations with different energies and dosages to form a junction field-effect transistor region, a synergistic effect of low on-resistance and high avalanche capability can be achieved, thereby enhancing the single-pulse avalanche energy of the device. Furthermore, the avalanche breakdown location is shifted to the active region and uniformly distributed within the active region, avoiding device failure caused by edge breakdown and localized overheating, thus improving the reliability of the device. This method is suitable for the large-scale production of high-reliability VDMOS devices.

[0103] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0104] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a vertically double-diffused metal-oxide-semiconductor field-effect transistor, characterized in that, The method includes: A substrate is provided, the substrate including a first surface and a second surface disposed opposite to each other; A field oxide layer is formed on the first surface, and an active region and a terminal region are defined by the field oxide layer; the field oxide layer includes a first ion implantation window located in the active region and a second ion implantation window located in the terminal region; Ions are implanted into the terminal region through the second ion implantation window to form multiple field-confining rings; wherein the depths of the multiple field-confining rings are different. Ions are implanted into the active region through the first ion implantation window using a first implantation energy and a first implantation dose to form a first implantation region; Ion implantation is performed on the first implantation region through the first ion implantation window using a second implantation energy and a second implantation dose to form a junction field-effect transistor region; wherein, the first implantation energy is less than the second implantation energy, and the first implantation dose is greater than the second implantation dose; A gate oxide layer is formed within the first ion implantation window and the second ion implantation window, and a polycrystalline gate is formed on the side of the gate oxide layer and the field oxide layer away from the substrate. In the active region, a P-type body region, an N+ type source region, and a P+ type deep body region are formed sequentially.

2. The method for fabricating a vertical double-diffused metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, The step of ion implanting the active region with a first implantation energy and a first implantation dose through the first ion implantation window to form a first implantation region includes: Phosphorus ions are implanted into the active region through the first ion implantation window using an ion implantation process with a first implantation energy and a first implantation dose, thereby forming a first implantation region. The first injection energy ranges from 60 keV to 80 keV, and the first injection dose ranges from 3 × 10⁻⁶. 12 cm -2 Up to 5×10 12 cm -2 ; The step of ion implanting the first implantation region with a second implantation energy and a second implantation dose through the first ion implantation window to form a junction field-effect transistor region includes: Phosphorus ions are implanted into the first implantation region through the first ion implantation window using an ion implantation process with a second implantation energy and a second implantation dose to form a junction field-effect transistor region. The second injection energy ranges from 120 keV to 180 keV, and the second injection dose ranges from 1 × 10⁻⁶. 12 cm -2 Up to 2×10 12 cm -2 .

3. The method for fabricating a vertically double-diffused metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, The second ion implantation window is arranged around the first ion implantation window, and the second ion implantation window includes a first sub-window, a second sub-window, a third sub-window, and a fourth sub-window arranged sequentially in a direction away from the first ion implantation window; The step of performing ion implantation on the terminal region through multiple second ion implantation windows to form multiple field-confined rings includes: Boron ions are implanted into the terminal region through the first sub-window using an ion implantation process with a third implantation energy and a third implantation dose to form a first field-limited ring. Boron ions are implanted into the terminal region through the second sub-window using an ion implantation process with a fourth implantation energy and a fourth implantation dose to form a second field-limited ring. Boron ions are implanted into the terminal region through the third sub-window using an ion implantation process with a fifth implantation energy and a fifth implantation dose to form a third field-limited ring. Boron ions are implanted into the terminal region through the fourth sub-window using an ion implantation process with a sixth implantation energy and a sixth implantation dose to form a fourth field-limited ring. Wherein, the third injection energy is less than the fourth injection energy, the fourth injection energy is less than the fifth injection energy, and the fifth injection energy is less than the sixth injection energy; the third injection dose is greater than the fourth injection dose, the fourth injection dose is greater than the fifth injection dose, and the fifth injection dose is greater than the sixth injection dose; the depth of the first field limiting loop is less than the depth of the second field limiting loop, the depth of the second field limiting loop is less than the depth of the third field limiting loop, and the depth of the third field limiting loop is less than the depth of the fourth field limiting loop.

4. The method for fabricating a vertically double-diffused metal-oxide-semiconductor field-effect transistor according to claim 3, characterized in that, The third injection energy is 80 keV, the fourth injection energy is 100 keV, the fifth injection energy is 120 keV, and the sixth injection energy is 150 keV; the third injection dose is 2.0 × 10⁻⁶. 13 cm -2 The fourth injection dose is 1.5 × 10⁻⁶. 13 cm -2 The fifth injection dose is 1.0 × 10⁻⁶. 13 cm -2 The sixth injection dose is 5.0 × 10⁻⁶. 12 cm -2 .

5. The method for fabricating a vertically double-diffused metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, After the steps of sequentially forming a P-type body region, an N+ type source region, and a P+ type deep body region in the active region, the method further includes: Impurity ions in the P-type body region, the N+ type source region, and the P+ type deep body region are activated using an annealing process; An interlayer dielectric layer is formed on the side of the polycrystalline gate away from the first surface; A first metal layer is formed on the side of the interlayer dielectric layer away from the first surface, and the first metal layer is patterned to form a first electrode; A second metal layer is formed on the second surface as a second electrode.

6. The method for fabricating a vertically double-diffused metal-oxide-semiconductor field-effect transistor according to claim 5, characterized in that, The step of forming a first metal layer on the side of the interlayer dielectric layer away from the first surface includes: The interlayer dielectric layer and the field oxide layer are etched to form contact holes; Platinum ions are implanted into the substrate through the contact holes to form a metal film. A first metal layer is formed on the side of the interlayer dielectric layer away from the first surface using a magnetron sputtering process, and at least a portion of the first metal layer is located within the contact hole.

7. The method for fabricating a vertically double-diffused metal-oxide-semiconductor field-effect transistor according to claim 5, characterized in that, The step of forming a second metal layer as a second electrode on the second surface includes: The second surface is thinned. Phosphorus ions are implanted into the second surface to form an N+ type buffer layer; Metal evaporation is performed on the side of the N+ type buffer layer away from the second surface to form a second metal layer as the second electrode.

8. The method for fabricating a vertically double-diffused metal-oxide-semiconductor field-effect transistor according to claim 7, characterized in that, After the step of implanting phosphorus ions into the second surface to form an N+ type buffer layer, the method further includes: A protective layer is formed on the side of the first electrode away from the first surface using a plasma-enhanced chemical vapor deposition process. The orthogonal projection of the protective layer on the substrate completely covers the orthogonal projections of the first electrode and the interlayer dielectric layer on the substrate.

9. A vertically double-diffused metal-oxide-semiconductor field-effect transistor, characterized in that, The vertically double-diffused metal-oxide-semiconductor field-effect transistor is manufactured using the fabrication method of the vertically double-diffused metal-oxide-semiconductor field-effect transistor according to any one of claims 1-8.

10. An electronic device, characterized in that, Including the vertical double-diffused metal-oxide-semiconductor field-effect transistor as described in claim 9.

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