Shielded gate trench type semiconductor device and method of manufacturing the same

Abstract

This invention provides a shielded gate trench semiconductor device and its manufacturing method. The device includes a semiconductor substrate with trenches, a field dielectric layer with a gradually decreasing thickness from bottom to top on the bottom and part of the sidewalls of the trenches; a first dielectric layer on the surface of the field dielectric layer; a shielded gate disposed within the trench surrounded by the first dielectric layer; an intermediate dielectric layer disposed above the shielded gate, and the intermediate dielectric layer having a convex morphology above the shielded gate; and a control gate disposed within the trench above the intermediate dielectric layer. This invention utilizes the difference in material corrosion rates to form a field dielectric layer with a gradually decreasing thickness, and utilizes the local oxidation effect to form a convex intermediate dielectric layer, which can significantly optimize the electric field distribution of the device, improve the withstand voltage capability, and effectively reduce the parasitic capacitance and switching losses between gates.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a shielded gate trench semiconductor device and its manufacturing method. Background Technology

[0002] In the shielded gate trench MOSFET structure, the shielded gate mainly serves to optimize the electric field distribution and reduce parasitic capacitance.

[0003] As semiconductor devices evolve towards higher frequencies, higher voltages, and lower losses, the traditional trench gate (LRSGT) structure is gradually revealing its limitations. To further improve device performance, the industry has proposed a novel shielded gate trench semiconductor device (UDSGT). Compared to traditional trench gates, the novel shielded gate trench semiconductor device can significantly reduce parasitic capacitance by minimizing the overlap area between the control gate and the drain and source shield gates, thereby reducing switching losses and improving switching speed.

[0004] However, in existing manufacturing processes, accurately and efficiently forming a field dielectric layer with an ideal morphology at the bottom of the trench while ensuring good isolation and shaping of the shielding gate and the control gate remains a challenge. Traditional processes are often cumbersome and have limited control over the morphology of the field dielectric layer, making it difficult to meet the stringent requirements for optimized electric field distribution in novel shielded gate trench semiconductor devices.

[0005] Therefore, there is an urgent need for a simple and highly operable method for manufacturing a new type of shielded gate trench semiconductor device. Summary of the Invention

[0006] The technical problem this invention aims to solve is that in existing shielded gate trench semiconductor device manufacturing processes, it is difficult to accurately and efficiently control the gradient morphology of the field dielectric layer, and it is also difficult to form an intermediate isolation layer with a specific protruding structure to optimize the capacitance and insulation performance between gates. Furthermore, a reliable solution for constructing a complete high-performance device structure is lacking. To solve these technical problems, this invention provides a shielded gate trench semiconductor device and a method for manufacturing such a device.

[0007] This invention provides a shielded gate trench semiconductor device, comprising: Semiconductor substrate with trenches; A field dielectric layer with gradually varying thickness is located at the bottom of the trench and on part of the sidewalls, and the thickness of the field dielectric layer on the sidewalls of the trench gradually decreases from bottom to top; The first dielectric layer is located on the surface of the field dielectric layer with gradually varying thickness; A shielding gate is located within the trench surrounded by the first dielectric layer; An intermediate dielectric layer is located above the shielding gate, and the intermediate dielectric layer has a morphology that protrudes above the shielding gate; The control gate is located in the trench above the intermediate dielectric layer.

[0008] Preferably, the system further includes: a drift region located within the semiconductor substrate; a body region located above the drift region; a source region located within the body region and adjacent to the edge of the trench; an interlayer dielectric layer covering the control gate and the surface of the semiconductor substrate; a contact structure passing through the interlayer dielectric layer and electrically connected to the source region and the body region; a source metal layer located above the interlayer dielectric layer and connected to the contact structure; and a drain metal layer located on the back side of the semiconductor substrate.

[0009] The present invention also provides a method for manufacturing a shielded gate trench semiconductor device, comprising: Step 1: Form trenches in a semiconductor substrate and form a field dielectric layer on the inner wall of the trenches; Step 2: Deposit a progressive barrier layer on the surface of the field dielectric layer, the progressive barrier layer filling the trench; Step 3: Etch the progressive barrier layer and the field dielectric layer. Utilize the difference in etching rates between the progressive barrier layer and the field dielectric layer to form a field dielectric layer with gradually varying thickness at the bottom of the trench and on part of the sidewalls. The thickness of the field dielectric layer on the sidewalls of the trench gradually decreases from bottom to top. Step 4: Form a first dielectric layer on the surface of the field dielectric layer with gradually varying thickness; Step 5: Form a shielding gate within the trench; Step 6: Reduce the height of the first dielectric layer to expose part of the sidewall of the shielding gate; Step 7: Partially oxidize the exposed shielding gate to form a second dielectric layer, and retain a portion of the shielding gate that has not been oxidized above the top surface of the shielding gate to form a protrusion. Step 8: Remove the second dielectric layer to expose the protrusion; Step 9: Oxidize the protrusion to form an intermediate dielectric layer, the intermediate dielectric layer having a protruding morphology above the shielding gate; Step 10: Form a control gate in the trench above the intermediate dielectric layer.

[0010] Preferably, in step one, the field dielectric layer material comprises undoped silicate glass.

[0011] Preferably, in step two, the progressive barrier layer material comprises borosilicate glass.

[0012] Preferably, in step two, the corrosion rate difference between the progressive barrier layer and the field dielectric layer is adjusted by controlling the doping concentration of the doping elements in the progressive barrier layer.

[0013] Preferably, the progressive barrier layer is planarized after step two and before step three.

[0014] Preferably, the planarization process includes wet etching, dry etching, or chemical mechanical polishing.

[0015] Preferably, in step three, the etching includes a wet etching process.

[0016] Preferably, in step four, the first dielectric layer is formed using a thermal oxidation process.

[0017] Preferably, in step five, the height of the shielding gate is reduced.

[0018] Preferably, in step five, a back etching process is used to reduce the height of the shielding gate.

[0019] Preferably, in step five, the material of the shielding gate includes doped polycrystalline silicon.

[0020] Preferably, in step six, a wet etching process is used to reduce the height of the first dielectric layer.

[0021] Preferably, in step seven, by controlling the parameters of the thermal oxidation process, the central portion of the shielding gate is retained and the protrusion is formed.

[0022] Preferably, in step eight, a wet etching process is used to remove the second dielectric layer.

[0023] Preferably, in step nine, a thermal oxidation process is used to completely oxidize the protrusion to form the intermediate dielectric layer.

[0024] Preferably, in step ten, forming the control gate includes: forming a gate insulating layer on the trench sidewall, depositing a control gate conductive material in the trench, and planarizing the control gate conductive material.

[0025] As described above, the shielded gate trench semiconductor device and its manufacturing method of the present invention have the following beneficial effects: This invention utilizes the material corrosion rate difference between the progressive barrier layer and the field dielectric layer to precisely form a thickness-gradient field dielectric layer with sidewall thickness gradually decreasing from bottom to top, without increasing process complexity. This structure significantly enhances the lateral electric field strength in the drift region, making the electric field distribution more uniform, thereby greatly improving the device's withstand voltage capability and effectively suppressing bottom spike electric field to prevent breakdown. Simultaneously, this invention precisely constructs an intermediate dielectric layer with a convex morphology by controlling the etch-back height of the first dielectric layer and the local oxidation effect on the shielding gate. This convex structure, thick at the center and thin at the edges, effectively increases the physical isolation distance between the shielding gate and the control gate, enhancing the insulation reliability between gates while significantly reducing the parasitic capacitance between gates, thereby effectively reducing the device's switching losses and improving high-frequency dynamic response characteristics. Attached Figure Description

[0026] Figure 1 The diagram shows a process flow diagram of the manufacturing method of the shielded gate trench semiconductor device of the present invention. Figure 2 The diagram shows the structure of the shielded gate trench semiconductor device of the present invention after the formation of the field dielectric layer; Figure 3 The diagram shows the structure of the shielded gate trench semiconductor device of the present invention after deposition of a progressive barrier layer; Figure 4 The diagram shows the structure of the shielded gate trench semiconductor device of the present invention after forming a field dielectric layer with a gradually varying thickness. Figure 5 The diagram shows the structure of the shielded gate trench semiconductor device of the present invention after the formation of the first dielectric layer; Figure 6 The diagram shows the structure of the shielded gate trench semiconductor device of the present invention after the deposition of the shielded gate conductive material; Figure 7 The diagram shows the structure of the shielded gate trench semiconductor device of the present invention after reducing the height of the shielded gate. Figure 8 The diagram shows the structure of the shielded gate trench semiconductor device of the present invention after reducing the height of the first dielectric layer; Figure 9 The diagram shows the structure of the shielded gate trench semiconductor device of the present invention after the formation of the second dielectric layer and the protrusion. Figure 10 The diagram shows the structure of the shielded gate trench semiconductor device of the present invention after the second dielectric layer has been removed. Figure 11 The diagram shows the structure of the shielded gate trench semiconductor device of the present invention after the formation of the intermediate dielectric layer; Figure 12The diagram shows the structure of the shielded gate trench semiconductor device of the present invention after the control gate is formed; Figure 13 The diagram shown is a schematic representation of the structure of the shielded gate trench semiconductor device of the present invention. Detailed Implementation

[0027] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0028] This embodiment provides a shielded gate trench semiconductor device and a method for manufacturing the shielded gate trench semiconductor device. By optimizing the morphology of the field dielectric layer and the structure of the intermediate dielectric layer, the device improves its breakdown voltage and reduces parasitic capacitance.

[0029] Please see Figure 13 Shielded gate trench semiconductor devices include semiconductor substrates with trenches.

[0030] In some embodiments, the semiconductor substrate may be a silicon substrate, which may include a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer beneath a thin semiconductor layer serving as the active layer. The semiconductor in the active layer and the bulk semiconductor typically comprise the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed-orientation substrates.

[0031] A gradually thickened field dielectric layer 102 is located at the bottom of the trench and on part of the sidewalls, with the thickness of the field dielectric layer 102 on the trench sidewalls gradually decreasing from bottom to top. This gradually thickened wedge structure enables a more uniform lateral electric field distribution within the drift region 101, alleviating the electric field concentration effect at the bottom of the trench, thereby improving the device's breakdown voltage without increasing the trench depth. Simultaneously, the thicker field dielectric layer at the bottom suppresses spike electric fields, preventing device breakdown in the off-state. The gradient slope of this field dielectric layer can be precisely adjusted through subsequent etching processes to match different voltage level requirements.

[0032] The first dielectric layer 104 is located on the surface of the field dielectric layer 102, which has a gradually varying thickness. As a transition layer between the shielding gate and the field dielectric layer, the first dielectric layer optimizes the interface state density and improves the reliability of the gate structure. The first dielectric layer also acts as a barrier to impurity diffusion, preventing dopant elements in the shielding gate from entering the field dielectric layer or the substrate.

[0033] The shielding gate 105 is located within the trench surrounded by the first dielectric layer 104. In some embodiments, the material of the shielding gate 105 may include doped polysilicon, metal silicide, tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, or combinations thereof. Using doped polysilicon as the shielding gate material can utilize its excellent step coverage capability to ensure filling quality within the deep trench. The shielding gate is typically connected to the source potential during device operation, thereby shielding the control gate from the influence of the drain high voltage and reducing the gate-drain overlap capacitance.

[0034] An intermediate dielectric layer 107 is located above the shielding gate 105, and the intermediate dielectric layer 107 has a protruding morphology above the shielding gate 105. This protruding morphology increases the physical distance between the shielding gate and the subsequently formed control gate, reducing the overlap capacitance between them and enhancing the insulation reliability between the gates, preventing dielectric breakdown under high-voltage operating conditions. The center thickness of the protrusion is greater than the edge thickness; this non-uniform thickness distribution further optimizes the electric field distribution at the bottom of the control gate, reducing switching losses.

[0035] The control gate 108 is located in a trench above the intermediate dielectric layer 107. In some embodiments, the material of the control gate 108 may be the same as or different from that of the shield gate 105, for example, a work function-adjustable metal material may be used to precisely control the threshold voltage. The control gate and the shield gate are electrically isolated through the intermediate dielectric layer. This vertical stacking structure saves chip area and is beneficial for achieving higher power density.

[0036] Please continue reading. Figure 13In some embodiments, the shielded gate trench semiconductor device further includes a drift region 101 located within the semiconductor substrate. A body region 110 is located above the drift region 101. A source region 111 is located within the body region 110 and adjacent to the edge of the trench. An interlayer dielectric layer 112 covers the control gate 108 and the surface of the semiconductor substrate. A contact structure passes through the interlayer dielectric layer 112 and is electrically connected to the source region 111 and the body region 110. A source metal layer 113 is located above the interlayer dielectric layer 112 and is connected to the contact structure. A drain metal layer 114 is located on the back side of the semiconductor substrate. The doping concentration and depth of the drift region 101 determine the on-resistance and breakdown voltage of the device and can be formed through multiple epitaxial growths or high-energy ion implantation. The junction depth formed between the body and source regions needs to be precisely controlled to prevent short-channel effects. The interlayer dielectric layer can be made of borosilicate glass, phosphosilicate glass, fluorosilicate glass, silicon oxide formed by plasma-enhanced chemical vapor deposition, or a low-dielectric-constant material to provide a planarized surface and isolate the gate and source metals. The contact structure typically uses a tungsten plug, coupled with a barrier layer made of titanium or titanium nitride. The source and drain metal layers can be made of aluminum, copper, aluminum-copper alloys, titanium, nickel, silver, or gold to ensure good conductivity and ohmic contact. The drain metal layer can be formed on the back side of the thinned substrate using sputtering or evaporation processes.

[0037] Figure 1 This is a schematic diagram of the process flow. Please refer to [link / reference]. Figure 1 The manufacturing method of a shielded gate trench semiconductor device includes the following steps.

[0038] Please see Figure 2 Step 1: Form trenches in a semiconductor substrate and form a field dielectric layer 102 on the inner wall of the trenches.

[0039] In some embodiments, in step one, the field dielectric layer 102 material includes undoped silicate glass. The process of forming the trench may include: first forming a hard mask layer, such as silicon nitride or silicon oxide, on the substrate surface; defining the trench pattern using photolithography; and etching the substrate downwards using reactive ion etching or inductively coupled plasma etching. The field dielectric layer can be formed using atmospheric pressure chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, high-density plasma chemical vapor deposition, low-pressure chemical vapor deposition, or atomic layer deposition. Besides undoped silicate glass, the field dielectric layer may also use thermal silicon oxide, tetraethoxysilane oxide, fluorosilicate glass, or silicon oxynitride. Using undoped silicate glass as the base layer provides good insulation performance and a stable etching rate, and its faster deposition rate helps shorten the production cycle.

[0040] Please see Figure 3Step two: A progressive barrier layer 103 is deposited on the surface of the field dielectric layer 102, and the progressive barrier layer 103 fills the trench. In some embodiments, in step two, the progressive barrier layer 103 is made of borosilicate glass. The progressive barrier layer can also be made of phosphosilicate glass, borosilicate glass, spin-coated glass, spin-coated polymer, or photosensitive polyimide. Borosilicate glass has a low casting temperature and excellent filling performance, enabling it to fill deep trenches without voids. The deposition process can be chemical vapor deposition or spin coating.

[0041] In some embodiments, in step two, the etching rate difference between the progressive barrier layer 103 and the field dielectric layer 102 is adjusted by controlling the doping concentration of the dopants in the progressive barrier layer 103. For example, by adjusting the mass percentages of boron and phosphorus, their etching rates in a specific etching solution can be precisely controlled. Changes in doping concentration alter the chemical bond energy and density of the dielectric layer, thereby enabling fine adjustment of the etching selectivity.

[0042] In some embodiments, the progressive barrier layer 103 is planarized after step two and before step three. In some embodiments, the planarization process includes wet etching, dry etching, or chemical mechanical polishing. The planarization process removes excess progressive barrier layer material outside the trench, ensuring a high degree of material uniformity inside the trench, providing a consistent starting surface for subsequent etching steps, and improving process uniformity.

[0043] Please see Figure 4 Step 3: Etch the progressive barrier layer 103 and the field dielectric layer 102. Utilize the difference in etching rates between the progressive barrier layer 103 and the field dielectric layer 102 to form a field dielectric layer 102 with gradually varying thickness at the bottom of the trench and on part of the sidewalls. The thickness of the field dielectric layer 102 on the sidewalls of the trench gradually decreases from bottom to top.

[0044] In some embodiments, step three, etching, includes a wet etching process. Wet etching can employ a buffered etching solution containing hydrofluoric acid, such as a solution composed of hydrofluoric acid and ammonium fluoride mixed in a specific ratio. Due to the different compositions of the progressive barrier layer and the field dielectric layer, the lateral and longitudinal etching rates of the etching solution at their interface differ. As etching progresses, the progressive barrier layer is gradually consumed, and the exposed field dielectric layer is etched over varying periods, naturally forming a gradient structure with a specific slope. This process is simpler and easier to control than complex multi-mask etching, enabling continuous and smooth thickness transitions and avoiding abrupt changes in the electric field.

[0045] Please see Figure 5Step four: Form a first dielectric layer 104 on the surface of the field dielectric layer 102 with a gradually varying thickness. In some embodiments, step four involves forming the first dielectric layer 104 using a thermal oxidation process. The thermal oxidation process can be performed in an oxygen, water vapor, or nitrous oxide atmosphere. The first dielectric layer formed by thermal oxidation has extremely high density and excellent interface properties, capable of repairing physical damage and chemical contamination caused to the trench sidewalls during etching. The thickness of the first dielectric layer can be adjusted according to the breakdown voltage requirements.

[0046] Please see Figure 6 and Figure 7 Step 5: Form a shielding gate 105 in the trench.

[0047] In some embodiments, in step five, the height of the shielding gate 105 is reduced.

[0048] In some embodiments, in step five, a back etching process is used to reduce the height of the shielding gate 105.

[0049] In some embodiments, in step five, the material of the shielding gate 105 includes doped polysilicon. The formation of the shielding gate typically involves depositing polysilicon via low-pressure chemical vapor deposition (LPCVD), during which in-situ doping can be performed, or impurities such as phosphorus, arsenic, or boron can be introduced after deposition via ion implantation. Subsequently, dry plasma etching is used for etching back, with the etching gas being a mixture of chlorine, hydrogen bromide, and oxygen. By precisely controlling the etching endpoint detection signal or etching time, the top surface of the shielding gate can be positioned at a predetermined depth within the trench, thereby reserving precise space for the subsequent formation of the control gate.

[0050] Please see Figure 8 Step 6: Reduce the height of the first dielectric layer 104 so that part of the sidewall of the shielding gate 105 is exposed.

[0051] In some embodiments, in step six, a wet etching process is used to reduce the height of the first dielectric layer 104. A portion of the first dielectric layer is removed using a selective etching solution, such as a diluted hydrofluoric acid solution. This etching process requires an extremely high selectivity for the shielding gate to ensure that the top sidewalls of the shielding gate are exposed without damaging it. The height of the exposed sidewalls determines the degree of protrusion of the subsequently formed intermediate dielectric layer.

[0052] Please see Figure 9 Step 7: Partially oxidize the exposed shielding gate 105 to form a second dielectric layer 106, and retain a portion of the shielding gate 105 that has not been oxidized on the top surface of the shielding gate 105 to form a protrusion 1051.

[0053] In some embodiments, in step seven, by controlling the parameters of the thermal oxidation process, the central portion of the shielding gate 105 is retained and forms a protrusion 1051. During the thermal oxidation process, oxygen atoms diffuse inward from the top surface and exposed sides of the shielding gate. Due to the presence of lateral oxidation, the edge portion of the shielding gate is transformed into silicon oxide, while the central portion is retained because the diffusion path is longer and it is subjected to stress compression from the surrounding oxide layer, resulting in a gradually slower oxidation rate. This localized oxidation effect is similar to the localized oxidation process in semiconductor manufacturing, ultimately forming a protruding silicon structure.

[0054] Please see Figure 10 Step 8: Remove the second dielectric layer 106 to expose the protrusion 1051.

[0055] In some embodiments, in step eight, a wet etching process is used to remove the second dielectric layer 106. After removing the second dielectric layer, the top of the shielding gate exhibits a stepped morphology with a high center and low edges. This step can remove the poor-quality oxides generated during the oxidation process and provide a clean silicon surface for the final growth of the intermediate dielectric layer.

[0056] Please see Figure 11 Step 9: Oxidize the protrusion 1051 to form an intermediate dielectric layer 107, which has a protruding morphology on the shielding gate 105.

[0057] In some embodiments, in step nine, a thermal oxidation process is used to completely oxidize the protrusion 1051 to form an intermediate dielectric layer 107. Further oxidation completely transforms the protrusion into a dielectric material. Due to the original geometry of the protrusion, the formed intermediate dielectric layer has a larger thickness at its center. This structure increases the average distance between the control gate and the shield gate, thereby reducing the parasitic capacitance between the gates and improving the switching speed of the device.

[0058] Please see Figure 12 Step 10: Form a control gate 108 in a trench above the intermediate dielectric layer 107.

[0059] In some embodiments, step ten, forming the control gate 108, includes: forming a gate insulating layer on the trench sidewalls, depositing a control gate conductive material within the trench, and planarizing the control gate conductive material. The gate insulating layer can be formed by in-situ vapor growth, thermal oxidation, or atomic layer deposition to ensure extremely high thickness uniformity and dielectric strength on the trench sidewalls. After the control gate conductive material is deposited, it is made flush with the substrate surface by a chemical mechanical polishing process, or slightly below the substrate surface by an etch-back process. The planarization process ensures the focusing accuracy of subsequent photolithography processes and improves device integration.

[0060] Please refer to it again. Figure 13 The shielded gate trench semiconductor device also includes a drift region 101 located within the semiconductor substrate. A body region 110 is located above the drift region 101. A source region 111 is located within the body region 110 and adjacent to the edge of the trench. An interlayer dielectric layer 112 covers the control gate 108 and the surface of the semiconductor substrate. A contact structure passes through the interlayer dielectric layer 112 and is electrically connected to the source region 111 and the body region 110. A source metal layer 113 is located above the interlayer dielectric layer 112 and is connected to the contact structure. A drain metal layer 114 is located on the back side of the semiconductor substrate.

[0061] The doping concentration and depth of drift region 101 determine the on-resistance and breakdown voltage of the device. During manufacturing, drift region 101 can be formed by epitaxial growth on a base substrate using chemical vapor deposition (CVD), during which N-type or P-type impurities can be doped in situ. Alternatively, drift region 101 can be formed by multiple high-energy ion implantations into the semiconductor substrate combined with high-temperature annealing, which repairs lattice damage and activates the implanted impurity ions. Body region 110 can be formed by implanting impurity ions with the opposite conductivity type into the top region of drift region 101. The junction depth between body region 110 and source region 111 needs precise control to prevent short-channel effects, which can be achieved through rapid thermal annealing or furnace tube annealing. By precisely controlling the annealing temperature and time, the diffusion depth and concentration distribution of impurities can be controlled. Source region 111 can be formed by high-dose ion implantation into body region 110, with an opposite conductivity type. The high doping concentration helps reduce the contact resistance formed subsequently.

[0062] The interlayer dielectric layer 112 can be made of borosilicate glass, phosphosilicate glass, fluorosilicate glass, silicon oxide formed by plasma-enhanced chemical vapor deposition, or a low-dielectric-constant material to provide a planarized surface and isolate the gate and source metals. The deposition method for the interlayer dielectric layer 112 can include high-density plasma chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, or spin coating. After deposition, the top surface of the interlayer dielectric layer 112 is typically planarized using chemical mechanical polishing or etch-back processes to eliminate surface undulations and provide a flat reference surface for subsequent photolithography and metallization processes.

[0063] The formation of the contact structure involves first etching contact holes in the interlayer dielectric layer 112 using a dry plasma etching process, followed by depositing barrier layers on the sidewalls and bottom of the contact holes. The barrier layers can be made of titanium, titanium nitride, tantalum, tantalum nitride, or combinations thereof, and are formed using physical vapor deposition, chemical vapor deposition, or atomic layer deposition processes. These layers prevent the diffusion of subsequently filled conductive metal into the surrounding dielectric layers and improve adhesion. The contact structure typically uses tungsten plugs, but copper, cobalt, ruthenium, or their alloys can also be used as filler materials. The conductive filler material can be used to fill the contact holes using chemical vapor deposition or electroplating processes, followed by chemical mechanical polishing to remove excess metal material from the surface of the interlayer dielectric layer 112. The source and drain metal layers can be made of aluminum, copper, aluminum-copper alloys, titanium, nickel, silver, or gold to ensure good conductivity and ohmic contact.

[0064] The source metal layer 113 can be formed by sputtering one or more metal thin films using physical vapor deposition (PVD) and then patterning them using photolithography and etching. Before forming the drain metal layer 114, the back side of the semiconductor substrate is typically thinned, for example by mechanical polishing combined with chemical mechanical polishing or wet etching, to reduce the substrate's bulk resistance and improve heat dissipation. The drain metal layer 114 can be formed on the thinned back side of the substrate by sputtering or evaporation. Its structure can be a multilayer metal stack composed of titanium, nickel, silver, or gold. This multilayer structure can simultaneously meet the requirements of forming good ohmic contact with the semiconductor substrate and adapting to subsequent packaging and soldering processes.

[0065] The method provided in this embodiment cleverly utilizes the difference in material etching rates and the local oxidation effect to achieve precise control of the morphology of the field dielectric layer and the intermediate dielectric layer without increasing the complexity of the process. This optimizes the electric field distribution and dynamic characteristics of the device, providing reliable technical support for high-performance power solutions.

[0066] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0067] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A shielded gate trench semiconductor device, characterized in that, include: Semiconductor substrate with trenches; A field dielectric layer with gradually varying thickness is located at the bottom of the trench and on part of the sidewalls, and the thickness of the field dielectric layer on the sidewalls of the trench gradually decreases from bottom to top; The first dielectric layer is located on the surface of the field dielectric layer with gradually varying thickness; A shielding gate is located within the trench surrounded by the first dielectric layer; An intermediate dielectric layer is located above the shielding gate, and the intermediate dielectric layer has a morphology that protrudes above the shielding gate; The control gate is located in the trench above the intermediate dielectric layer.

2. The shielded gate trench semiconductor device according to claim 1, characterized in that: Also includes: The drift region is located within the semiconductor substrate; The body region is located above the drift region; The source region is located within the body region and adjacent to the edge of the trench; An interlayer dielectric layer covers the surface of the control gate and the semiconductor substrate; The contact structure passes through the interlayer dielectric layer and is electrically connected to the source region and the body region; A source metal layer is located above the interlayer dielectric layer and connected to the contact structure; A drain metal layer is located on the back side of the semiconductor substrate.

3. A method for manufacturing a shielded gate trench semiconductor device, characterized in that, include: Step 1: Form trenches in a semiconductor substrate and form a field dielectric layer on the inner wall of the trenches; Step 2: Deposit a progressive barrier layer on the surface of the field dielectric layer, the progressive barrier layer filling the trench; Step 3: Etch the progressive barrier layer and the field dielectric layer. Utilize the difference in etching rates between the progressive barrier layer and the field dielectric layer to form a field dielectric layer with gradually varying thickness at the bottom of the trench and on part of the sidewalls. The thickness of the field dielectric layer on the sidewalls of the trench gradually decreases from bottom to top. Step 4: Form a first dielectric layer on the surface of the field dielectric layer with gradually varying thickness; Step 5: Form a shielding gate within the trench; Step 6: Reduce the height of the first dielectric layer to expose part of the sidewall of the shielding gate; Step 7: Partially oxidize the exposed shielding gate to form a second dielectric layer, and retain a portion of the shielding gate that has not been oxidized above the top surface of the shielding gate to form a protrusion. Step 8: Remove the second dielectric layer to expose the protrusion; Step 9: Oxidize the protrusion to form an intermediate dielectric layer, the intermediate dielectric layer having a protruding morphology above the shielding gate; Step 10: Form a control gate in the trench above the intermediate dielectric layer.

4. The method for manufacturing a shielded gate trench semiconductor device according to claim 3, characterized in that: In step one, the field dielectric layer material includes undoped silicate glass.

5. The method for manufacturing a shielded gate trench semiconductor device according to claim 4, characterized in that: In step two, the progressive barrier layer material includes borosilicate glass.

6. The method for manufacturing a shielded gate trench semiconductor device according to claim 5, characterized in that: In step two, the corrosion rate difference between the progressive barrier layer and the field dielectric layer is adjusted by controlling the doping concentration of the doped elements in the progressive barrier layer.

7. The method for manufacturing a shielded gate trench semiconductor device according to claim 3, characterized in that: After step two and before step three, the progressive barrier layer is planarized.

8. The method for manufacturing a shielded gate trench semiconductor device according to claim 7, characterized in that: The planarization process includes wet etching, dry etching, or chemical mechanical polishing.

9. The method for manufacturing a shielded gate trench semiconductor device according to claim 3, characterized in that: In step three, the etching includes a wet etching process.

10. The method for manufacturing a shielded gate trench semiconductor device according to claim 3, characterized in that: In step four, the first dielectric layer is formed using a thermal oxidation process.

11. The method for manufacturing a shielded gate trench semiconductor device according to claim 3, characterized in that: In step five, the height of the shielding gate is reduced.

12. The method for manufacturing a shielded gate trench semiconductor device according to claim 11, characterized in that: In step five, a back etching process is used to reduce the height of the shielding gate.

13. The method for manufacturing a shielded gate trench semiconductor device according to claim 3, characterized in that: In step five, the material of the shielding gate includes doped polycrystalline silicon.

14. The method for manufacturing a shielded gate trench semiconductor device according to claim 3, characterized in that: In step six, a wet etching process is used to reduce the height of the first dielectric layer.

15. The method for manufacturing a shielded gate trench semiconductor device according to claim 3, characterized in that: In step seven, by controlling the parameters of the thermal oxidation process, the central portion of the shielding gate is retained and the protrusion is formed.

16. The method for manufacturing a shielded gate trench semiconductor device according to claim 3, characterized in that: In step eight, a wet etching process is used to remove the second dielectric layer.

17. The method for manufacturing a shielded gate trench semiconductor device according to claim 3, characterized in that: In step nine, the protrusion is completely oxidized using a thermal oxidation process to form the intermediate dielectric layer.

18. The method for manufacturing a shielded gate trench semiconductor device according to claim 3, characterized in that: In step ten, forming the control gate includes: forming a gate insulating layer on the trench sidewall, depositing a control gate conductive material in the trench, and planarizing the control gate conductive material.

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