Silicon carbide power device and preparation method thereof, silicon carbide mosfet, silicon carbide igbt

Abstract

This application provides a silicon carbide power device and its fabrication method, a silicon carbide MOSFET, and a silicon carbide IGBT, relating to the field of semiconductor technology. The aim is to significantly improve the short-circuit withstand capability of the silicon carbide power device without sacrificing the gate voltage withstand capability and the main electrical characteristics of the silicon carbide power device. The silicon carbide power device includes a silicon carbide layer, and a gate dielectric layer, a polysilicon layer, and an electrode layer sequentially disposed on the silicon carbide layer. Multiple gate lines of the polysilicon layer have a first doping type, and each gate line is connected to multiple polysilicon bridges. Along a first direction, the polysilicon bridge includes a first lightly doped region, a first heavily doped region, a second lightly doped region, and a first doping type region sequentially connected. The first lightly doped region and the second lightly doped region are either undoped or have a low concentration of the first or second doping type, and the first heavily doped region has a second doping type. The first lightly doped region is in electrical contact with the gate line, and the first doping type region is electrically connected to the electrode layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a silicon carbide power device and its fabrication method, a silicon carbide MOSFET, and a silicon carbide IGBT. Background Technology

[0002] Currently, silicon carbide power devices have broad application prospects in high voltage, high frequency, and high temperature fields due to their advantages such as high breakdown voltage, low on-resistance, high operating frequency, and good thermal conductivity.

[0003] However, silicon carbide MOSFETs have a shorter short-circuit withstand time, significantly lower than silicon IGBTs of the same voltage level. This places higher demands on protection circuits and limits their application in fields with high reliability requirements.

[0004] Traditional techniques often improve short-circuit performance by adjusting the structural parameters and doping distribution in the silicon carbide epitaxial layer, but this inevitably affects other electrical properties of the device. For example, reducing the JFET area or channel density can improve short-circuit withstand performance, but it will significantly increase on-resistance and losses.

[0005] How to significantly improve the short-circuit withstand performance of existing silicon carbide power devices without sacrificing their main electrical characteristics, and how to mass-produce them using conventional processes, has become a problem that must be faced and urgently needs to be solved. Summary of the Invention

[0006] This application proposes a silicon carbide power device and its fabrication method, a silicon carbide MOSFET, and a silicon carbide IGBT, aiming to significantly improve the short-circuit withstand capability of the silicon carbide power device without sacrificing the gate withstand voltage capability and the main electrical characteristics of the silicon carbide power device.

[0007] To achieve the above objectives, embodiments of this application provide the following technical solutions: On one hand, embodiments of this application provide a silicon carbide power device, which includes a silicon carbide layer, a gate dielectric layer, a polysilicon layer, and an electrode layer. The silicon carbide layer includes a substrate and an epitaxial layer disposed on the substrate. The gate dielectric layer is disposed on the epitaxial layer. The polysilicon layer is disposed on the gate dielectric layer or on both the gate dielectric layer and the silicon carbide layer. The electrode layer is disposed on the side of the polysilicon layer away from the silicon carbide layer. The polysilicon layer includes multiple gate lines and multiple polysilicon bridges. The multiple gate lines have a first doping type and are arranged along a first direction parallel to the silicon carbide layer. Each gate line extends along a second direction parallel to the silicon carbide layer and is connected to multiple polysilicon bridges. The first and second directions intersect. Along the first direction, each polysilicon bridge includes a first lightly doped region, a first heavily doped region, a second lightly doped region, and a first doping type region connected sequentially. The first lightly doped region and the second lightly doped region have no intentional doping or have a low concentration of the first or second doping type. The first heavily doped region has a second doping type. The first lightly doped region is electrically connected to the gate line, and the first doped type region is electrically connected to the electrode layer.

[0008] The silicon carbide power device provided in the embodiments of this application includes a silicon carbide layer, a gate dielectric layer, a polysilicon layer, and an electrode layer. The polysilicon layer includes multiple gate lines and multiple polysilicon bridges. The multiple gate lines have a first doping type. The polysilicon bridges include a first lightly doped region, a first heavily doped region, a second lightly doped region, and a first doping type region connected in sequence. The first lightly doped region and the second lightly doped region have no intentional doping or have a low concentration of the first or second doping type. The first heavily doped region has a second doping type. The first lightly doped region is electrically contacted with the gate lines, and the first doping type region is electrically connected to the electrode layer.

[0009] It is understandable that the gate line and the electrode layer are electrically connected sequentially through a first lightly doped region, a first heavily doped region, a second lightly doped region, and a first doping type region. The gate line, the first lightly doped region, and the first heavily doped region are equivalent to a polysilicon diode, and the first heavily doped region, the second lightly doped region, and the first doping type region are equivalent to another polysilicon diode. The above arrangement is equivalent to embedding two reverse-connected polysilicon diodes between the gate line and electrode layers of the silicon carbide power device, thus introducing a thermal-electric negative feedback loop for the silicon carbide power device.

[0010] In polysilicon diodes, the reverse-biased leakage current is exponentially positively correlated with temperature, and the gate line includes multiple gates. When a silicon carbide power device is short-circuited, the temperature rises rapidly. The leakage current of the two polysilicon diodes embedded between the gate line and the electrode layer increases exponentially with the temperature, thereby causing a rapid increase in the current in the gate drive circuit. The increased voltage drop across the external gate resistor will share the drive voltage, thus rapidly and significantly reducing the effective voltage applied to the gate. This reduces the inversion degree of the silicon carbide power device channel or even completely turns off the channel, thereby effectively limiting the short-circuit current of the silicon carbide power device. Ultimately, it achieves self-regulation of the short-circuit current and clamps the junction temperature to prevent it from rising further, theoretically achieving an infinite short-circuit withstand time.

[0011] Furthermore, compared to traditional silicon carbide devices, the silicon carbide power device of this application only adds a polysilicon bridge and modifies the electrode layer contact settings, retaining the polysilicon gate line and silicon carbide layer structure. Therefore, it does not sacrifice key electrical performance characteristics such as on-resistance, withstand voltage, threshold voltage, output capacitance, and reverse transfer capacitance at normal operating temperatures. In addition, because the embedded polysilicon diode introduces additional capacitance, the input capacitance of the silicon carbide power device increases, which improves the ratio of input capacitance to reverse transfer capacitance, thus helping to prevent the silicon carbide power device from turning on erroneously.

[0012] In some embodiments, a plurality of polysilicon bridges are disposed between two adjacent gate lines, and the plurality of polysilicon bridges are arranged along a second direction. Along a first direction, each polysilicon bridge includes a first lightly doped region, a first heavily doped region, a second lightly doped region, a first doping type region, a third lightly doped region, a second heavily doped region, and a fourth lightly doped region connected in sequence. The third and fourth lightly doped regions are undoped or have a low concentration of the first or second doping type, while the second heavily doped region has the second doping type. One of two adjacent gate lines is electrically contacted with the first lightly doped region, and the other is electrically contacted with the fourth lightly doped region.

[0013] In some embodiments, multiple gate lines are interconnected with multiple polysilicon bridges to form a mesh structure.

[0014] In some embodiments, the silicon carbide power device further includes an interlayer dielectric layer. An electrode layer penetrates the interlayer dielectric layer and is electrically connected to a first doped region. Alternatively, the silicon carbide layer includes a substrate and an epitaxial layer disposed on the substrate. The silicon carbide power device further includes a gate dielectric layer covering the epitaxial layer. The first doped region penetrates the gate dielectric layer and is electrically contacted with the epitaxial layer. The electrode layer penetrates the interlayer dielectric layer and is electrically connected to the epitaxial layer. The first doped region is electrically connected to the electrode layer through the epitaxial layer.

[0015] In some embodiments, a plurality of polysilicon bridges are disposed between two adjacent gate lines, and the plurality of polysilicon bridges are arranged along a second direction. Along a first direction, each polysilicon bridge includes a first lightly doped region, a first heavily doped region, a second lightly doped region, a first doping type region, a third lightly doped region, a second heavily doped region, and a fourth lightly doped region connected in sequence. The third and fourth lightly doped regions are undoped or have a low concentration of the first or second doping type, while the second heavily doped region has the second doping type. One of two adjacent gate lines is electrically contacted with the first lightly doped region, and the other is electrically contacted with the fourth lightly doped region.

[0016] The concentrations of both the first and second lightly doped regions are less than or equal to 10. 17 cm -3 Alternatively, the concentrations of the first, second, third, and fourth lightly doped regions are all less than or equal to 10. 17 cm -3 The concentration of the first doped region is greater than or equal to 10. 18 cm -3 Alternatively, the concentrations of the first and second doped regions are greater than or equal to 10. 18 cm -3 .

[0017] On the other hand, embodiments of this application also provide a method for fabricating a silicon carbide power device, which is used to fabricate the silicon carbide power device in any of the above embodiments. The fabrication method includes: A gate dielectric layer is formed on the epitaxial layer of the silicon carbide layer, and a polysilicon layer is formed on the gate dielectric layer. The silicon carbide layer includes a substrate and an epitaxial layer disposed on the substrate. Multiple photolithography and ion implantation processes are performed on the polysilicon layer to form multiple gate lines and multiple polysilicon bridges. The gate lines have a first doping type and are arranged along a first direction parallel to the silicon carbide layer. Each gate line extends along a second direction parallel to the silicon carbide layer and is connected to multiple polysilicon bridges. The first and second directions intersect. Along the first direction, each polysilicon bridge includes a first lightly doped region, a first heavily doped region, a second lightly doped region, and a first doping type region connected in sequence; or, each polysilicon bridge includes a first lightly doped region, a first heavily doped region, a second lightly doped region, a first doping type region, a third lightly doped region, a second heavily doped region, and a fourth lightly doped region connected in sequence. The first lightly doped region, or the first lightly doped region and the fourth lightly doped region, are in electrical contact with the gate lines. The first lightly doped region, the second lightly doped region, the third lightly doped region, and the fourth lightly doped region are all unintentionally doped or all have a low concentration of the first or second doping type. The first heavily doped region and the second lightly doped region both have the second doping type. Photolithography and etching of the polysilicon layer preserves multiple gate lines and multiple polysilicon bridges; An interlayer dielectric layer is formed on the side of the polysilicon layer away from the gate dielectric layer. The interlayer dielectric layer and the interlayer dielectric layer and the gate dielectric layer are photolithographically etched simultaneously to form a through first contact hole and a second contact hole, respectively. The first contact hole exposes the first doped type region and the second contact hole exposes the epitaxial layer. An electrode layer is formed on the side of the interlayer dielectric layer away from the gate dielectric layer. The electrode layer is electrically connected to the first doped type region through a first contact hole and to the epitaxial layer through a second contact hole.

[0018] The method for fabricating a silicon carbide power device provided in the embodiments of this application involves forming a polysilicon layer including multiple gate lines and multiple polysilicon bridges on a silicon carbide layer, then forming an interlayer dielectric layer with a first contact hole on the polysilicon layer, and forming an electrode layer on the side of the interlayer dielectric layer away from the silicon carbide layer to form a silicon carbide power device. The electrode layer directly contacts a first doped region through the first contact hole in the interlayer dielectric layer, forming an electrical connection. Furthermore, the electrode layer is connected to the epitaxial layer through a second contact hole.

[0019] It is understandable that the gate line and the electrode layer are electrically connected sequentially through a first lightly doped region, a first heavily doped region, a second lightly doped region, and a first doping type region. The gate line, the first lightly doped region, and the first heavily doped region are equivalent to a polysilicon diode, and the first heavily doped region, the second lightly doped region, and the first doping type region are equivalent to another polysilicon diode. The above arrangement is equivalent to embedding two reverse-connected polysilicon diodes between the gate line and the electrode layer of the silicon carbide power device, thus introducing a thermal-electric negative feedback loop for the silicon carbide power device.

[0020] In polysilicon diodes, the reverse-biased leakage current is exponentially positively correlated with temperature, and the gate line includes multiple gates. When a silicon carbide power device is short-circuited, the temperature rises rapidly. The leakage current of the two polysilicon diodes embedded between the gate line and the electrode layer increases exponentially with the temperature, thereby causing a rapid increase in the current in the gate drive circuit. The increased voltage drop across the external gate resistor will share the drive voltage, thus rapidly and significantly reducing the effective voltage applied to the gate. This reduces the inversion degree of the silicon carbide power device channel or even completely turns off the channel, thereby effectively limiting the short-circuit current of the silicon carbide power device. Ultimately, it achieves self-regulation of the short-circuit current and clamps the junction temperature to prevent it from rising further, theoretically achieving an infinite short-circuit withstand time.

[0021] Furthermore, compared to traditional silicon carbide devices, the silicon carbide power device of this application only adds a polysilicon bridge and modifies the electrode layer contact settings, retaining the polysilicon gate line and silicon carbide layer structure. Therefore, it does not sacrifice key electrical performance characteristics such as on-resistance, withstand voltage, threshold voltage, output capacitance, and reverse transfer capacitance at normal operating temperatures. In addition, because the embedded polysilicon diode introduces additional capacitance, the input capacitance of the silicon carbide power device increases, which improves the ratio of input capacitance to reverse transfer capacitance, thus helping to prevent the silicon carbide power device from turning on erroneously.

[0022] On the other hand, embodiments of this application also provide another method for fabricating a silicon carbide power device, which is used to fabricate the silicon carbide power device in any of the above embodiments. This fabrication method includes: A gate dielectric layer is formed on the epitaxial layer of the silicon carbide layer. The gate dielectric layer is photolithographically etched and etched to form a through third contact hole. The silicon carbide layer includes a substrate and an epitaxial layer disposed on the substrate. The third contact hole exposes the epitaxial layer. A polysilicon layer is formed on the gate dielectric layer; Multiple photolithography and ion implantation processes are performed on the polysilicon layer to form multiple gate lines and multiple polysilicon bridges. The multiple gate lines have a first doping type and are arranged along a first direction parallel to the silicon carbide layer. Each gate line extends along a second direction parallel to the silicon carbide layer and is connected to multiple polysilicon bridges. The first and second directions intersect. Along the first direction, each polysilicon bridge includes a first lightly doped region, a first heavily doped region, a second lightly doped region, and a region of the first doping type, connected sequentially. Alternatively, each polysilicon bridge includes a region of the first doping type connected sequentially. The region comprises a first lightly doped region, a first heavily doped region, a second lightly doped region, a first doped type region, a third lightly doped region, a second heavily doped region, and a fourth lightly doped region. The first lightly doped region, or the first lightly doped region and the fourth lightly doped region, are electrically in contact with the gate line. The first doped type region is electrically in contact with the epitaxial layer through a third contact hole. The first lightly doped region, the second lightly doped region, the third lightly doped region, and the fourth lightly doped region are all without intentional doping or have a low concentration of the first doped type or the second doped type. The first heavily doped region and the second heavily doped region both have the second doped type. Photolithography and etching of the polysilicon layer preserves multiple gate lines and multiple polysilicon bridges; An interlayer dielectric layer is formed on the side of the epitaxial layer away from the substrate, and the interlayer dielectric layer and the gate dielectric layer are etched to form a through second contact hole, which exposes the epitaxial layer. An electrode layer is formed on the side of the interlayer dielectric layer away from the silicon carbide layer, and the electrode layer is electrically connected to the epitaxial layer through a second contact hole.

[0023] The method for fabricating a silicon carbide power device provided in the embodiments of this application involves forming a polysilicon layer including multiple gate lines and multiple polysilicon bridges on a silicon carbide layer, then forming an interlayer dielectric layer with a second contact hole on the polysilicon layer, and forming an electrode layer on the side of the interlayer dielectric layer away from the silicon carbide layer to form a silicon carbide power device. The electrode layer is electrically contacted with the epitaxial layer through the second contact hole in the interlayer dielectric layer, and a first doped region is electrically contacted with the epitaxial layer through a third contact hole, thereby forming an electrical connection between the electrode layer and the first doped region.

[0024] It is understandable that the gate line and the electrode layer are electrically connected sequentially through a first lightly doped region, a first heavily doped region, a second lightly doped region, a first doped type region, and an epitaxial layer. The gate line, the first lightly doped region, and the first heavily doped region are equivalent to a polysilicon diode, and the first heavily doped region, the second lightly doped region, and the first doped type region are equivalent to another polysilicon diode. The above arrangement is equivalent to embedding two reverse-connected polysilicon diodes between the gate line and the electrode layer of the silicon carbide power device, thus introducing a thermal-electric negative feedback loop for the silicon carbide power device.

[0025] In polysilicon diodes, the reverse-biased leakage current is exponentially positively correlated with temperature, and the gate line includes multiple gates. When a silicon carbide power device is short-circuited, the temperature rises rapidly. The leakage current of the two polysilicon diodes embedded between the gate line and the electrode layer increases exponentially with the temperature, thereby causing a rapid increase in the current in the gate drive circuit. The increased voltage drop across the external gate resistor will share the drive voltage, thus rapidly and significantly reducing the effective voltage applied to the gate. This reduces the inversion degree of the silicon carbide power device channel or even completely turns off the channel, thereby effectively limiting the short-circuit current of the silicon carbide power device. Ultimately, it achieves self-regulation of the short-circuit current and clamps the junction temperature to prevent it from rising further, theoretically achieving an infinite short-circuit withstand time.

[0026] Furthermore, compared to traditional silicon carbide devices, the silicon carbide power device of this application only adds a polysilicon bridge and modifies the electrode layer contact settings, retaining the polysilicon gate line and silicon carbide layer structure. Therefore, it does not sacrifice key electrical performance characteristics such as on-resistance, withstand voltage, threshold voltage, output capacitance, and reverse transfer capacitance at normal operating temperatures. In addition, because the embedded polysilicon diode introduces additional capacitance, the input capacitance of the silicon carbide power device increases, which improves the ratio of input capacitance to reverse transfer capacitance, thus helping to prevent the silicon carbide power device from turning on erroneously.

[0027] On the other hand, embodiments of this application also provide another method for fabricating a silicon carbide power device, which is used to fabricate the silicon carbide power device in any of the above embodiments. This fabrication method includes: A gate dielectric layer is formed on the epitaxial layer of the silicon carbide layer, and a polysilicon layer with a heavily doped first doping type is formed on the gate dielectric layer. The silicon carbide layer includes a substrate and an epitaxial layer disposed on the substrate. Photolithography and etching of a polysilicon layer preserves multiple gate lines and multiple first doped regions. The multiple gate lines are arranged along a first direction parallel to the silicon carbide layer, and each gate line extends along a second direction parallel to the silicon carbide layer. The first direction and the second direction intersect. A polycrystalline silicon layer with no intentional doping or low doping concentration is deposited. The polycrystalline silicon layer is then photolithographically ... Photolithography and etching of the polysilicon layer preserves multiple gate lines and multiple polysilicon bridges; An interlayer dielectric layer is formed on the side of the polysilicon layer away from the gate dielectric layer. The interlayer dielectric layer and the interlayer dielectric layer and the gate dielectric layer are photolithographically etched simultaneously to form a through first contact hole and a second contact hole, respectively. The first contact hole exposes the first doped type region and the second contact hole exposes the epitaxial layer. An electrode layer is formed on the side of the interlayer dielectric layer away from the gate dielectric layer. The electrode layer is electrically connected to the first doped type region through a first contact hole and to the silicon carbide epitaxial layer through a second contact hole.

[0028] On the other hand, embodiments of this application also provide a silicon carbide MOSFET, which includes the silicon carbide power device and drain of any of the above embodiments, the gate line includes the gate electrode, and the electrode layer includes the source electrode.

[0029] On the other hand, embodiments of this application also provide a silicon carbide IGBT, which includes the silicon carbide power device and collector of any of the above embodiments, the gate line includes a gate electrode, and the electrode layer includes an emitter electrode.

[0030] The silicon carbide MOSFETs and silicon carbide IGBTs described above have the same structure and beneficial technical effects as the silicon carbide power devices provided in some of the above embodiments, and will not be repeated here. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not actual dimensions of the products or actual processes of the methods involved in the embodiments of this application.

[0032] Figure 1 A schematic diagram of the structure of a silicon carbide power device provided for an embodiment of this application; Figure 2 A schematic diagram of another silicon carbide power device provided for an embodiment of this application; Figure 3 for Figure 2 A partial cross-sectional view of a portion of the film layer of a silicon carbide power device along section line AA'; Figure 4 A partial cross-sectional view of a portion of the film layer of another silicon carbide power device provided for an embodiment of this application along section line AA'; Figure 5 A partial cross-sectional view of a portion of the film layer of another silicon carbide power device provided for an embodiment of this application along section line AA'; Figure 6 A flowchart illustrating a method for fabricating a silicon carbide power device provided in an embodiment of this application; Figures 7-9 for Figure 6 The preparation method shown in the diagrams illustrates each step. Figure 10 A flowchart illustrating another method for fabricating a silicon carbide power device provided as an embodiment of this application; Figures 11-13 for Figure 10 The preparation method shown in the diagrams illustrates each step. Figure 14 A flowchart illustrating another method for fabricating a silicon carbide power device provided as an embodiment of this application; Figures 15-21 for Figure 14 The preparation method is illustrated in the following diagrams. Detailed Implementation

[0033] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0034] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and encompassing, that is, "including, but not limited to".

[0035] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0036] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. For example, in describing some embodiments, the term "connection" may be used to indicate that two or more components have direct physical or electrical contact with each other.

[0037] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0038] Silicon-oxide-semiconductor field-effect transistors (SiC MOSFETs) hold promise as a replacement for silicon-insulated-gate bipolar transistors (Si IGBTs) in building more efficient systems due to their advantages such as high breakdown voltage, low on-resistance, fast switching speed, and good high-temperature tolerance. However, SiC MOSFETs have poor short-circuit withstand capability, with a typical short-circuit withstand time of 3 µs, compared to 10 µs for Si IGBTs. Consequently, SiC MOSFETs require more complex and faster protection circuits and are less suitable for applications with high reliability requirements, limiting their full potential.

[0039] Traditional techniques typically improve short-circuit performance by adjusting the structural parameters and doping distribution in the silicon carbide epitaxial layer. However, this inevitably affects other electrical properties of the device. For example, reducing the area or channel density of a JFET can improve short-circuit withstand performance, but it will significantly increase on-resistance and losses, creating a trade-off between conduction performance and short-circuit withstand capability.

[0040] Therefore, embodiments of this application provide a silicon carbide power device and its fabrication method, a silicon carbide MOSFET, and a silicon carbide IGBT, aiming to comprehensively and significantly improve the short-circuit withstand capability of silicon carbide power devices without sacrificing the gate withstand voltage capability and the electrical characteristics of silicon carbide power devices under normal operating temperature.

[0041] On the one hand, embodiments of this application provide a silicon carbide power device. Figure 1 This is a schematic diagram of the structure of a silicon carbide power device provided for an embodiment of this application.

[0042] See Figure 1 , Figure 1 The diagram shows a top view of a silicon carbide power device. The device includes a silicon carbide layer 1, a gate dielectric layer 4, a polysilicon layer, and an electrode layer 6. The silicon carbide layer 1 includes a substrate 15 and an epitaxial layer 14 disposed on the substrate 15. The gate dielectric layer 4 is disposed above the epitaxial layer 14. The polysilicon layer is disposed above the gate dielectric layer 4 or above both the gate dielectric layer 4 and the silicon carbide layer 1. The electrode layer 6 is disposed on the side of the polysilicon layer away from the silicon carbide layer 1.

[0043] For example, electrode layer 6 can be the source, in which case the silicon carbide power device is a silicon carbide MOSFET. Alternatively, electrode layer 6 can also be the emitter, in which case the silicon carbide power device is a silicon carbide IGBT.

[0044] See also Figure 1 The polysilicon layer includes multiple gate lines 21 and multiple polysilicon bridges 22. The multiple gate lines 21 have a first doping type. The multiple gate lines 21 are arranged along a first direction X parallel to the silicon carbide layer 1. Each gate line 21 extends along a second direction Y parallel to the silicon carbide layer 1, and each gate line 21 is connected to multiple polysilicon bridges 22. The first direction X and the second direction Y intersect.

[0045] For example, the embodiments of this application are illustrated with the first direction X being perpendicular to the second direction Y. Along the first direction X, on each gate line 21, a plurality of polysilicon bridges 22 may be located on the same side of the gate line 21, or the plurality of polysilicon bridges 22 may be located on opposite sides of the gate line 21. The embodiments of this application are illustrated with the example of a plurality of polysilicon bridges 22 being located on the same side of the gate line 21.

[0046] Along the first direction X, the polysilicon bridge 22 includes a first lightly doped region 221, a first heavily doped region 222, a second lightly doped region 223, and a first doping type region 224 connected in sequence. The first lightly doped region 221 and the second lightly doped region 223 have no intentional doping or have a low concentration of the first or second doping type. The first heavily doped region 222 has the second doping type. The first heavily doped region 224 has the second doping type.

[0047] For example, the first lightly doped region 221 and the second lightly doped region 223 can both be of the first doping type with no intentional doping and a low concentration, or of the second doping type with a low concentration. For example, the embodiments of this application illustrate the example where both the first lightly doped region 221 and the second lightly doped region 223 are of the second doping type with a low concentration.

[0048] It is understood that the polysilicon layer 2 includes a plurality of strip polysilicon gate lines 21 arranged with a set width and a set spacing and having a first doping type, and a plurality of polysilicon bridges 22 connected at one end perpendicularly to the polysilicon gate lines 21 and arranged with a set width and a set spacing, having in a first direction X away from the polysilicon gate lines 21 a plurality of polysilicon bridges consisting of a second doping type region (a first lightly doped region 221, a first heavily doped region 222, and a second lightly doped region 223) and a first doping type region 224 in sequence.

[0049] For example, if the first doping type is N-type, the second doping type can be P-type. Then, the conductivity type of the multiple gate lines 21 and the first doping type region 224 is N-type. The conductivity type of the first lightly doped region 221, the first heavily doped region 222, and the second lightly doped region 223 is P-type.

[0050] For example, on the polysilicon bridge 22, the doped regions are distributed in parallel strips, with varying concentrations in the first direction X and approximately uniform concentrations in the second direction Y. The ion doping concentrations in the first lightly doped region 221, the first heavily doped region 222, and the second lightly doped region 223 can be the same or different.

[0051] See also Figure 1 The first lightly doped region 221 is electrically connected to the gate line 21, and the first doped type region 224 is electrically connected to the electrode layer 6.

[0052] For example, the silicon carbide power device further includes an interlayer dielectric layer 5, which is located between the electrode layer 6 and the polysilicon layer. The interlayer dielectric layer 5 has a first contact hole 32 and a second contact hole 31. The electrode layer 6 can be electrically connected to the first doped region 224 through the first contact hole 32. The electrode layer 6 can contact the source region or emitter region of the silicon carbide power device through the second contact hole 31.

[0053] In conventional structures, the second contact hole 31 is located between the polysilicon gate lines 21 and is continuous in the second direction Y. However, in embodiments of this application, for example... Figure 1 In the structure shown, the polysilicon bridge 22 blocks the second contact hole 31, so the second contact hole 31 is arranged periodically in the second direction Y according to a set spacing.

[0054] It is understandable that the end of the polysilicon bridge 22 containing the first doped region 224 is electrically connected to the electrode layer 6. The gate line 21 passes through the first lightly doped region 221, the first heavily doped region 222, the second lightly doped region 223 and the first doped region 224 in sequence and is electrically connected to the electrode layer 6. This is equivalent to embedding two polysilicon diodes in reverse series between the gate line 21 and the electrode layer 6.

[0055] Among them, the gate line 21, the first lightly doped region 221 and the first heavily doped region 222 are equivalent to a polysilicon diode, and the first heavily doped region 222, the second lightly doped region 223 and the first doped type region 224 are equivalent to another polysilicon diode.

[0056] For example, the ion doping concentrations in gate line 21, the first heavily doped region 222, and the first doped type region 224 are relatively high, while the ion doping concentrations in the first lightly doped region 221 and the second lightly doped region 223 are relatively low. Therefore, both polysilicon diodes can be PIN (Positive-Intrinsic-Negative Diode) diodes. The first lightly doped region 221 and the second lightly doped region 223 correspond to the intrinsic semiconductor layer of the PIN diode.

[0057] For example, the first lightly doped region 221 and the second lightly doped region 223 are responsible for bearing voltage when a positive and negative voltage is applied to the silicon carbide power device, respectively, with the specific allocation depending on the doping type. In the case of the second doping type being P-type, the first lightly doped region 221, which is closer to the polysilicon gate line 21, bears the positive gate voltage. The first heavily doped region 222 is responsible for cutting off the electric field, preventing punch-through, and optimizing the gate withstand voltage and leakage current at normal operating temperature.

[0058] For example, the gate withstand voltage can be adjusted by regulating the length and concentration of the first lightly doped region 221 and the second lightly doped region 223. Generally, the gate positive voltage withstand requirement of silicon carbide power devices is higher than the negative voltage withstand requirement, so the length of the doped region responsible for bearing the positive voltage withstand is longer.

[0059] The silicon carbide power device provided in the embodiments of this application includes a silicon carbide layer 1, a gate dielectric layer 4, a polysilicon layer, and an electrode layer 6. The polysilicon layer includes multiple gate lines 21 and multiple polysilicon bridges 22. The multiple gate lines 21 have a first doping type. The polysilicon bridges 22 include a first lightly doped region 221, a first heavily doped region 222, a second lightly doped region 223, and a first doping type region 224 connected in sequence. The first lightly doped region 221 and the second lightly doped region 223 have no intentional doping or have a low concentration of the first or second doping type. The first heavily doped region 224 has a second doping type. The first lightly doped region 221 is electrically contacted with the gate lines 21, and the first doping type region 224 is electrically connected to the electrode layer 6.

[0060] It is understood that the gate line 21 and the electrode layer 6 are electrically connected sequentially through the first lightly doped region 221, the first heavily doped region 222, the second lightly doped region 223, and the first doped type region 224. The gate line 21, the first lightly doped region 221, and the first heavily doped region 222 are equivalent to a polysilicon diode, and the first heavily doped region 222, the second lightly doped region 223, and the first doped type region 224 are equivalent to another polysilicon diode. The above arrangement is equivalent to embedding two reverse-connected polysilicon diodes between the gate line 21 and the electrode layer 6 of the silicon carbide power device, thus introducing a thermal-electrical negative feedback loop for the silicon carbide power device.

[0061] In this process, the reverse-biased leakage current of the polysilicon diode is exponentially positively correlated with temperature, and the gate line 21 includes multiple gates. When the silicon carbide power device is short-circuited, the temperature rises rapidly, and the leakage current of the two reverse-connected polysilicon diodes embedded between the gate line 21 and the electrode layer 6 increases exponentially with the temperature. This causes the current in the gate drive circuit to increase rapidly, and the increased voltage drop across the resistance of the external gate line 21 will share the drive voltage. Therefore, the effective voltage applied to the gate decreases rapidly and significantly, thereby reducing the inversion degree of the silicon carbide power device channel or even completely turning off the channel. This effectively limits the short-circuit current of the silicon carbide power device, ultimately achieving self-regulation of the short-circuit current and clamping the junction temperature so that it no longer rises. Theoretically, an infinite short-circuit withstand time can be achieved.

[0062] Furthermore, compared to traditional silicon carbide devices, the silicon carbide power device of this application only adds a polysilicon bridge 22 and modifies the contact settings of the electrode layer 6, while retaining the polysilicon gate line 21 and the silicon carbide layer 1 structure. Therefore, it does not sacrifice key electrical performance characteristics such as on-resistance, withstand voltage, threshold voltage, output capacitance, and reverse transfer capacitance at normal operating temperatures. In addition, since the embedded polysilicon diode introduces additional capacitance, the input capacitance of the silicon carbide power device increases, which improves the ratio of input capacitance to reverse transfer capacitance, thus helping to prevent the silicon carbide power device from turning on erroneously.

[0063] Figure 2 A schematic diagram of another silicon carbide power device provided as an embodiment of this application. In some embodiments, see Figure 2Multiple polysilicon bridges 22 are disposed between two adjacent gate lines 21, and the multiple polysilicon bridges 22 are arranged along the second direction Y. Along the first direction X, the polysilicon bridge 22 includes a first lightly doped region 221, a first heavily doped region 222, a second lightly doped region 223, a first doping type region 224, a third lightly doped region, a second heavily doped region, and a fourth lightly doped region connected in sequence. Among them, the third lightly doped region and the fourth lightly doped region have no intentional doping or have a low concentration of the first doping type or the second doping type, and the second heavily doped region has the second doping type.

[0064] For example, the embodiments of this application illustrate the case where the conductivity type of the doped ions in the third lightly doped region, the second heavily doped region, and the fourth lightly doped region is all of the second doping type.

[0065] For example, the conductivity type and concentration of the dopant ions in the third lightly doped region are the same as those in the second lightly doped region 223. The conductivity type and concentration of the dopant ions in the second heavily doped region are the same as those in the first heavily doped region 222. The conductivity type and concentration of the dopant ions in the fourth lightly doped region are the same as those in the first lightly doped region 221. That is, the first lightly doped region 221, the first heavily doped region 222, and the second lightly doped region 223 are symmetrically arranged with respect to the first doping type region 224, along with the fourth lightly doped region, the second heavily doped region, and the third lightly doped region.

[0066] See also Figure 2 One of the two adjacent gate lines 21 is in electrical contact with the first lightly doped region 221, and the other is in electrical contact with the fourth lightly doped region 227.

[0067] Understandably, through the above configuration, two silicon carbide power devices can be formed at a polysilicon bridge 22 between two adjacent gate lines 21, and the two silicon carbide power devices are symmetrically arranged, thereby increasing the number of silicon carbide power devices that can be set on a unit plane (XY) area, which is beneficial to improving the integration density of silicon carbide power devices. Furthermore, it can also significantly improve the short-circuit withstand capability of silicon carbide power devices without sacrificing gate withstand voltage and electrical characteristics at normal operating temperature.

[0068] In some embodiments, see Figure 2 Multiple gate lines 21 are interconnected with multiple polysilicon bridges 22 to form a mesh structure.

[0069] It is understood that, along the first direction X, each polysilicon bridge 22 includes two sub-polysilicon bridges connected in parallel in a straight line. The two parallel sub-polysilicon bridges share the same first contact hole 32. The opposite ends of the two parallel sub-polysilicon bridges are respectively interconnected with two adjacent parallel polysilicon gate lines 21, thereby forming a rectangular or quasi-rectangular mesh polysilicon structure.

[0070] The doping of the polysilicon bridge 22 is symmetrical about the left and right sides along the central axis (parallel to the Y direction), with the first type doped region 224 at the very center. A first contact hole 32 is provided above the first type doped region 224 to electrically connect the first type doped region 224 to the electrode layer 6. Along the first direction X, the left and right sides of the first type doped region 224 are both second doped region regions, which also contain a high-concentration heavily doped region (second heavily doped region) and two low-concentration lightly doped regions (third lightly doped region and fourth lightly doped region), with the second heavily doped region located between the third lightly doped region and the fourth lightly doped region. This arrangement is also equivalent to embedding two reverse-connected polysilicon PIN diodes between the polysilicon gate line 21 and the electrode layer 6, while the interconnected mesh polysilicon improves connectivity and structural strength.

[0071] Figure 3 for Figure 2 A partial cross-sectional view of a portion of the film layer of a silicon carbide power device along section line AA'; Figure 4 A partial cross-sectional view of a portion of the film layer of another silicon carbide power device provided for an embodiment of this application along section line AA'.

[0072] In some embodiments, see Figure 3 and Figure 4 The silicon carbide power device also includes an interlayer dielectric (ILD) 5. The interlayer dielectric 5 is disposed between the electrode layer 6 and the polysilicon layer. The material of the interlayer dielectric 5 includes an insulating dielectric material.

[0073] See Figure 3 The electrode layer 6 penetrates the interlayer dielectric layer 5 and is electrically connected to the first doped type region 224. For example, a first contact hole 32 is provided in the interlayer dielectric layer 5, and the first contact hole 32 exposes at least a portion of the first doped type region 224. The electrode layer 6 can be electrically connected to the first doped type region 224 through the first contact hole 32.

[0074] For example, such as Figure 3 The silicon carbide power device shown is a planar device. The silicon carbide layer 1 includes a substrate 15 and an epitaxial layer 14 stacked together. Multiple ion-doped regions are disposed within the epitaxial layer 14, such as a first-doped source region 11, a second-doped source region 12, and a well region 13.

[0075] The doping type in the silicon carbide layer 1 can be the same as or different from the doping type in the polycrystalline silicon layer. For example, the first doping type of the silicon carbide layer 1 and the first doping type of the polycrystalline silicon layer can both be P-type, or one can be N-type and the other P-type.

[0076] It is understood that the electrode layer 6 can be directly electrically connected to the first doped type region 224 through the interlayer dielectric layer 5, and can be electrically connected to the gate line 21 in sequence through the first doped type region 224, the second lightly doped region 223, the first heavily doped region 222 and the first lightly doped region 221.

[0077] Or see Figure 4 The silicon carbide layer 1 includes a substrate 15 and an epitaxial layer 14 disposed on the substrate 15. The silicon carbide power device also includes a gate dielectric layer 4 covering the epitaxial layer 14. A first doped type region 224 penetrates the gate dielectric layer 4 and is electrically connected to the epitaxial layer 14. An electrode layer 6 penetrates the interlayer dielectric layer 5 and is electrically connected to the epitaxial layer 14. The first doped type region 224 is electrically connected to the electrode layer 6 through the epitaxial layer 14.

[0078] For example, such as Figure 4 The silicon carbide power device shown is a planar device. The silicon carbide layer 1 includes a substrate 15 and an epitaxial layer 14 stacked together. Multiple ion-doped regions are disposed in the epitaxial layer 14, such as a first-doped source region 11, a second-doped source region 12, and a well region 13.

[0079] The doping type in the silicon carbide layer 1 can be the same as or different from the doping type in the polycrystalline silicon layer. For example, the first doping type of the silicon carbide layer 1 and the first doping type of the polycrystalline silicon layer can both be P-type, or one can be N-type and the other P-type.

[0080] It is understood that the electrode layer 6 can make electrical contact with the epitaxial layer 14 through the interlayer dielectric layer 5, and the first doped region 224 can make electrical contact with the epitaxial layer 14 through the gate dielectric layer 4, thereby connecting the electrode layer 6 with the first doped region 224. In turn, the electrode layer 6 can be connected to the gate line 21 in sequence through the first doped region 224, the second lightly doped region 223, the first heavily doped region 222, and the first lightly doped region 221.

[0081] For example, a through-hole third contact hole 320 is provided in the gate dielectric layer 4, through which the first doped region 224 can make electrical contact with the epitaxial layer 14. See also... Figure 2 In the structure, the third contact hole 320 connects the first doped type region 224 in the polysilicon bridge 22 to the first doped type source region 11 of silicon carbide, and the epitaxial layer 14 is then connected to the source metal 6 through the second contact hole 31.

[0082] Understandably, see Figure 3 and Figure 4 Both of the above connection methods can achieve electrical connection between electrode layer 6 and gate line 21.

[0083] In some embodiments, see Figures 1-4 The concentrations of both the first lightly doped region 221 and the second lightly doped region 223 are less than or equal to 10. 17 cm -3 Alternatively, the concentrations of the first lightly doped region 221, the second lightly doped region 223, the third lightly doped region, and the fourth lightly doped region are all less than or equal to 10. 17 cm -3 The concentration of the first doped region 222 is greater than or equal to 10. 18 cm -3 Alternatively, the concentrations of the first and second doped regions are greater than or equal to 10. 18 cm -3 .

[0084] Understandably, see Figure 1 The concentration of the first heavily doped region 222 is greater than the concentration of the first lightly doped region 221 and the second lightly doped region 223. The first doping type region 224 within the polysilicon bridge 22 is heavily doped, and the second doping type region includes a high-concentration heavily doped region (the first heavily doped region 222) and two low-concentration lightly doped regions (the first lightly doped region 221 and the second lightly doped region 223). The first heavily doped region 222 is located between the first lightly doped region 221 and the second lightly doped region 223, making the embedded polysilicon diode a PIN diode.

[0085] And, see also Figure 2 The concentration of the first heavily doped region 222 is greater than the concentration of the first lightly doped region 221 and the second lightly doped region 223. The concentration of the second heavily doped region is greater than the concentration of the third and fourth lightly doped regions. The first doped region 224 and the second heavily doped region within the polysilicon bridge 22 are heavily doped. The second doped region includes a high-concentration heavily doped region (the first heavily doped region 222 and the second heavily doped region) and four low-concentration lightly doped regions (the first lightly doped region 221 and the second lightly doped region 223, the third lightly doped region, and the fourth lightly doped region). The first heavily doped region 222 is located between the first lightly doped region 221 and the second lightly doped region 223, and the second heavily doped region is located between the third lightly doped region and the fourth lightly doped region, making all the embedded polysilicon diodes PIN diodes.

[0086] Furthermore, in a PIN diode, when a negative voltage (or zero bias) is applied, the PIN diode is equivalent to a combination of a capacitor and a resistor. When a positive voltage is applied, the PIN diode is equivalent to a small resistor. Utilizing the characteristics of PIN diodes, the inversion degree of the channel in silicon carbide power devices can be further reduced, or even the channel can be completely turned off. This effectively limits the short-circuit current of silicon carbide power devices, ultimately achieving self-regulation of the short-circuit current and clamping the junction temperature to prevent it from rising. Theoretically, an infinite short-circuit withstand time can be achieved.

[0087] Preferably, the first doped region 224 within the polysilicon bridge 22 has the same doping concentration as the polysilicon gate line 21 and is formed synchronously by the same process steps, with a preferred doping concentration of at least 10. 19 cm -3 .

[0088] Preferably, the four lightly doped regions of the second doping type (first lightly doped region 221, second lightly doped region 223, third lightly doped region, and fourth lightly doped region) within the polysilicon bridge 22 have the same concentration and are formed synchronously by the same process steps. The two lightly doped regions of the second doping type are responsible for bearing voltage when a positive and negative voltage are applied to the device, respectively. The specific allocation depends on the doping type; for example, in the case of P-type second doping, the lightly doped region 221 closer to the polysilicon gate line 21 bears the positive gate voltage. The first heavily doped region 222 is responsible for cutting off the electric field, preventing punch-through, and optimizing gate withstand voltage and leakage current at normal operating temperature.

[0089] Furthermore, by way of example, the gate withstand voltage can be adjusted by regulating the length and concentration of the first lightly doped region 221 and the second lightly doped region 223, or the third lightly doped region and the fourth lightly doped region. Generally, the positive voltage withstand requirement of the device gate is higher than that of the negative voltage, so the region responsible for bearing the positive voltage withstand voltage is longer.

[0090] As a preferred embodiment, the concentrations of the first doped region 222 and the second doped region are not less than 10. 18 cm -3 Preferably not less than 10 19 cm -3 The concentrations of the first lightly doped region 221, the second lightly doped region 223, the third lightly doped region, and the fourth lightly doped region are all no higher than 10. 17 cm -3 Preferably not higher than 10 16 cm -3 The above settings ensure the gate withstand voltage of the device, allowing it to be adapted to conventional gate drive designs.

[0091] Figure 5 A partial cross-sectional view along section line AA' of a portion of the film layer of another silicon carbide power device provided for an embodiment of this application.

[0092] For example, see Figures 3-5 Silicon carbide power devices can be either planar or trench-type devices.

[0093] For example, see Figure 3 and Figure 4 Silicon carbide power devices are planar devices. A planar device means that the gate of the gate line 21 of the silicon carbide power device is located above the silicon carbide layer 1. See also... Figure 5 Silicon carbide power devices are trench devices. A trench device refers to a silicon carbide power device in which at least a portion of the gate of the gate line 21 is located within an internal trench of the silicon carbide layer 1.

[0094] For example, see Figure 5 For trench-type silicon carbide power devices, the silicon carbide layer 1 has a first-doped source region 11, a second-doped source region 12, a well region 13, an epitaxial layer 14, and a substrate 15, consistent with those of conventional trench SiC MOSFETs. Furthermore, the trench-type silicon carbide power devices also conform to... Figure 2 As shown, a polysilicon bridge 22, a second contact hole 31, and a first contact hole 32 are provided.

[0095] It is understood that the gate line 21 provided in this application is connected to multiple polysilicon bridges 22 to form a structure of multiple polysilicon diodes with two reverse series connections. This structure can be applied not only to planar devices but also to trench devices. It can comprehensively and significantly improve the short-circuit withstand capability of silicon carbide power devices without sacrificing the gate withstand voltage capability and the electrical characteristics of silicon carbide power devices under normal operating temperature.

[0096] On the other hand, embodiments of this application also provide a silicon carbide MOSFET, which includes the silicon carbide power device and drain of any of the above embodiments, the gate line 21 includes a gate, and the electrode layer 6 includes a source.

[0097] It is understandable that the electrode layer 6 can be the source, and the gate and the source are electrically connected through the polysilicon bridge 22. Furthermore, by setting multiple polysilicon bridges 22, the short-circuit withstand capability of the silicon carbide MOSFET can be significantly improved in a comprehensive manner, without sacrificing the gate withstand voltage capability and the electrical characteristics of the silicon carbide MOSFET under normal operating temperature.

[0098] On the other hand, embodiments of this application also provide a silicon carbide IGBT, which includes the silicon carbide power device and collector in any of the above embodiments, the gate line 21 includes a gate, and the electrode layer 6 includes an emitter.

[0099] It is understandable that the electrode layer 6 can be the emitter, and the gate and emitter are electrically connected through the polysilicon bridge 22. Furthermore, by setting multiple polysilicon bridges 22, the short-circuit withstand capability of the silicon carbide IGBT can be significantly improved in a comprehensive manner, without sacrificing the gate withstand voltage capability and the electrical characteristics of the silicon carbide IGBT under normal operating temperature.

[0100] On the other hand, embodiments of this application also provide a method for fabricating a silicon carbide power device, which is used to fabricate the silicon carbide power device in any of the above embodiments. Figure 6 A flowchart illustrating a method for fabricating a silicon carbide power device provided in an embodiment of this application; Figures 7-9 for Figure 6 The preparation method is illustrated in the following diagrams.

[0101] See Figure 6 The preparation method includes the following steps S1 to S5: Step S1: See Figure 7 A gate dielectric layer 4 is formed on the epitaxial layer 14 of the silicon carbide layer 1, and a polysilicon layer 2 is formed on the gate dielectric layer 4. The silicon carbide layer 1 includes a substrate 15 and an epitaxial layer 14 disposed on the substrate 15.

[0102] For example, a polycrystalline silicon layer 2 of a set thickness can be uniformly deposited on the silicon carbide layer 1 by a deposition process.

[0103] For example, the silicon carbide layer 1 includes an epitaxial layer 14 and a substrate 15 stacked together. The epitaxial layer 14 contains a first-doped source region 11, a second-doped source region 12, and a well region 13. A gate dielectric layer 4 is also disposed between the epitaxial layer 14 and the polysilicon layer 2. Various doping processes in the silicon carbide material layer 1 and the formation of the gate dielectric layer 4 can be achieved using conventional silicon carbide power device manufacturing processes.

[0104] Step S2: See Figure 8Multiple photolithography and ion implantation processes are performed on the polysilicon layer 2 to form multiple gate lines 21 and multiple polysilicon bridges 22 in the polysilicon layer 2. The multiple gate lines 21 have a first doping type and are arranged along a first direction X parallel to the silicon carbide layer 1. Each gate line 21 extends along a second direction Y parallel to the silicon carbide layer 1, and each gate line 21 is connected to multiple polysilicon bridges 22. The first direction X and the second direction Y intersect. Along the first direction X, the polysilicon bridge 22 includes a first lightly doped region 221, a first heavily doped region 222, a second lightly doped region 223, and a first doping type region 224 connected sequentially. Alternatively, the polysilicon bridge 22 includes a first lightly doped region 221, a first heavily doped region 222, a second lightly doped region 223, a first doped type region 224, and a third lightly doped region, a second heavily doped region, and a fourth lightly doped region connected in sequence; the first lightly doped region 221, or the first lightly doped region 221 and the fourth lightly doped region, are in electrical contact with the gate line 21. The first lightly doped region 221, the second lightly doped region 223, the third lightly doped region, and the fourth lightly doped region are all unintentionally doped or all have a low concentration of the first doped type or the second doped type. The first heavily doped region 222 and the second heavily doped region both have the second doped type.

[0105] For example, the first lightly doped region 221, the second lightly doped region 223, the third lightly doped region, and the fourth lightly doped region can all be either unintentionally doped and of a low concentration of the first doping type, or of a low concentration of the second doping type. For instance, the embodiments of this application illustrate this by taking the first lightly doped region 221 and the second lightly doped region 223 as examples where both are of the low concentration of the second doping type.

[0106] It is understood that the polysilicon layer 2 includes a plurality of strip polysilicon gate lines 21 arranged with a set width and a set spacing and having a first doping type, and a plurality of polysilicon bridges 22 connected at one end perpendicularly to the polysilicon gate lines 21 and arranged with a set width and a set spacing, having in a first direction X away from the polysilicon gate lines 21 a plurality of polysilicon bridges consisting of a second doping type region (a first lightly doped region 221, a first heavily doped region 222, and a second lightly doped region 223) and a first doping type region 224 in sequence.

[0107] Among them, the gate line 21, the first lightly doped region 221 and the first heavily doped region 222 are equivalent to a polysilicon diode, and the first heavily doped region 222, the second lightly doped region 223 and the first doped type region 224 are equivalent to another polysilicon diode.

[0108] For example, multiple masks can be used to implant the polysilicon layer 2 multiple times at certain temperatures, energies and doses to form multiple gate lines 21 and multiple polysilicon bridges 22 in the polysilicon layer 2.

[0109] Step S3: Photolithography and etching of the polysilicon layer, retaining multiple gate lines 21 and multiple polysilicon bridges 22.

[0110] Step S4: See Figure 9 An interlayer dielectric layer 5 is formed on the side of the polysilicon layer away from the gate dielectric layer 4. The interlayer dielectric layer 5 and the interlayer dielectric layer 5 and the gate dielectric layer 4 are photolithographically etched simultaneously to form a through first contact hole 32 and a second contact hole 31, respectively. The first contact hole 32 exposes the first doped type region 224, and the second contact hole 31 exposes the epitaxial layer 14.

[0111] It is understandable that while etching the interlayer dielectric layer 5 to form the through first contact hole 32, the interlayer dielectric layer 5 can also be etched simultaneously to form the through second contact hole 31, so that a portion of the first doped type region 224 is exposed, and a portion of the epitaxial layer 14 is also exposed.

[0112] Step S5: See Figure 3 An electrode layer 6 is formed on the side of the interlayer dielectric layer 5 away from the gate dielectric layer 4. The electrode layer 6 is electrically connected to the first doped type region 224 through the first contact hole 32 and to the epitaxial layer 14 through the second contact hole 31. It can be understood that the electrode layer 6 can directly contact the first doped type region 224 through the first contact hole 32 to form an electrical connection.

[0113] It is understandable that the end of the polysilicon bridge 22 containing the first doped region 224 is directly electrically connected to the electrode layer 6. The gate line 21 passes sequentially through the first lightly doped region 221, the first heavily doped region 222, the second lightly doped region 223, and the first doped region 224, and is electrically connected to the electrode layer 6. This is equivalent to embedding two reverse-connected polysilicon diodes between the gate line 21 and the electrode layer 6. Furthermore, the electrode layer 6 can also make direct electrical contact with the epitaxial layer 14 through the second contact hole 31.

[0114] For example, after forming electrode layer 6, silicon carbide power devices can be fabricated using conventional metallization and passivation processes for silicon carbide power devices.

[0115] In the method for fabricating a silicon carbide power device provided in the embodiments of this application, a polysilicon layer 2 including multiple gate lines 21 and multiple polysilicon bridges 22 is formed on a silicon carbide layer 1. Then, an interlayer dielectric layer 5 having a first contact hole 32 is formed on the polysilicon layer 2, and an electrode layer 6 is formed on the side of the interlayer dielectric layer 5 away from the silicon carbide layer 1 to form a silicon carbide power device. The electrode layer 6 directly contacts the first doped region 224 through the first contact hole 32 in the interlayer dielectric layer 5, forming an electrical connection. Furthermore, the electrode layer 6 is connected to the epitaxial layer 14 through a second contact hole 31.

[0116] It is understood that the gate line 21 and the electrode layer 6 are electrically connected sequentially through the first lightly doped region 221, the first heavily doped region 222, the second lightly doped region 223, and the first doped type region 224. The gate line 21, the first lightly doped region 221, and the first heavily doped region 222 are equivalent to a polysilicon diode, and the first heavily doped region 222, the second lightly doped region 223, and the first doped type region 224 are equivalent to another polysilicon diode. The above arrangement is equivalent to embedding two reverse-connected polysilicon diodes between the gate line 21 and the electrode layer 6 of the silicon carbide power device, thus introducing a thermal-electrical negative feedback loop for the silicon carbide power device.

[0117] In this process, the reverse-biased leakage current of the polysilicon diode is exponentially positively correlated with temperature, and the gate line 21 includes multiple gates. When the silicon carbide power device is short-circuited, the temperature rises rapidly, and the leakage current of the two reverse-connected polysilicon diodes embedded between the gate line 21 and the electrode layer 6 increases exponentially with the temperature. This causes the current in the gate drive circuit to increase rapidly, and the increased voltage drop across the resistance of the external gate line 21 will share the drive voltage. Therefore, the effective voltage applied to the gate decreases rapidly and significantly, thereby reducing the inversion degree of the silicon carbide power device channel or even completely turning off the channel. This effectively limits the short-circuit current of the silicon carbide power device, ultimately achieving self-regulation of the short-circuit current and clamping the junction temperature so that it no longer rises. Theoretically, an infinite short-circuit withstand time can be achieved.

[0118] Furthermore, compared to traditional silicon carbide devices, the silicon carbide power device of this application only adds a polysilicon bridge 22 and modifies the contact settings of the electrode layer 6, while retaining the polysilicon gate line 21 and the silicon carbide layer 1 structure. Therefore, it does not sacrifice key electrical performance characteristics such as on-resistance, withstand voltage, threshold voltage, output capacitance, and reverse transfer capacitance at normal operating temperatures. In addition, since the embedded polysilicon diode introduces additional capacitance, the input capacitance of the silicon carbide power device increases, which improves the ratio of input capacitance to reverse transfer capacitance, thus helping to prevent the silicon carbide power device from turning on erroneously.

[0119] On the other hand, embodiments of this application also provide another method for fabricating silicon carbide power devices, which is used to fabricate silicon carbide power devices in any of the above embodiments. Figure 10 A flowchart illustrating another method for fabricating a silicon carbide power device provided as an embodiment of this application; Figures 11-13 for Figure 10 The preparation method is illustrated in the following diagrams.

[0120] See Figure 10 The preparation method includes the following steps S1 to S6: Step S1: See Figure 11A gate dielectric layer 4 is formed on the epitaxial layer 14 of the silicon carbide layer 1. The gate dielectric layer 4 is photolithographically etched and etched to form a through third contact hole 320. The silicon carbide layer 1 includes a substrate 15 and an epitaxial layer 14 disposed on the substrate 15. The third contact hole 320 exposes the epitaxial layer 14.

[0121] For example, the silicon carbide layer 1 includes an epitaxial layer 14 and a substrate 15 stacked together. The epitaxial layer 14 contains a first-doped source region 11, a second-doped source region 12, and a well region 13. A gate dielectric layer 4 is also disposed between the epitaxial layer 14 and the polysilicon layer 2. Various doping processes in the silicon carbide material layer 1 and the formation of the gate dielectric layer 4 can be achieved using conventional silicon carbide power device manufacturing processes.

[0122] Step S2: See Figure 12 A polysilicon layer 2 is formed on the gate dielectric layer 4.

[0123] Step S3: See Figure 13 The polysilicon layer 2 is subjected to multiple photolithography and ion implantation processes to form multiple gate lines 21 and multiple polysilicon bridges 22 in the polysilicon layer. The multiple gate lines 21 have a first doping type, and the multiple gate lines 21 are arranged along a first direction X parallel to the silicon carbide layer 1. Each gate line 21 extends along a second direction Y parallel to the silicon carbide layer 1, and each gate line 21 is connected to multiple polysilicon bridges 22. The first direction X and the second direction Y intersect. Along the first direction X, the polysilicon bridge 22 includes a first lightly doped region 221, a first heavily doped region 222, a second lightly doped region 223, and a first doped type region 224 connected in sequence; or, the polysilicon bridge 22 includes a first lightly doped region 221, a first heavily doped region 222, a second lightly doped region 223, a first doped type region 224, a third lightly doped region, a second heavily doped region, and a fourth lightly doped region connected in sequence. The first lightly doped region 221 is in electrical contact with the gate line 21, or the first lightly doped region 221 and the fourth lightly doped region are in electrical contact with the gate line 21. The first doped type region 224 is in electrical contact with the epitaxial layer 14 through a third contact hole 320. The first lightly doped region 221, the second lightly doped region 223, the third lightly doped region, and the fourth lightly doped region are all without intentional doping or have a low concentration of the first doped type or the second doped type; the first heavily doped region 222 and the second heavily doped region both have the second doped type.

[0124] For example, the first lightly doped region 221, the second lightly doped region 223, the third lightly doped region, and the fourth lightly doped region can all be either unintentionally doped and of low concentration, representing the first doping type, or of low concentration, representing the second doping type. For instance, the embodiments of this application illustrate this by showing that the first lightly doped region 221, the second lightly doped region 223, the third lightly doped region, and the fourth lightly doped region are all of the second doping type with low concentration.

[0125] It is understood that the polysilicon layer 2 includes a plurality of strip polysilicon gate lines 21 arranged with a set width and a set spacing and having a first doping type, and a plurality of polysilicon bridges 22 connected at one end perpendicularly to the polysilicon gate lines 21 and arranged with a set width and a set spacing, having in a first direction X away from the polysilicon gate lines 21 a plurality of polysilicon bridges consisting of a second doping type region (a first lightly doped region 221, a first heavily doped region 222, and a second lightly doped region 223) and a first doping type region 224 in sequence.

[0126] Among them, the gate line 21, the first lightly doped region 221 and the first heavily doped region 222 are equivalent to a polysilicon diode, and the first heavily doped region 222, the second lightly doped region 223 and the first doped type region 224 are equivalent to another polysilicon diode.

[0127] For example, multiple masks can be used to implant the polysilicon layer 2 multiple times at certain temperatures, energies and doses to form multiple gate lines 21 and multiple polysilicon bridges 22 in the polysilicon layer 2.

[0128] Step S4: Photolithography and etching of polysilicon layer 2, retaining multiple gate lines 21 and multiple polysilicon bridges 22.

[0129] Step S5: An interlayer dielectric layer 5 is formed on the side of the epitaxial layer 14 away from the substrate 15, and the interlayer dielectric layer 5 and the gate dielectric layer 4 are etched to form a through second contact hole 31, which exposes the epitaxial layer 14.

[0130] For example, the position design of the second contact hole 31 can be as follows: Figure 1 and Figure 2 As shown.

[0131] Step S6: See Figure 4 An electrode layer 6 is formed on the side of the interlayer dielectric layer 5 away from the silicon carbide layer 1. The electrode layer 6 is electrically connected to the epitaxial layer 14 through the second contact hole 31.

[0132] It is understandable that, such as Figure 1 As shown, at one end of the polysilicon bridge 22, where the first doped region 224 is located, it is electrically connected to the electrode layer 6 through the epitaxial layer 14. The gate line 21 passes through the first lightly doped region 221, the first heavily doped region 222, the second lightly doped region 223, and the first doped region 224 in sequence, and is electrically connected to the electrode layer 6. This is equivalent to embedding two polysilicon diodes in reverse series between the gate line 21 and the electrode layer 6.

[0133] For example, after forming electrode layer 6, silicon carbide power devices can be fabricated using conventional metallization and passivation processes for silicon carbide power devices.

[0134] In the method for fabricating a silicon carbide power device provided in the embodiments of this application, a polysilicon layer 2 including multiple gate lines 21 and multiple polysilicon bridges 22 is formed on a silicon carbide layer 1. Then, an interlayer dielectric layer 5 having a second contact hole 31 is formed on the polysilicon layer 2, and an electrode layer 6 is formed on the side of the interlayer dielectric layer 5 away from the silicon carbide layer 1 to form a silicon carbide power device. The electrode layer 6 is electrically contacted with the epitaxial layer 14 through the second contact hole 31 in the interlayer dielectric layer 5, and the first doped region 224 is electrically contacted with the epitaxial layer 14 through a third contact hole 320, thereby forming an electrical connection between the electrode layer 6 and the first doped region 224.

[0135] It is understood that the gate line 21 and the electrode layer 6 are electrically connected sequentially through the first lightly doped region 221, the first heavily doped region 222, the second lightly doped region 223, the first doped type region 224, and the epitaxial layer 14. The gate line 21, the first lightly doped region 221, and the first heavily doped region 222 are equivalent to a polysilicon diode, and the first heavily doped region 222, the second lightly doped region 223, and the first doped type region 224 are equivalent to another polysilicon diode. The above arrangement is equivalent to embedding two reverse-connected polysilicon diodes between the gate line 21 and the electrode layer 6 of the silicon carbide power device, thus introducing a thermal-electric negative feedback loop for the silicon carbide power device.

[0136] In this process, the reverse-biased leakage current of the polysilicon diode is exponentially positively correlated with temperature, and the gate line 21 includes multiple gates. When the silicon carbide power device is short-circuited, the temperature rises rapidly, and the leakage current of the two reverse-connected polysilicon diodes embedded between the gate line 21 and the electrode layer 6 increases exponentially with the temperature. This causes the current in the gate drive circuit to increase rapidly, and the increased voltage drop across the resistance of the external gate line 21 will share the drive voltage. Therefore, the effective voltage applied to the gate decreases rapidly and significantly, thereby reducing the inversion degree of the silicon carbide power device channel or even completely turning off the channel. This effectively limits the short-circuit current of the silicon carbide power device, ultimately achieving self-regulation of the short-circuit current and clamping the junction temperature so that it no longer rises. Theoretically, an infinite short-circuit withstand time can be achieved.

[0137] Furthermore, compared to traditional silicon carbide devices, the silicon carbide power device of this application only adds a polysilicon bridge 22 and modifies the contact settings of the electrode layer 6, while retaining the polysilicon gate line 21 and the silicon carbide layer 1 structure. Therefore, it does not sacrifice key electrical performance characteristics such as on-resistance, withstand voltage, threshold voltage, output capacitance, and reverse transfer capacitance at normal operating temperatures. In addition, since the embedded polysilicon diode introduces additional capacitance, the input capacitance of the silicon carbide power device increases, which improves the ratio of input capacitance to reverse transfer capacitance, thus helping to prevent the silicon carbide power device from turning on erroneously.

[0138] On the other hand, embodiments of this application also provide another method for fabricating silicon carbide power devices, which is used to fabricate silicon carbide power devices in any of the above embodiments. Figure 14 A flowchart illustrating another method for fabricating a silicon carbide power device provided as an embodiment of this application; Figures 15-21 for Figure 14 The preparation method is illustrated in the following diagrams.

[0139] See Figure 14 The preparation method includes the following steps S1 to S6: Step S1: See Figure 15 A gate dielectric layer 4 is formed on the epitaxial layer 14 of the silicon carbide layer 1, and a polysilicon layer 2 with a heavily doped first doping type is formed on the gate dielectric layer 4. The silicon carbide layer 1 includes a substrate 15 and an epitaxial layer 14 disposed on the substrate 15.

[0140] Step S2: See Figure 16 The polysilicon layer 2 is photolithographically etched and etched, retaining multiple gate lines 21 and multiple first doped region 224. The multiple gate lines 21 are arranged along a first direction X parallel to the silicon carbide layer 1, and each gate line 21 extends along a second direction Y parallel to the silicon carbide layer 1. The first direction X and the second direction Y intersect. For example, the embodiments of this application are illustrated with the first direction X being perpendicular to the second direction Y.

[0141] Step S3: See Figure 17 and Figure 18 A polysilicon layer 2 with no intentional doping or with low concentration of doping is deposited, and photolithography and ion implantation are performed on the polysilicon layer 2 to form a first doped region 222 of multiple polysilicon bridges 22 in the polysilicon layer 2, or to form a first doped region 222 and a second doped region.

[0142] Each gate line 21 is connected to a plurality of polysilicon bridges 22. Along the first direction X, the polysilicon bridge 22 includes a first lightly doped region 221, a first heavily doped region 222, a second lightly doped region 223, and a first doping type region 224 connected in sequence. Alternatively, the polysilicon bridge 22 includes a first lightly doped region 221, a first heavily doped region 222, a second lightly doped region 223, a first doping type region 224, a third lightly doped region, a second heavily doped region, and a fourth lightly doped region connected in sequence.

[0143] The first lightly doped region 221, or the first lightly doped region 221 and the fourth lightly doped region, is in electrical contact with the gate line 21. The first lightly doped region 221, the second lightly doped region 223, the third lightly doped region, and the fourth lightly doped region are all composed of deposited polycrystalline silicon with no intentional doping or with low concentration doping. The first heavily doped region 222 and the second heavily doped region both have a second doping type.

[0144] It is understood that the polysilicon layer 2 includes a plurality of strip polysilicon gate lines 21 arranged with a set width and a set spacing and having a first doping type, and a plurality of polysilicon bridges 22 connected at one end perpendicularly to the polysilicon gate lines 21 and arranged with a set width and a set spacing, having in a first direction X away from the polysilicon gate lines 21 a plurality of polysilicon bridges consisting of a second doping type region (a first lightly doped region 221, a first heavily doped region 222, and a second lightly doped region 223) and a first doping type region 224 in sequence.

[0145] Among them, the gate line 21, the first lightly doped region 221 and the first heavily doped region 222 are equivalent to a polysilicon diode, and the first heavily doped region 222, the second lightly doped region 223 and the first doped type region 224 are equivalent to another polysilicon diode.

[0146] Step S4: See Figure 19 The polysilicon layer 2 is photolithographically etched and etched, retaining multiple gate lines 21 and multiple polysilicon bridges 22.

[0147] Step S5: See Figure 20 An interlayer dielectric layer 5 is formed on the side of the polysilicon layer 2 away from the gate dielectric layer 4. The interlayer dielectric layer 5 and the interlayer dielectric layer 5 and the gate dielectric layer 4 are photolithographically etched simultaneously to form a through first contact hole 32 and a second contact hole 31, respectively. The first contact hole 32 exposes the first doped type region 224, and the second contact hole 31 exposes the epitaxial layer 14.

[0148] Step S6: See Figure 1 , Figure 2 and Figure 21 An electrode layer 6 is formed on the side of the interlayer dielectric layer 5 away from the gate dielectric layer 4. The electrode layer 6 is electrically connected to the first doped type region 224 through the first contact hole 32 and to the silicon carbide epitaxial layer 14 through the second contact hole 31.

[0149] For example, the structure formed by this application can be as follows: Figure 1 As shown, at one end of the polysilicon bridge 22, where the first doped region 224 is located, it is electrically connected to the electrode layer 6 through the epitaxial layer 14. The gate line 21 passes through the first lightly doped region 221, the first heavily doped region 222, the second lightly doped region 223, and the first doped region 224 in sequence, and is electrically connected to the electrode layer 6. This is equivalent to embedding two polysilicon diodes in reverse series between the gate line 21 and the electrode layer 6.

[0150] In this process, the reverse-biased leakage current of the polysilicon diode is exponentially positively correlated with temperature, and the gate line 21 includes multiple gates. When the silicon carbide power device is short-circuited, the temperature rises rapidly, and the leakage current of the two reverse-connected polysilicon diodes embedded between the gate line 21 and the electrode layer 6 increases exponentially with the temperature. This causes the current in the gate drive circuit to increase rapidly, and the increased voltage drop across the resistance of the external gate line 21 will share the drive voltage. Therefore, the effective voltage applied to the gate decreases rapidly and significantly, thereby reducing the inversion degree of the silicon carbide power device channel or even completely turning off the channel. This effectively limits the short-circuit current of the silicon carbide power device, ultimately achieving self-regulation of the short-circuit current and clamping the junction temperature so that it no longer rises. Theoretically, an infinite short-circuit withstand time can be achieved.

[0151] The silicon carbide power device formed by the preparation method provided in this application can significantly improve the short-circuit withstand capability of the silicon carbide power device without sacrificing the gate withstand voltage capability and the main electrical characteristics of the silicon carbide power device.

[0152] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A silicon carbide power device, characterized in that, include: A silicon carbide layer, comprising a substrate and an epitaxial layer disposed on the substrate; A gate dielectric layer is disposed on the epitaxial layer; A polycrystalline silicon layer is disposed on the gate dielectric layer or on the gate dielectric layer and the silicon carbide layer; An electrode layer is disposed on the side of the polycrystalline silicon layer away from the silicon carbide layer; The polysilicon layer includes multiple gate lines and multiple polysilicon bridges. The multiple gate lines have a first doping type. The multiple gate lines are arranged along a first direction parallel to the silicon carbide layer. Each gate line extends along a second direction parallel to the silicon carbide layer, and each gate line is connected to multiple polysilicon bridges. The first direction and the second direction intersect. Along the first direction, the polysilicon bridge includes a first lightly doped region, a first heavily doped region, a second lightly doped region, and a first doping type region connected in sequence. The first lightly doped region and the second lightly doped region have no intentional doping or have a low concentration of the first doping type or the second doping type. The first heavily doped region has the second doping type. The first lightly doped region is in electrical contact with the gate line, and the first doping type region is in electrical connection with the electrode layer.

2. The silicon carbide power device according to claim 1, characterized in that, Multiple polysilicon bridges are disposed between two adjacent gate lines, and the multiple polysilicon bridges are arranged along the second direction; Along the first direction, the polysilicon bridge includes a first lightly doped region, a first heavily doped region, a second lightly doped region, a first doping type region, a third lightly doped region, a second heavily doped region, and a fourth lightly doped region connected in sequence, wherein the third lightly doped region and the fourth lightly doped region have no intentional doping or have a low concentration of the first doping type or the second doping type, and the second heavily doped region has the second doping type. One of the two adjacent gate lines is electrically connected to the first lightly doped region, and the other is electrically connected to the fourth lightly doped region.

3. The silicon carbide power device according to claim 2, characterized in that, The multiple gate lines are interconnected with multiple polysilicon bridges to form a mesh structure.

4. The silicon carbide power device according to claim 1, characterized in that, The silicon carbide power device further includes an interlayer dielectric layer; The electrode layer is electrically connected to the first doped region through a first contact hole penetrating the interlayer dielectric layer, and simultaneously, the electrode layer is electrically connected to the epitaxial layer through a second contact hole penetrating the interlayer dielectric layer and the gate dielectric layer; or, The first doped region is electrically connected to the epitaxial layer through a third contact hole penetrating the gate dielectric layer, and the electrode layer is electrically connected to the epitaxial layer through a second contact hole penetrating the interlayer dielectric layer and the gate dielectric layer.

5. The silicon carbide power device according to claim 1 or 2, characterized in that, Multiple polysilicon bridges are disposed between two adjacent gate lines, and the multiple polysilicon bridges are arranged along the second direction; Along the first direction, the polysilicon bridge includes a first lightly doped region, a first heavily doped region, a second lightly doped region, a first doping type region, a third lightly doped region, a second heavily doped region, and a fourth lightly doped region connected in sequence. The third lightly doped region and the fourth lightly doped region are unintentionally doped or have a low concentration of the first or second doping type, while the second heavily doped region has a second doping type. One of two adjacent gate lines is electrically contacted with the first lightly doped region, and the other is electrically contacted with the fourth lightly doped region. The concentrations of both the first lightly doped region and the second lightly doped region are less than or equal to 10. 17 cm -3 Alternatively, the concentrations of the first lightly doped region, the second lightly doped region, the third lightly doped region, and the fourth lightly doped region are all less than or equal to 10. 17 cm -3 ; The concentration of the first heavily doped region is greater than or equal to 10. 18 cm -3 Alternatively, the concentrations of the first heavily doped region and the second heavily doped region are greater than or equal to 10. 18 cm -3 .

6. A method for fabricating a silicon carbide power device, characterized in that, Used to prepare silicon carbide power devices as described in any one of claims 1 to 5; The preparation method includes: A gate dielectric layer is formed on the epitaxial layer of a silicon carbide layer, and a polysilicon layer is formed on the gate dielectric layer. The silicon carbide layer includes a substrate and the epitaxial layer disposed on the substrate. The polysilicon layer is subjected to multiple photolithography and ion implantation processes to form multiple gate lines and multiple polysilicon bridges within the polysilicon layer. The multiple gate lines have a first doping type and are arranged along a first direction parallel to the silicon carbide layer. Each gate line extends along a second direction parallel to the silicon carbide layer and is connected to multiple polysilicon bridges. The first direction and the second direction intersect. Along the first direction, each polysilicon bridge includes a first lightly doped region, a first heavily doped region, a second lightly doped region, and a first doping type region connected sequentially. Alternatively, the... The polysilicon bridge comprises a first lightly doped region, a first heavily doped region, a second lightly doped region, a first doping type region, a third lightly doped region, a second heavily doped region, and a fourth lightly doped region connected in sequence; the first lightly doped region, or the first lightly doped region and the fourth lightly doped region, are in electrical contact with the gate line; the first lightly doped region, the second lightly doped region, the third lightly doped region, and the fourth lightly doped region are all unintentionally doped or all have a low concentration of the first doping type or the second doping type; the first heavily doped region and the second heavily doped region both have the second doping type; The polysilicon layer is photolithographically etched and etched, retaining the multiple gate lines and the multiple polysilicon bridges; An interlayer dielectric layer is formed on the side of the polysilicon layer away from the gate dielectric layer. The interlayer dielectric layer and the interlayer dielectric layer and the gate dielectric layer are photolithographically etched simultaneously to form a first contact hole and a second contact hole, respectively. The first contact hole exposes the first doped region and the second contact hole exposes the epitaxial layer. An electrode layer is formed on the side of the interlayer dielectric layer away from the gate dielectric layer. The electrode layer is electrically connected to the first doped type region through the first contact hole and to the silicon carbide epitaxial layer through the second contact hole.

7. A method for fabricating a silicon carbide power device, characterized in that, Used to prepare silicon carbide power devices as described in any one of claims 1 to 5; The preparation method includes: A gate dielectric layer is formed on the epitaxial layer of a silicon carbide layer. The gate dielectric layer is photolithographically etched and etched to form a through third contact hole. The silicon carbide layer includes a substrate and the epitaxial layer disposed on the substrate. The third contact hole exposes the epitaxial layer. A polysilicon layer is formed on the gate dielectric layer; The polysilicon layer is subjected to multiple photolithography and ion implantation processes to form multiple gate lines and multiple polysilicon bridges within the polysilicon layer. The multiple gate lines have a first doping type and are arranged along a first direction parallel to the silicon carbide layer. Each gate line extends along a second direction parallel to the silicon carbide layer and is connected to multiple polysilicon bridges. The first direction and the second direction intersect. Along the first direction, each polysilicon bridge includes a first lightly doped region, a first heavily doped region, a second lightly doped region, and a first doping type region connected in sequence; or, the polysilicon bridge includes a second lightly doped region, a third heavily doped region, and a second lightly doped region connected in sequence. The system comprises a lightly doped region, a first heavily doped region, a second lightly doped region, a first doping type region, a third lightly doped region, a second heavily doped region, and a fourth lightly doped region. The first lightly doped region, or either the first lightly doped region or the fourth lightly doped region, is electrically contacted with the gate line. The first doped type region is electrically contacted with the epitaxial layer via the third contact hole. The first lightly doped region, the second lightly doped region, the third lightly doped region, and the fourth lightly doped region are all without intentional doping or have a low concentration of the first or second doping type. The first heavily doped region and the second heavily doped region both have the second doping type. The polysilicon layer is photolithographically etched and etched, retaining the multiple gate lines and the multiple polysilicon bridges; An interlayer dielectric layer is formed on the side of the epitaxial layer away from the substrate, and the interlayer dielectric layer and the gate dielectric layer are etched to form a through second contact hole, the second contact hole exposing the epitaxial layer; An electrode layer is formed on the side of the interlayer dielectric layer away from the silicon carbide layer, and the electrode layer is electrically connected to the epitaxial layer through the second contact hole.

8. A method for fabricating a silicon carbide power device, characterized in that, Used to prepare silicon carbide power devices as described in any one of claims 1 to 5; The preparation method includes: A gate dielectric layer is formed on the epitaxial layer of a silicon carbide layer, and a polysilicon layer having a heavily doped first doping type is formed on the gate dielectric layer, wherein the silicon carbide layer includes a substrate and the epitaxial layer disposed on the substrate; The polysilicon layer is photolithographically etched and etched, retaining the plurality of gate lines and the plurality of first doped type regions. The plurality of gate lines are arranged along a first direction parallel to the silicon carbide layer, and each gate line extends along a second direction parallel to the silicon carbide layer. The first direction and the second direction intersect. A polycrystalline silicon layer with no intentional doping or low doping concentration is deposited. The polycrystalline silicon layer is then photolithographically ... The polysilicon layer is photolithographically etched and etched, retaining the multiple gate lines and the multiple polysilicon bridges; An interlayer dielectric layer is formed on the side of the polysilicon layer away from the gate dielectric layer. The interlayer dielectric layer and the interlayer dielectric layer and the gate dielectric layer are photolithographically etched simultaneously to form a first contact hole and a second contact hole, respectively. The first contact hole exposes the first doped region and the second contact hole exposes the epitaxial layer. An electrode layer is formed on the side of the interlayer dielectric layer away from the gate dielectric layer. The electrode layer is electrically connected to the first doped type region through the first contact hole and to the silicon carbide epitaxial layer through the second contact hole.

9. A silicon carbide MOSFET, characterized in that, The device includes a silicon carbide power device and a drain as described in any one of claims 1 to 5, wherein the gate line is connected to the gate electrode and the electrode layer is connected to the source electrode.

10. A silicon carbide IGBT, characterized in that, The device includes a silicon carbide power device and a collector as described in any one of claims 1 to 5, wherein the gate line is connected to the gate electrode and the electrode layer is connected to the emitter electrode.

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