A semiconductor device and a manufacturing method thereof

Abstract

This invention discloses a semiconductor device, comprising: a substrate; an epitaxial layer located on the substrate; a P-type base region located in the epitaxial layer; an N-type source region located in the P-type base region; and a plurality of P-type base regions. + The N-type source region, located in the epitaxial layer, has a higher doping concentration than the P-type base region. The trench extends downwards from the upper surface of the semiconductor device, sequentially passing through the N-type source region and the P-type base region, resulting in a first N-type source region, a first P-type base region, a second N-type source region, and a first P-type base region located on either side of the trench, respectively. It then extends into the epitaxial layer, with the trench located in multiple P-type base regions. + The device comprises a gate structure located within a trench, consisting of a gate oxide layer and a polysilicon gate layer arranged sequentially from bottom to top; and multiple N-type doped regions located in the epitaxial layer near the substrate, each having a first conductivity type. The inclusion of multiple N-type doped regions in this semiconductor device reduces the electric field stress on the gate oxide layer, improving the long-term reliability and breakdown voltage of the device; it also reduces the on-resistance and conduction losses.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more specifically, to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] Power devices play a crucial role in power conversion, power processing, and motor drive systems. Silicon carbide (SiC), a typical representative of wide-bandgap semiconductors, possesses excellent characteristics such as a high critical breakdown electric field, high thermal conductivity, and high saturated electron drift velocity. Compared to the currently mainstream silicon-based insulated-gate bipolar transistors (Si IGBTs), silicon carbide-based metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) employ a unipolar conduction mechanism and do not exhibit minority carrier storage effects. Therefore, they have lower switching losses and higher operating frequencies, demonstrating significant advantages in high-voltage, high-frequency, and high-temperature applications.

[0003] In the device structure design of SiC MOSFETs, trench gate structures have attracted widespread attention due to their higher cell density, lower conduction losses, and stronger switching performance compared to planar gate structures. However, trench gate SiC MOSFETs still face several technical challenges in practical applications. The electric field concentration at the bottom of the gate trench is particularly prominent. Specifically, when the device is in reverse blocking mode, the electric field lines become highly concentrated in the corner region at the bottom of the trench due to curvature effects, resulting in a local electric field intensity much higher than the average electric field level of the material. This electric field concentration significantly increases the electric field stress on the gate oxide layer, thereby reducing the long-term reliability of the gate oxide layer and potentially even causing premature breakdown of the gate dielectric under conditions below the device's rated breakdown voltage.

[0004] Secondly, the static and dynamic performance of SiC MOSFETs cannot be decoupled. Low conduction loss in static performance requires low resistance, high doping, and a short channel; while low switching loss in dynamic performance requires low capacitance, low gate charge, and rapid depletion layer formation. The requirements for design parameters such as doping, thickness, and oxide layer are contradictory, therefore true decoupling is impossible. Summary of the Invention

[0005] The purpose of this invention is to provide a semiconductor device in which multiple N-type doped regions can reduce the electric field stress on the gate oxide layer, improve the long-term reliability and breakdown voltage of the device, and also reduce the on-resistance and conduction loss of the device.

[0006] To achieve the above objectives, the present invention provides a semiconductor device comprising: The substrate has a first type of conductivity; The epitaxial layer, located on the substrate, has a first conductivity type; The P-type base region, located in the epitaxial layer, has a second conductivity type; The N-type source region, located in the P-type base region, has the first conductivity type; Multiple P + The region, located in the epitaxial layer, has a second conductivity type and a higher doping concentration than the P-type base region; The trench extends downwards from the top surface of the semiconductor device, sequentially passing through the N-type source region and the P-type base region, to form a first N-type source region, a first P-type base region, a second N-type source region, and a first P-type base region located on both sides of the trench, respectively; and extends into the epitaxial layer. The trench is located in multiple P-type base regions. + Between districts; The gate structure, located within the trench, includes a gate oxide layer and a polysilicon gate arranged sequentially from bottom to top. Multiple N-type doped regions are located in the epitaxial layer near the substrate and have the first conductivity type; The source metal, along with the first N-type source region, the second N-type source region, and multiple P-type source regions. + Zone electrical connection; Drain metal, located on the lower surface of the substrate; The gate metal is electrically connected to the L-type polysilicon gate.

[0007] Preferably, the plurality of N-type doped regions include at least one located in P + The first group of N-type doped regions below the gate structure and at least one second group of N-type doped regions below the gate structure, wherein the doping concentration of the first group of N-type doped regions is higher than that of the second group of N-type doped regions.

[0008] Preferably, the implantation window width of the first group of N-type doped regions is related to the P-type doped region. + The implantation window width of the region allows the first group of N-type doped regions to be P-type doped in the horizontal direction. + Area coverage.

[0009] Preferably, the polysilicon gate is configured as an L-shape, and the depth and width of the L-shaped polysilicon gate are adjustable.

[0010] Preferably, it further includes an interlayer dielectric layer covering at least a portion of the L-shaped polysilicon gate; An interlayer dielectric layer is stacked on top of the gate oxide layer to form the insulating layer of the gate structure, thereby adjusting the MOS capacitance.

[0011] Preferably, the first P-type base region and the first N-type source region constitute the first MOS cell, and the second P-type base region and the second N-type source region constitute the second MOS cell; the first MOS cell and the second MOS cell are asymmetrically arranged in terms of doping concentration, channel length and / or implantation depth, so as to optimize the static electrical performance and dynamic electrical performance respectively.

[0012] Preferably, the trench includes a first trench and a second trench arranged symmetrically; multiple P + The district includes: First P + The area is located on the side of the first trench that is furthest from the second trench; Second P + The area is located on the side of the second trench that is furthest from the first trench; Third P + The area is located between the first trench and the second trench.

[0013] Preferably, wherein the third P + The shape of the area is similar to that of the first P + District and Second P + The areas have different shapes; Source metal and first P + District and Second P + The region forms a planar ohmic contact and interacts with the third P. + The area forms ohmic contact on the sides and front.

[0014] This invention also provides a method for fabricating a semiconductor device, comprising the following steps: S1. An N-type epitaxial layer is grown on an N-type silicon carbide substrate; S2. An N-type source is formed through ion implantation; S3. Formation of P-type base regions via ion implantation; S4. Multiple P-type cells are formed through ion implantation. + district; S5. Multiple N-type doped regions are formed by ion implantation, wherein the doping concentration of the first group of N-type doped regions is higher than that of the second group of N-type doped regions. S6. Etching to form trenches; S7, Growth gate oxide layer; S8. Deposit polysilicon and etch to form an L-shaped polysilicon gate; S9, deposit interlayer dielectric layer and etch; S10 forms the source metal, drain metal, and gate metal.

[0015] Preferably, in S3, the injection concentration of the P-type base region is controlled to be different in different regions; In S8, the etching depth and / or width of the L-type polysilicon gate are controlled.

[0016] According to the above technical solution, the P of the present invention +Deep junctions can mitigate electric field issues. In semiconductor devices, when the interface of a PN junction is not planar but curved, especially with convex corners, electric field lines become densely compressed at the bends. The P-type base region and the N-type drift region form a perpendicular PN junction. At the bottom corner of the trench, the interface of this PN junction abruptly changes direction; this turning point is where the curvature is greatest, and the electric field lines become highly concentrated here, forming electric field spikes. The gate oxide layer is located in this high-electric-field region. If the electric field spike exceeds the oxide layer's withstand capability, the gate oxide layer will prematurely break down, leading to device failure.

[0017] P + The region is a heavily doped, deep-junction p-type region. Without p... + In deep junctions, the depletion layer primarily extends from the P-type base region to the N-type drift region, with the trench corner marking the start of the depletion layer; therefore, the peak electric field occurs at the corner. With P... + After deep condensation, P + The P region and the N drift region also form a PN junction. + The deeper the region and the higher the doping concentration, the greater the extent of its depletion layer extension. Therefore, the high-electric-field region is "pushed" to the P-value. + The electric field strength is concentrated around the trench corners, rather than concentrated around them. The electric field strength decreases significantly at the trench corners. Furthermore, a deep junction implies that P... + The zone extends deeper, beyond the bottom of the trench, causing the depletion layer to begin expanding from below the trench, forming a protective layer for the bottom of the trench.

[0018] Preferably, P + The region is heavily doped with e 17 ~e 21 It is much higher than that of ordinary P-type base regions. 16 ~e 18 , making P + The depletion layer of the PN junction formed by the N-drift region and the N-drift region mainly extends towards the N-drift region side, thus achieving depletion without increasing the P-value. + With a wider trench, a larger N-side depletion width is obtained, thereby more effectively controlling the electric field distribution and achieving reliable protection from the bottom of the trench.

[0019] Multiple N-type doped regions are also disposed near the substrate in the epitaxial layer. These N-type doped regions have the first conductivity type N-type, and their doping concentration is higher than that of the epitaxial layer, but they can be different from each other. Multiple N-type doped regions are used to improve the electric field concentration problem at the bottom of the gate trench. Specifically, the presence of multiple N-type doped regions can guide the current path and change the depletion layer expansion mode, thereby effectively alleviating the electric field concentration problem at the corner of the trench bottom. Compared with the traditional trench gate structure without N-type doped regions, the presence of multiple N-type doped regions can reduce the electric field stress on the gate oxide layer, improving the long-term reliability and breakdown voltage of the device.

[0020] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0021] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the following detailed description to explain the invention, but do not constitute a limitation thereof. In the drawings: Figure 1-11 This is a schematic diagram of the structure corresponding to each step in the fabrication method of a semiconductor device provided in an embodiment of the present invention; Figure 12 It is a semiconductor device.

[0022] Explanation of reference numerals in the attached figures 100 substrate; 102 epitaxial layer; 400 first P + District; 402 Second P + District; 404 Third Page + Regions; 200 First N-type source region; 300 First P-type base region; 202 Second N-type source region; 302 Second P-type base region; 700, 702 Gate oxide layers; 800, 802 Polysilicon gate; 500, 502, 504 First group of N-type doped regions; 506, 508 Second group of N-type doped regions; 1000, 1002 Interlayer dielectric layer; 1200 Source metal. Detailed Implementation

[0023] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0024] In this invention, unless otherwise stated, directional terms included in the terminology represent only the orientation of the term in its normal use or as commonly understood by those skilled in the art, and should not be regarded as a limitation on the term.

[0025] See Figure 1 A semiconductor device comprising: Substrate 100 has a first conductivity type; Epitaxial layer 102, located on substrate 100, has a first conductivity type; The P-type base region, located in the epitaxial layer, has a second conductivity type; The N-type source region, located in the P-type base region, has the first conductivity type; Multiple P + The region, located in the epitaxial layer 102, has a second conductivity type and a higher doping concentration than the P-type base region; The trench extends downward from the upper surface of the semiconductor device, sequentially passing through the N-type source region and the P-type base region, to form a first N-type source region 200, a first P-type base region 300, and a second N-type source region 202 and a first P-type base region 302 located on both sides of the trench, respectively; and extends into the epitaxial layer 102. The trench is located in multiple P-type base regions. + Between districts; The gate structure, located in the trench, includes gate oxide layers 700 and 702 and polysilicon gates 800 and 802 arranged sequentially from bottom to top; Multiple N-type doped regions are located in the epitaxial layer 102 near the substrate 100 and have a first conductivity type; Source metal 1200, and the first N-type source region 200, the second N-type source region 202, and multiple P + Electrical connections for zones 400, 402, and 404; Drain metal is located on the lower surface of substrate 100; The gate metal is electrically connected to the L-type polysilicon gates 800 and 802.

[0026] By implementing the above technical solution, a substrate 100 is provided, which has a first conductivity type. In this embodiment, the first conductivity type is N-type conductivity, and the substrate 100 is made of N-type silicon carbide (SiC) material.

[0027] An epitaxial layer 102 is disposed on the substrate 100. The epitaxial layer 102 also has the first conductivity type N-type, but its doping concentration is lower than that of the substrate 100. The epitaxial layer 102 is formed by epitaxial growth processes such as chemical vapor deposition.

[0028] A P-type base region is provided in the epitaxial layer 102, which has a second conductivity type, P-type. Specifically, the P-type base region includes a first P-type base region 300 and a second P-type base region 302, which are located on opposite sides of a subsequently formed trench.

[0029] An N-type source region is disposed within the P-type base region, and the N-type source region has a first conductivity type of N-type. Specifically, the N-type source region includes a first N-type source region 200 and a second N-type source region 202, which are located in the first P-type base region 300 and the second P-type base region 302, respectively, and are located near the upper surface of the device. The doping concentration of the N-type source region is relatively high.

[0030] Multiple P are also provided in the epitaxial layer 102. + Zones 400, 402, and 404, these are P... + The region exhibits a second conductivity type, P-type, and its doping concentration is higher than that of the aforementioned P-type base region. Multiple P-type base regions... + The zones are distributed at different locations in the horizontal direction to shield the electric field and provide ohmic contact.

[0031] A trench is formed, extending downwards from the upper surface of the semiconductor device, sequentially passing through the N-type source region and the P-type base region, thereby dividing the N-type source region and the P-type base region into left and right parts respectively: a first N-type source region 200 and a first P-type base region 300 located on the left side of the trench, and a second N-type source region 202 and a second P-type base region 302 located on the right side of the trench. The trench continues to extend downwards into the epitaxial layer 102, and the trench is located in multiple P-type base regions in the horizontal direction. + Between districts.

[0032] A gate structure is disposed inside the trench. This gate structure includes gate oxide layers 700 and 702 and polysilicon gates 800 and 802, arranged sequentially from bottom to top. Gate oxide layers 700 and 702 cover the inner wall of the trench, and polysilicon gates 800 and 802 fill the interior of the gate oxide layers. The gate oxide layers can be silicon dioxide, formed by thermal oxidation or atomic layer deposition (ALD); the polysilicon gates are formed by chemical vapor deposition and doped to N-type or P-type to adjust the work function.

[0033] Preferably, P + Deep junctions can mitigate electric field effects. In semiconductor devices, when the interface of a PN junction is not planar but curved, especially with convex corners, electric field lines become densely compressed at the bends. The P-type base region 300 / 302 and the N-type drift region 102 form a vertical PN junction. At the bottom corner of the trench, the interface of this PN junction abruptly changes direction; this turning point is where the curvature is greatest, and the electric field lines become highly concentrated here, forming electric field spikes. The gate oxide layer 700 / 702 is located in this high-electric-field region. If the electric field spike exceeds the oxide layer's withstand capability, the gate oxide layer will prematurely break down, leading to device failure.

[0034] P + Regions 400, 402, and 404 are heavily doped, deep-junction p-type regions. Without p... + In deep junctions, the depletion layer mainly extends from the P-type base region 300 / 302 towards the N-type drift region. The trench corner is the starting point of the depletion layer, therefore the peak electric field is located at the corner. With P... + After deep condensation, P + The P region and the N drift region also form a PN junction. + The deeper the region and the higher the doping concentration, the greater the extent of its depletion layer extension. Therefore, the high-electric-field region is "pushed" to the P-value. + The electric field strength is concentrated around the trench corners, rather than concentrated around them. The electric field strength decreases significantly at the trench corners. Furthermore, a deep junction implies that P... + The zone extends deeper, beyond the bottom of the trench, causing the depletion layer to begin expanding from below the trench, forming a protective layer for the bottom of the trench.

[0035] Preferably, P + The region is heavily doped with e17 ~e 21 The value is much higher than that of the typical P-type base region e16~e18, making P + The depletion layer of the PN junction formed by the N-drift region and the N-drift region mainly extends towards the N-drift region side, thus achieving depletion without increasing the P-value. + With a wider trench, a larger N-side depletion width is obtained, thereby more effectively controlling the electric field distribution and achieving reliable protection from the bottom of the trench.

[0036] In the epitaxial layer 102, near the substrate 100, multiple N-type doped regions 500, 502, 504, 506, and 508 are also provided. These N-type doped regions have the first conductivity type N-type, and their doping concentration is higher than that of the epitaxial layer 102, but they can be different from each other. Multiple N-type doped regions are used to improve the electric field concentration problem at the bottom of the gate trench. Specifically, the arrangement of multiple N-type doped regions 500, 502, 504, 506, and 508 can guide the current path and change the depletion layer expansion mode, thereby effectively alleviating the electric field concentration problem at the corner of the trench bottom. Compared with the traditional trench gate structure without N-type doped regions, the provision of multiple N-type doped regions can reduce the electric field stress borne by the gate oxide layer, improving the long-term reliability and breakdown voltage of the device.

[0037] In this embodiment, preferably, the plurality of N-type doped regions include at least one located in the P-type region. + The first group of N-type doped regions 500, 502, and 504 below the gate structure and at least one second group of N-type doped regions 506 and 508 located below the gate structure, wherein the doping concentration of the first group of N-type doped regions is higher than that of the second group of N-type doped regions.

[0038] The first group of N-type doped regions 500, 502, and 504 are located in P... + Below regions 400, 402, and 404, i.e., viewed vertically, the first group of N-type doped regions 500, 502, and 504 are respectively adjacent to the P-type doped regions above them. + Regions 400, 402, and 404 are corresponding in location. The second group of N-type doped regions includes regions labeled 506 and 508, which are located below the gate structure, that is, directly below or near the bottom of the trench.

[0039] The doping concentration of the first group of N-type doped regions 500, 502, and 504 is higher than that of the second group of N-type doped regions 506 and 508. In one embodiment, the doping concentration of the first group of N-type doped regions can be 1 × 10⁻⁶. 17 cm -3 ~1×10 20 cm -3 The doping concentration of the second group of N-type doped regions can be 1×10⁻⁶. 16 cm -3 ~1×10 18 cm-3 .

[0040] When the device is reverse blocked, the P-type region, including P... + A depletion layer is formed between the region and the N-type drift region, which withstands the voltage.

[0041] The first group of N-type doped regions, 500, 502, and 504, have high doping concentrations and are less prone to depletion under reverse bias. This alters the shape of the depletion layer, making the boundary of the depletion layer, which would normally extend to the bottom of the trench, flatter instead of sharply curving at the trench corners. Meanwhile, the second group of N-type doped regions, 506 and 508, are more easily depleted, thus acting as a buffer transition and preventing abrupt changes from the high-concentration region to the intrinsic epitaxial layer. Therefore, this method distributes the peak electric field at the trench corners around multiple high-concentration N-type regions, reducing the maximum electric field intensity at the corners and protecting the gate oxide layer.

[0042] When the MOSFET is forward-biased, current flows from the drain substrate 100 upward through the epitaxial layer 102, then through the N-type doped region into the channel, and finally reaches the source.

[0043] The first group of high-concentration N-type doped regions, 500, 502, and 504, have extremely low resistivity; they are located in the P-type region. + Below the first group of N-type doped regions, adjacent to the channel inlet, current preferentially flows through this path into the channel. The second group, N-type doped regions 506 and 508, with slightly higher resistivity and located deeper at the bottom of the trench, serve as auxiliary paths, diverting some current. Therefore, by setting a concentration gradient, allowing most of the current to flow along the high-concentration region, the on-resistance of the device can be significantly reduced.

[0044] If all N-type regions have the same concentration and are too high, the depletion layer may not expand effectively, reducing the device's breakdown voltage; if the concentration is too low, the electric field cannot be effectively guided. By setting two sets of concentrations, high and low, both electric field shielding and withstand voltage can be satisfied simultaneously.

[0045] This concentration difference can be achieved by adjusting the ion implantation dose. During manufacturing, the first set of implantation windows for the N-type doped regions is defined using photolithography, and a high dose of N-type ions, such as nitrogen or phosphorus, is implanted. Then, a second set of implantation windows for the N-type doped regions is defined using another photolithography step, and a lower dose is implanted. Both implantations employ high-temperature ion implantation processes to maintain the integrity of the silicon carbide lattice.

[0046] In this embodiment, preferably, the implantation window width of the first group of N-type doped regions 500, 502, and 504 is related to the P-type doped region width. + The implantation window widths of regions 400, 402, and 404 allow the first group of N-type doped regions to be horizontally p-doped. +Area 400, 402, and 404 are covered.

[0047] If the high-concentration N-type doped regions 500, 502, and 504 in the first group have too wide lateral diffusion, they will extend beyond the P-type doped region. + Below the region, it is directly exposed at the bottom corner of the trench. At this point, the PN junction formed by the high-concentration N-type region and the P-type base region will interfere with the P-type base. + The original exhaustion layer expansion mode of the region weakens P. + The shielding capability of the area against the electric field at the corner.

[0048] Therefore, the highest concentrations of the first group of N-type doped regions 500, 502, and 504 are strictly limited to P. + Directly below the area, making it P + The lower concentration of the second group of N-type doped regions 506 and 508 can be appropriately distributed below the trench to provide an auxiliary path without significantly weakening the shielding effect.

[0049] In this embodiment, preferably, the polysilicon gate is configured as an L-type, and the depth and width of the L-type polysilicon gate are adjustable.

[0050] The etching depth and / or width of the L-shaped polysilicon gates 800 and 802 are configured to adjust the gate resistance and gate capacitance. The gate resistance is mainly determined by the cross-sectional area and length of the polysilicon gate. The L-shaped structure reduces the bottom cross-sectional area, thereby increasing the gate resistance. At the same time, the reduced area between the bottom of the gate and the underlying epitaxial layer 102 leads to a decrease in the gate-drain capacitance Cgd. By adjusting the etching parameters, the values ​​of the gate resistance and capacitance can be optimized according to different application requirements, such as high-frequency switching or low-speed high-current applications, thus obtaining products suitable for different operating environments.

[0051] In a MOSFET, a capacitance is formed between the gate and the channel. The magnitude of this capacitance is determined by the formula for a parallel-plate capacitor:

[0052] Where: C: capacitance value; ε: Dielectric constant of the insulating layer; an inherent property of the material. A: The overlap area between the gate and the channel; d: Thickness of the insulation layer; When an L-shaped polysilicon gate is used, the gate capacitance is larger and the switching loss is lower when the etching depth is small. As the etching depth increases, the overlap area at the bottom of the gate can be gradually reduced, thereby reducing the gate capacitance and improving the switching speed.

[0053] Therefore, the wider the etching width, the narrower the top of the gate, and the greater the gate resistance, which helps to suppress oscillations; the deeper the etching, the smaller the gate capacitance, and the faster the switching.

[0054] In this embodiment, preferably, it further includes interlayer dielectric layers 1000 and 1002, covering at least a portion of the L-type polysilicon gates 800 and 802; Interlayer dielectric layers 1000 and 1002 are stacked on top of gate oxide layers 700 and 702, together forming the insulating layer of the gate structure to adjust the MOS capacitance.

[0055] On top of the existing gate oxide layers 700 and 702, interlayer dielectric layers 1000 and 1002 are stacked, typically SiO2. These interlayer dielectric layers do not completely cover the entire gate, resulting in varying total insulating layer thicknesses in different regions. On the channel region near the first P-type base region 300, only 700 / 702 layers are present, indicating a thinner insulating layer. This location results in a larger gate capacitance and lower switching losses, used for controlling channel turn-on. On the channel region near the second P-type base region 302, there are 700 / 702 layers. + 1000 or 702 + 1002, increased thickness, decreased capacitance, and faster switching speed.

[0056] In this embodiment, preferably, the first P-type base region 300 and the first N-type source region 200 constitute a first MOS unit, and the second P-type base region 302 and the second N-type source region 202 constitute a second MOS unit; the first MOS unit and the second MOS unit are asymmetrically arranged in terms of doping concentration, channel length and / or implantation depth, so as to optimize static electrical performance and dynamic electrical performance respectively.

[0057] The doping concentration of the P-type base region in the first MOS cell differs from that in the second MOS cell to adjust the on-resistance on both sides. In the channel region, near the first P-type base region 300, only 700 / 702 dopant is used, resulting in a thinner insulating layer. This location has a larger gate capacitance and lower switching losses, used to control channel turn-on. The gate capacitance of the second MOS cell is smaller than that of the first MOS cell, providing a faster switching speed.

[0058] The first MOS cell is used to optimize static electrical performance, and the second MOS cell is used to optimize dynamic electrical performance. The two MOS cells operate in parallel, jointly transmitting current in the on state. During the switching process, the second MOS cell dominates the fast switching. Therefore, by adjusting the combination of the doping concentration of the P-type base region and the etching concentration and depth of the L-type polysilicon gate of the first and second MOS cells, switching elements suitable for different application scenarios and meeting different application requirements can be obtained.

[0059] In this embodiment, preferably, the trench includes a first trench and a second trench symmetrically arranged; a plurality of P + The district includes: First P + Zone 400 is located on the side of the first trench that is furthest from the second trench; Second P + Zone 402 is located on the side of the second trench that is furthest from the first trench; Third P + Zone 404 is located between the first trench and the second trench.

[0060] Each cell structure includes two trenches. Although the left and right sides of a single trench are asymmetrical, the two trenches in the cell can achieve left-right symmetry, making the overall current distribution symmetrical from left to right, thereby achieving the effect of current equalization.

[0061] Localized asymmetric structures enable performance decoupling, allowing one side of the trench to optimize static performance while the other side optimizes dynamic performance. Furthermore, by designing two symmetrical trench structures, the current distribution within the component becomes more uniform, reducing localized heat generation and improving reliability.

[0062] Moreover, by setting two grooves and three P + A dual-trench MOSFET structure was constructed in the region. Compared to a single-trench structure, the dual-trench structure can increase cell density without increasing the size of individual cells, thereby reducing on-resistance. Simultaneously, three P... + The layout of the zones provides more comprehensive protection against electric field shielding: the outermost first P + Zone 400 and Second P + Zone 402 shields the electric field at the outer corners of the two trenches, while the central third P... + Zone 404 simultaneously shields the inner corner electric fields of both trenches. This layout effectively avoids localized electric field enhancement caused by mutual coupling between the electric fields of the trenches, further improving the device's withstand voltage and reliability.

[0063] In this embodiment, preferably, the third P + The shape of section 404 is the same as that of the first P + Zone 400 and Second P + The shape of section 402 is different; Source metal 1200 and the first P + Zone 400 and Second P + Zone 402 forms a planar ohmic contact and interacts with the third P + Zone 404 forms ohmic contacts on the sides and front.

[0064] Source metal 1200 and the first P + Zone 400 and Second P + Region 402 forms a planar ohmic contact. The source metal covers these P... +The upper surface of the region, due to the first P + Zone 400 and Second P + Zone 402 has a large upper surface area and low resistance due to its planar contact.

[0065] Source metal 1200 and third P + Region 404 forms ohmic contacts on both the side and front sides. That is, the source metal not only covers the third P... + The upper surface of zone 404 is frontal, and its sidewalls are also covered. This can be achieved by making the third P during etching of the contact hole. + The sidewalls of zone 404 are exposed, allowing metal to be deposited simultaneously on both the top and sidewalls during metal deposition. This is achieved due to the third P... + Zone 404 is relatively narrow, and its top surface area is limited, but through sidewall contact, the total ohmic contact area is significantly increased.

[0066] Furthermore, the source metal 1200 uses this contact method to transfer the third P + Region 404 is shorted to the adjacent N-type source region 202, thereby clamping the potential of the P-type region and preventing the parasitic bipolar transistor (BJT) from conducting.

[0067] This shape also facilitates short-circuiting with the adjacent N-type source region 202 via a metal connection, effectively clamping the P-type region potential and preventing parasitic BJT conduction.

[0068] This invention also provides a method for fabricating a semiconductor device, comprising the following steps: S1. An N-type epitaxial layer 102 is grown on an N-type silicon carbide substrate 100; S2. An N-type source is formed through ion implantation; S3. Formation of P-type base regions via ion implantation; S4. Multiple P-type cells are formed through ion implantation. + Areas 400, 402, and 404; S5. Multiple N-type doped regions are formed by ion implantation, wherein the doping concentration of the first group of N-type doped regions 500, 502, and 504 is higher than that of the second group of N-type doped regions 506 and 508. S6. Etching to form trenches; S7, growth gate oxide layers 700 and 702; S8. Deposit polysilicon and etch to form L-type polysilicon gates 800 and 802; S9, deposit interlayer dielectric layers 1000 and 1002 and etch them; S10 forms the source metal, drain metal, and gate metal.

[0069] like Figure 1As shown, an N-type epitaxial layer 102 is grown on an N-type conductive SiC substrate 100, wherein the substrate 100 is doped with a concentration of e19~e20 and the epitaxial layer 102 is doped with a concentration of e15~e16.

[0070] like Figure 2 As shown, an N-type doped N-type source region is formed by high-temperature ion implantation of nitrogen / phosphorus elements, with a doping concentration of e19~e20; like Figure 3 As shown, a P-type doped base region is formed by high-temperature ion implantation of aluminum elements, with a doping concentration of e16~e18. The doping concentrations of the first P-type base region 300 and the second P-type base region 302 can be set to be different. like Figure 4 As shown, P is formed by high-temperature ion implantation of aluminum. + P-type doped + Region, doping concentration e17~e21; like Figure 5 As shown, multiple N-type doped regions are formed by high-temperature ion implantation of nitrogen / phosphorus elements. The doping concentration of the first group of N-type doped regions 500, 502, and 504 is greater than that of the second group of N-type doped regions 506 and 508. Furthermore, the implantation window of the first group of N-type doped regions 500, 502, and 504 is smaller than that of their corresponding P-type doped regions. + The width of the area is used to prevent the weakening of P. + The area improves the effect of electric field concentration at the bottom of the shielding trench grid; like Figure 6 As shown, the trench is formed by dry etching, and after etching, a first P-type base region 300, a first N-type source region 200, a second P-type base region 302, and a second N-type source region 202 are obtained on both sides of the trench.

[0071] like Figure 7 As shown, the gate oxide layer of Figure 700702 is formed by thermal oxidation growth / ALD deposition and other methods.

[0072] like Figure 8 As shown, the gate POLY of Figure 800802 is formed by depositing POLY.

[0073] like Figure 9 As shown, the 800802L-type gate POLY is formed by etching the POLY. In the figure, the etching depths of 900 and 902 can be adjusted according to the performance requirements of the MOS switch.

[0074] like Figure 10 As shown, the oxide layer structures shown in Figures 1000 and 1002 are formed by depositing SiO2.

[0075] LL-type polysilicon gates are obtained through photolithography etching, forming... Figure 11 The structure shown.

[0076] By sputtering Ni, with P + Regions 400, 402, and 404 form a P-type ohmic contact, which in turn forms an N-type ohmic contact with the N-type source regions 200 and 202. Then, Ti / TiN / Wu / Al is sputtered to form the front metal electrode 1200, resulting in... Figure 12 The cells shown.

[0077] In this embodiment, preferably, in S3, the injection concentration of the P-type base region in different regions is controlled to be different; In S8, the etching depth and / or width of the L-type polysilicon gate are controlled.

[0078] The switching characteristics of the device can be controlled by adjusting the doping concentrations of 300 and 302, as well as the etching depth and / or width of the L-type polysilicon gate.

[0079] The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the specific details of the above embodiments. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, and these simple modifications all fall within the protection scope of the present invention.

[0080] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not describe the various possible combinations separately.

[0081] Furthermore, various different embodiments of the present invention can be combined in any way, as long as they do not violate the spirit of the present invention, they should also be regarded as the content disclosed by the present invention.

Claims

1. A semiconductor device, characterized in that, include: Substrate (100) has a first conductivity type; An epitaxial layer (102), located on the substrate (100), has a first conductivity type; The P-type base region, located in the epitaxial layer, has a second conductivity type; The N-type source region, located in the P-type base region, has the first conductivity type; Multiple P + The region, located in the epitaxial layer (102), has a second conductivity type and a higher doping concentration than the P-type base region; The trench extends downward from the upper surface of the semiconductor device, passing sequentially through the N-type source region and the P-type base region, to form a first N-type source region (200), a first P-type base region (300), and a second N-type source region (202) and a first P-type base region (302) located on both sides of the trench, respectively; and extends into the epitaxial layer (102). The trench is located in the plurality of P-type base regions. + Between districts; The gate structure, located within the trench, includes a gate oxide layer (700, 702) and a polysilicon gate (800, 802) arranged sequentially from bottom to top. Multiple N-type doped regions are located in the epitaxial layer (102) near the substrate (100) and have a first conductivity type; Source metal (1200), the first N-type source region (200), the second N-type source region (202), and the plurality of P + Electrical connections for zones (400, 402, 404); Drain metal is located on the lower surface of the substrate (100); The gate metal is electrically connected to the polysilicon gate (800, 802).

2. The semiconductor device according to claim 1, characterized in that, The plurality of N-type doped regions include at least one located in the P-type doped region. + The first group of N-type doped regions (500, 502, 504) below the gate structure and at least one second group of N-type doped regions (506, 508) located below the gate structure, wherein the doping concentration of the first group of N-type doped regions is higher than that of the second group of N-type doped regions.

3. The semiconductor device according to claim 1, characterized in that, The implantation window width of the first group of N-type doped regions (500, 502, 504) and its corresponding P + The implantation window width of regions (400, 402, 404) is such that the first group of N-type doped regions is horizontally affected by the P... + The area is covered by districts (400, 402, 404).

4. The semiconductor device according to claim 1, characterized in that, The polysilicon gate is configured as an L-shape, and the depth and width of the L-shaped polysilicon gate are adjustable.

5. The semiconductor device according to claim 4, characterized in that, It also includes an interlayer dielectric layer (1000, 1002) covering at least a portion of the L-type polysilicon gate (800, 802); The interlayer dielectric layers (1000, 1002) are stacked on top of the gate oxide layers (700, 702) to form the insulating layer of the gate structure, thereby adjusting the MOS capacitance.

6. The semiconductor device according to claim 5, characterized in that, The first P-type base region (300) and the first N-type source region (200) constitute a first MOS unit, and the second P-type base region (302) and the second N-type source region (202) constitute a second MOS unit. The first MOS unit and the second MOS unit are asymmetrically arranged in terms of doping concentration, channel length and / or implantation depth, which are used to optimize static electrical performance and dynamic electrical performance respectively.

7. The semiconductor device according to claim 6, characterized in that, The trench includes a first trench and a second trench arranged symmetrically; the plurality of P + The district includes: First P + Zone (400) is located on the side of the first trench away from the second trench; Second P + Zone (402) is located on the side of the second trench away from the first trench; Third P + Zone (404) is located between the first trench and the second trench.

8. The semiconductor device according to claim 1, characterized in that, in, The third P + The shape of region (404) is the same as that of the first P + Zone (400) and the second P + The shapes of areas (402) are different; The source metal (1200) and the first P + Zone (400) and the second P + Region (402) forms a planar ohmic contact and interacts with the third P + The area (404) forms ohmic contacts on the side and front.

9. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: S1. An N-type epitaxial layer (102) is grown on an N-type silicon carbide substrate (100). S2. An N-type source region is formed through ion implantation; S3. Formation of P-type base regions via ion implantation; S4. Multiple P-type cells are formed through ion implantation. + Zones (400, 402, 404); S5. Multiple N-type doped regions are formed by ion implantation, wherein the doping concentration of the first group of N-type doped regions (500, 502, 504) is higher than that of the second group of N-type doped regions (506, 508). S6. Etching to form trenches; S7, Growth gate oxide layer (700, 702); S8. Deposit polysilicon and etch to form L-type polysilicon gates (800, 802). S9, deposit interlayer dielectric layers (1000, 1002) and etch; S10 forms the source metal, drain metal, and gate metal.

10. The preparation method according to claim 9, characterized in that, In S3, the injection concentration of the P-type base region is controlled to be different in different regions; In S8, the etching depth and / or width of the L-shaped polysilicon gate are controlled.

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