A SiC MOSFET termination structure and its fabrication method
By adjusting the ion implantation window and optimizing the conductivity type distribution, the problems of large terminal size and low utilization of SiC MOSFET devices were solved, achieving a reduction in terminal area size and cost optimization.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- XILI MICROELECTRONICS (SHENZHEN) CO LTD
- Filing Date
- 2026-03-18
- Publication Date
- 2026-07-10
AI Technical Summary
The current SiC MOSFET device has a large terminal size while meeting the breakdown voltage requirements, resulting in low device utilization on the wafer. Furthermore, the existing process requires additional photomasks and photolithography costs.
By adjusting the ion implantation window, the second conductivity type body region and the first conductivity type JFET region of the terminal region are superimposed with the second conductivity type P region of the terminal region, thereby optimizing the conductivity type distribution in the terminal region, reducing the size of the terminal region, and without increasing the manufacturing process steps.
While meeting the breakdown voltage, the terminal area size is reduced to below 60µm, improving the utilization rate of the device on the wafer and avoiding additional photomask and photolithography costs.
Smart Images
Figure CN122373422A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of SiC MOSFET device fabrication, and more particularly to a SiC MOSFET termination structure and its fabrication method. Background Technology
[0002] Electronic and electrical technologies have gradually become an indispensable part of human life, and power semiconductors, as the most basic components in these technologies, play a crucial role. Currently, silicon-based semiconductors are the most commonly used semiconductor material. However, with the development of technology, their excellent performance can no longer meet the demands of rapidly developing industrial electronics. The need for high-performance, high-reliability power semiconductor devices has thus emerged. Silicon carbide, as a third-generation semiconductor material, with its wide bandgap, high melting point, low dielectric constant, high thermal conductivity, and high saturated electron drift velocity, is widely used in applications requiring high voltage, high temperature, high frequency, and radiation resistance.
[0003] In existing technologies, SiC MOSFETs with different breakdown voltage ranges vary due to different epitaxial layer sizes. As the breakdown voltage increases, the epitaxial layer thickness gradually increases, and the termination size also increases accordingly. There are two common termination structures for existing SiC MOSFETs: Junction Terminal Extension (JTE) and Field Limiting Rings (FLR). JTE has the advantage of a short termination size, but it requires high-precision doping technology and is prone to breakdown voltage reduction due to process deviations. Compared to JTE, FLR requires a larger termination size and sufficient field limiting rings to allow the depletion layer to extend laterally. Therefore, there is an urgent need for a SiC MOSFET device termination with a small termination size and high breakdown voltage to overcome the shortcomings of existing technologies. Summary of the Invention
[0004] This invention aims to at least partially solve one of the problems in related technologies. Therefore, the objective of this invention is to provide a method for fabricating a SiC MOSFET termination structure that, while meeting the SiC MOSFET breakdown voltage, reduces the size of the termination region and improves the device utilization rate on the wafer. Furthermore, the fabrication method of this application does not require additional photomasks or photolithography costs; it only requires adjusting the corresponding injection window, without adding any additional manufacturing processes.
[0005] A method for fabricating a SiC MOSFET termination structure, comprising: S1: An epitaxial layer of the first conductivity type is formed on a substrate of the first conductivity type; S2: An active region second conductivity type body region and at least two spaced-apart terminal regions second conductivity type body regions are formed on the first conductivity type epitaxial layer; S3: A first conductivity type source region is formed in the second conductivity type body region of the active region; S4: An active region of second conductivity type P, a boundary region of second conductivity type P, and M spaced-apart terminal regions of second conductivity type P are formed on the first conductivity type epitaxial layer; and the terminal regions of second conductivity type P overlap with the terminal regions of second conductivity type body regions; M is an integer greater than or equal to 4; S5: An active region of the first conductivity type JFET region and at least two spaced-apart terminal regions of the first conductivity type JFET region are formed on the first conductivity type epitaxial layer; the terminal region of the first conductivity type JFET region overlaps with the terminal region of the second conductivity type P region, and the terminal region of the first conductivity type JFET region is located on the side of the terminal region of the second conductivity type body region away from the active region; S6: The source, drain, and gate are formed on the epitaxial layer of the first conductivity type.
[0006] Furthermore, at least one terminal region second conductivity type P region is provided between the terminal region second conductivity type body region and the boundary region second conductivity type P region; at least one terminal region second conductivity type P region is provided between two adjacent second conductivity type body regions.
[0007] Furthermore, a cutoff ring is provided on the side of the terminal region away from the active region, and at least one terminal region of the second conductivity type P is provided between the first conductivity type JFET region of the terminal region and the cutoff ring; at least one terminal region of the second conductivity type P is provided between two adjacent first conductivity type JFET regions.
[0008] Furthermore, in the first direction, the distance between the M terminal regions of the second conductivity type P region is equal, and the size of the M terminal regions of the second conductivity type P region is equal in the first direction; the first direction refers to the direction from the active region to the terminal region.
[0009] Furthermore, in the first direction, the distance between the first terminal region of the second conductivity type P region and the active region is equal to the distance between the M terminal regions of the second conductivity type P regions.
[0010] Further, step S2 includes: Hard mask polysilicon is deposited on the epitaxial layer of the first conductivity type; The hard mask polysilicon is photolithographically etched, developed, and etched to form the injection windows of the active region second conductivity type body region and the terminal region second conductivity type body region; Ions of the second conductivity type are injected through the injection window.
[0011] Further, step S3 includes: A layer of silicon dioxide is deposited on the surface of the polycrystalline silicon of the hard mask. Photolithography, development, and etching are performed on silicon dioxide to form an injection window for the first conductivity type source region located between the polysilicon in the hard mask. Ions of the first conductivity type are injected through the injection window.
[0012] Further, step S5 includes: Hard mask polysilicon is deposited on the epitaxial layer of the first conductivity type; The hard mask polysilicon is photolithographically lithographically etched, developed, and etched to form the injection windows of the active region first conductivity type JFET region and the terminal region first conductivity type JFET region; Ions of the first conductivity type are injected through the injection window; High-temperature annealing is performed using a furnace tube process; the high-temperature annealing temperature is 1600℃-1800℃, and the high-temperature annealing time is 10min-120min.
[0013] Further, step S6 includes: A gate oxide layer, a field oxide layer, and a gate polysilicon layer are formed on the epitaxial layer of the first conductivity type. An interlayer dielectric layer, a source metal, a passivation layer, and a polyimide (PI) layer are deposited on the first conductivity type epitaxial layer.
[0014] The second objective of this application is to provide a SiC MOSFET termination structure, which is fabricated based on the SiC MOSFET termination structure fabrication method described above.
[0015] Compared with the prior art, the technical solution provided in this application has the following advantages: By adjusting the ion implantation window, this application makes the second conductivity type body region and the first conductivity type JFET region of the terminal region superimposed on the second conductivity type P region of the terminal region. By optimizing the second conductivity type body region, the second conductivity type P region, and the first conductivity type JFET region in the terminal region, the overall size of the terminal region is reduced, ensuring that the size of the terminal region is less than or equal to 60um. This application reduces the size of the terminal region and improves the utilization rate of the device on the wafer while meeting the breakdown voltage of SiC MOSFET. At the same time, the fabrication method of this application does not require additional photolithography masks and photolithography costs, only the corresponding implantation window needs to be adjusted, without adding any additional manufacturing process.
[0016] This application provides a SiC MOSFET termination structure in which the second conductivity type body region and the first conductivity type JFET region of the termination region are superimposed on the second conductivity type P region of the termination region. By optimizing the second conductivity type body region, the second conductivity type P region, and the first conductivity type JFET region in the termination region, the size of the termination region is reduced and the utilization rate of the device on the wafer is improved while meeting the SiC MOSFET breakdown voltage. Attached Figure Description
[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.
[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without creative effort.
[0019] In the attached image: Figure 1 This is a schematic diagram of the SiC MOSFET termination structure in the comparative examples of this application; Figure 2 This is a schematic diagram of the SiC MOSFET termination structure in the embodiments of this application; Figure 3 This is a schematic diagram of the epitaxial layer and the second conductivity type body region in an embodiment of the present invention; Figure 4 This is a schematic diagram of forming a source region of the first conductivity type in an embodiment of the present invention; Figure 5 This is a schematic diagram of the formation of the second conductivity type P region in an embodiment of the present invention; Figure 6 This is a schematic diagram of forming a JFET region of the first conductivity type in an embodiment of the present invention; Figure 7 for Figure 1 and Figure 2 Simulated breakdown voltage diagram of SiC MOSFET termination structure.
[0020] Icon labels: 1. Substrate of first conductivity type; 2. Epitaxial layer of first conductivity type; 3. Active region of second conductivity type body region; 4. Source region of first conductivity type; 5. Active region of second conductivity type P region; 6. Active region of first conductivity type JFET region; 7. Gate oxide layer; 8. Gate polysilicon; 9. Field oxide layer; 10. Interlayer dielectric layer; 11. Source metal; 12. Passivation layer; 13. Polyimide (PI) layer; 14. Hard mask polysilicon; 301. Termination region of second conductivity type body region; 501. Termination region of second conductivity type P region; 502. Junction region of second conductivity type P region; 601. Termination region of first conductivity type JFET region; 701. Cut-off ring. Detailed Implementation
[0021] To provide a clearer understanding of the technical features, objectives, and effects of this invention, specific embodiments are now described in detail with reference to the accompanying drawings. In the following description, it should be understood that the orientations or positional relationships indicated by terms such as "front," "rear," "upper," "lower," "left," "right," "longitudinal," "horizontal," "vertical," "horizontal," "top," "bottom," "inner," "outer," "head," and "tail" are based on the orientations or positional relationships shown in the accompanying drawings, and are constructed and operated in a specific orientation. They are only for the convenience of describing this technical solution and do not indicate that the referred mechanism or element must have a specific orientation; therefore, they should not be construed as limitations on this invention.
[0022] It should also be noted that, unless otherwise explicitly specified and limited, terms such as "installation," "connection," "linking," "fixing," and "setting" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. When an component is referred to as being "on" or "below" another component, the component can be located "directly" or "indirectly" on the other component, or there may be one or more intermediary components. The terms "first," "second," "third," etc., are only for the convenience of describing this technical solution and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first," "second," "third," etc., may explicitly or implicitly include one or more of that feature. For those skilled in the art, the specific meaning of the above terms in this invention can be understood according to the specific circumstances.
[0023] In the following description, specific details such as particular system structures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of the invention. However, those skilled in the art will understand that the invention can be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, mechanisms, circuits, and methods are omitted so as not to obscure the description of the invention with unnecessary detail.
[0024] Example 1
[0025] This application also provides a method for fabricating a SiC MOSFET termination structure, including: S1: An epitaxial layer 2 of the first conductivity type is formed on a substrate 1 of the first conductivity type; S2: An active region second conductivity type body region 3 and at least two spaced-apart terminal regions second conductivity type body regions 301 are formed on the first conductivity type epitaxial layer 2; S3: A first conductivity type source region 4 is formed in the second conductivity type body region 3 of the active region; S4: An active region second conductivity type P region 5, a boundary region second conductivity type P region 502, and M spaced-apart terminal region second conductivity type P regions 501 are formed on the first conductivity type epitaxial layer 2; and the terminal region second conductivity type P region 501 overlaps with the terminal region second conductivity type body region 301; M is an integer greater than or equal to 4; wherein, the active region second conductivity type P region 5 is located in the active region, the terminal region second conductivity type P region 501 is located in the terminal region, and the boundary region second conductivity type P region 502 is located at the boundary between the active region and the terminal region.
[0026] S5: An active region first conductivity type JFET region 6 and at least two spaced-apart terminal regions first conductivity type JFET regions 601 are formed on the first conductivity type epitaxial layer 2; the terminal regions first conductivity type JFET regions 601 overlap with the terminal regions second conductivity type P regions 501, and the terminal regions first conductivity type JFET regions 601 are located on the side of the terminal regions second conductivity type body regions 301 away from the active region; S6: A gate, a source metal 11, and a drain metal are formed on the first conductivity type epitaxial layer 2.
[0027] In this application, steps S2, S3, S4, and S5 all require the formation of corresponding implantation windows before ion implantation. This application adjusts the ion implantation windows so that the second conductivity type body region 301 and the first conductivity type JFET region 601 of the terminal region are superimposed on the second conductivity type P region 501 of the terminal region. By optimizing the second conductivity type body region, the second conductivity type P region, and the first conductivity type JFET region within the terminal region, the overall size of the terminal region is reduced, ensuring that the terminal region size is less than or equal to 60µm. This application reduces the terminal region size and improves the device utilization rate on the wafer while meeting the SiC MOSFET breakdown voltage. Furthermore, the fabrication method of this application does not require additional photolithography masks or photolithography costs; only the corresponding implantation window needs to be adjusted, without adding any additional manufacturing processes.
[0028] This application provides a SiC MOSFET termination structure in which the second conductivity type body region 301 and the first conductivity type JFET region 601 of the termination region are both superimposed on the second conductivity type P region 501 of the termination region. By optimizing the second conductivity type body region, the second conductivity type P region, and the first conductivity type JFET region in the termination region, the size of the termination region is reduced and the utilization rate of the device on the wafer is improved while meeting the SiC MOSFET breakdown voltage.
[0029] Example 2
[0030] This application provides a method for fabricating a SiC MOSFET termination structure, comprising: S1: As Figure 3 As shown, a first conductivity type epitaxial layer 2 is formed on a first conductivity type substrate 1; Specifically, the substrate 1 of the first conductivity type is made of 4H-SiC, 6H-SiC, or 3C-SiC material; the doping concentration of the epitaxial layer 2 of the first conductivity type is 1e15cm. -3 -1e16 cm -3 The thickness of the first conductive epitaxial layer 2 is 5um-20um.
[0031] S2: An active region of the second conductivity type body region 3 and at least two spaced-apart terminal regions of the second conductivity type body region 301 are formed on the first conductivity type epitaxial layer 2. Specifically, this includes: S21: Deposit hard mask polysilicon 14 on the first conductivity type epitaxial layer 2; S22: The hard mask polysilicon 14 is photolithographically etched, developed, and etched to form the injection windows of the active region second conductivity type body region 3 and the terminal region second conductivity type body region 301. The photoresist coating during the photolithography process has a thickness of not less than 0.9 μm, and the hard mask polysilicon 14 is etched using a dry etching method.
[0032] S23: Implanting ions of a second conductivity type through an implantation window; in this application, the second conductivity type ion is an Al ion, and the implantation of the second conductivity type ion is formed by multiple implantations, with an implantation energy of 50 KeV-1000 KeV and a doping dose of 1e11-2e15 cm⁻¹. 2 .
[0033] S3: As Figure 4 As shown, a first conductivity type source region 4 is formed in the second conductivity type body region 3 of the active region; specifically including: S31: A layer of silicon dioxide is deposited on the surface of the hard mask polysilicon 14; S32: Photolithography, development, and etching are performed on silicon dioxide to form an injection window for a first conductivity type source region 4 located between the hard mask polysilicon 14; wherein, the first conductivity type source region 4 is formed only in the active region, and no corresponding injection window needs to be formed in the terminal region.
[0034] S33: Implanting ions of the first conductivity type through the implantation window. In this application, the implanted ions in the first conductivity type source region 4 are N ions, with an implantation energy of 50 KeV-1000 KeV and a doping dose of 1e11-5e15 cm⁻¹. 2 .
[0035] S4: As Figure 5 As shown, an active region of second conductivity type P region 5, a boundary region of second conductivity type P region 502, and M spaced-apart terminal regions of second conductivity type P region 501 are formed on the first conductivity type epitaxial layer 2; and the terminal regions of second conductivity type P region 501 overlap with the terminal regions of second conductivity type body region 301; M is an integer greater than or equal to 4; wherein, the active region of second conductivity type P region 5 is located within the active region, the terminal regions of second conductivity type P region 501 are located within the terminal region, and the boundary regions of second conductivity type P region 502 are located at the boundary between the active region and the terminal region. Specifically, it includes: S41. Remove the silicon dioxide and hard mask polysilicon 14 formed in step S3, and then deposit a certain thickness of hard mask polysilicon 14 on the first conductivity type epitaxial layer 2. Remove the hard mask polysilicon 14 by photolithography, development and etching to form the implantation windows corresponding to the active region second conductivity type P region 5, the boundary region second conductivity type P region 502 and the terminal region second conductivity type P region 501. The photoresist thickness during the photolithography process is not less than 0.9 μm; S42. Implanting second conductivity type ions onto the first conductivity type epitaxial layer through the implantation window; the second conductivity type ions are Al ions, and the second conductivity type ion implantation is formed by multiple implantations, with an implantation energy of 50 KeV-1000 KeV and a doping dose of 1e11-5e15 cm⁻¹.2 .
[0036] In this application, the injection windows of the second conductivity type P region 501 in the terminal region are distributed at equal intervals, and the injection window sizes are all the same and adjustable. The number of injection windows is less than or equal to 9.
[0037] It should be noted that in this application, the second conductive type P region 501 of the terminal region overlaps with the second conductive type body region 301 of the terminal region. At the overlapping position, the injection window for injecting the second conductive type P region 501 of the terminal region and the injection window for injecting the second conductive type body region 301 of the terminal region are the same. After two injections, an overlapping area is formed. The second conductive type P region 501 of the terminal region at the position where the second conductive type body region 301 of the terminal region is not injected only contains the second conductive type P region 501 of the terminal region. In this application, the second conductive type P regions 501 of the terminal region are distributed at intervals, and their number is much greater than the number of second conductive type body regions 301 of the terminal region.
[0038] When designing the injection window, it is important to note that: at least one terminal area second conductive type P area 501 is provided between the terminal area second conductive type body area 301 and the boundary area second conductive type P area 502; at least one terminal area second conductive type P area 501 is provided between two adjacent second conductive type body areas.
[0039] In this application, the distances between the M terminal regions of the second conductivity type P region 501 are equal, and the dimensions of the M terminal regions of the second conductivity type P region 501 are equal in a first direction; the first direction refers to the direction from the active region to the terminal region. In the first direction, the distance between the first terminal region of the second conductivity type P region 501 and the active region is equal to the distance between the M terminal regions of the second conductivity type P region 501.
[0040] S5: As Figure 6 As shown, an active region of the first conductivity type JFET region 6 and at least two spaced-apart terminal regions of the first conductivity type JFET region 601 are formed on the first conductivity type epitaxial layer 2; the terminal region of the first conductivity type JFET region 601 overlaps with the terminal region of the second conductivity type P region 501, and the terminal region of the first conductivity type JFET region 601 is located on the side of the terminal region of the second conductivity type body region 301 away from the active region; specifically including: S51: Remove the hard mask polysilicon 14 from step S4, and deposit the hard mask polysilicon 14 on the first conductivity type epitaxial layer 2. S52: Perform photolithography, development, and etching on the hard mask polysilicon 14 to form the injection windows of the active region first conductivity type JFET region 6 and the terminal region first conductivity type JFET region 601.
[0041] In this application, the first conductivity type JFET region 601 of the terminal region overlaps with the second conductivity type P region 501 of the terminal region. At the overlapping position, the injection window for injecting the second conductivity type P region 501 of the terminal region and the injection window for injecting the first conductivity type JFET region 601 of the terminal region are the same. After two injections, an overlapping region is formed. The second conductivity type P region 501 of the terminal region at the position where the first conductivity type JFET region 601 of the terminal region is not injected only contains the second conductivity type P region 501 of the terminal region. In this application, the first conductivity type JFET regions 601 of the terminal region are distributed at intervals, and their number is less than the number of second conductivity type P regions 501 of the terminal region.
[0042] When designing the injection window, it is important to note that the first conductivity type JFET region 601 of the terminal region is located on the side of the second conductivity type body region 301 of the terminal region away from the active region. In this application, a cutoff ring 701 is provided on the side of the terminal region away from the active region, and at least one second conductivity type P region 501 of the terminal region is provided between the first conductivity type JFET region 601 of the terminal region and the cutoff ring 701; at least one second conductivity type P region 501 of the terminal region is provided between two adjacent first conductivity type JFET regions.
[0043] The cutoff ring 701 can be implanted and formed synchronously with the first conductivity type JFET region 601 of the termination region. The implantation parameters and formation process of the two are the same. The cutoff ring 701 is located between the repeating termination device units and is used to realize the separation between two adjacent repeating units.
[0044] S53: Implanting ions of the first conductivity type through the implantation window; wherein the first conductivity type ions are N ions, formed by multiple implantations, with an implantation energy of 30 KeV-1000 KeV and a doping dose of 1e11-5e15 cm⁻¹. 2 ; S54: High-temperature annealing is performed using a furnace tube process; the high-temperature annealing temperature is 1600℃-1800℃, and the annealing time is 10min-120min. High-temperature annealing can activate ions and repair lattice damage.
[0045] S6: Forming the source, drain, and gate on the epitaxial layer 2 of the first conductivity type; specifically including: S61: A gate oxide layer 7, a field oxide layer 9, and a gate polysilicon 8 are formed on the first conductivity type epitaxial layer 2. Specifically, the gate oxide layer 7 is formed by a thermal oxidation process. The thermal oxidation temperature is 1300℃-1500℃, and the thickness of the gate oxide layer 7 is 400A-550A.
[0046] A field oxide layer 9 of a certain thickness is deposited on the gate oxide layer 7; the field oxide layer 9 is etched by photolithography, development and etching processes, either by dry or wet methods; the thickness of the field oxide layer 9 is 10000A-40000A.
[0047] A layer of gate polysilicon 8 is deposited, and the gate polysilicon 8 is formed by photolithography, development and etching of polysilicon; the thickness of the gate polysilicon 8 is 3000A-6000A.
[0048] S62: An interlayer dielectric layer 10, a source metal 11, a passivation layer 12, and a polyimide (PI) layer 13 are deposited on the first conductivity type epitaxial layer 2. Specifically, this includes: An interlayer dielectric layer 10 of a certain thickness is deposited, and then gate contact holes and source contact holes are selectively etched; wherein, the thickness of the interlayer dielectric layer 10 is 10000A-15000A; An ohmic contact is formed using metallic Ni, followed by the deposition of source metal 11, passivation layer 12, and polyimide PI layer 13. In this application, the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.
[0049] S63: Metallization is performed on the back side of the first conductivity type substrate 1.
[0050] Example 3
[0051] This application provides a method for fabricating a SiC MOSFET termination structure, comprising: S1: As Figure 3 As shown, a first conductivity type epitaxial layer 2 is formed on a first conductivity type substrate 1; Specifically, the substrate 1 of the first conductivity type is made of 4H-SiC, 6H-SiC, or 3C-SiC material; the doping concentration of the epitaxial layer 2 of the first conductivity type is 1e15cm. -3 -1e16 cm -3 The thickness of the first conductive epitaxial layer 2 is 5um-20um.
[0052] S2: An active region of the second conductivity type body region 3 and two spaced-apart terminal regions of the second conductivity type body region 301 are formed on the first conductivity type epitaxial layer 2. Specifically, this includes: S21: Deposit hard mask polysilicon 14 on the first conductivity type epitaxial layer 2; S22: The hard mask polysilicon 14 is photolithographically etched, developed, and etched to form the injection windows of the active region second conductivity type body region 3 and the terminal region second conductivity type body region 301. The photoresist coating during the photolithography process has a thickness of not less than 0.9 μm, and the hard mask polysilicon 14 is etched using a dry etching method.
[0053] S23: Implanting ions of a second conductivity type through an implantation window; in this application, the second conductivity type ion is an Al ion, and the implantation of the second conductivity type ion is formed by multiple implantations, with an implantation energy of 50 KeV-1000 KeV and a doping dose of 1e11-2e15 cm⁻¹. 2 .
[0054] S3: As Figure 4 As shown, a first conductivity type source region 4 is formed in the second conductivity type body region 3 of the active region; specifically including: S31: A layer of silicon dioxide is deposited on the surface of the hard mask polysilicon 14; S32: Photolithography, development, and etching are performed on silicon dioxide to form an injection window for a first conductivity type source region 4 located between the hard mask polysilicon 14; wherein, the first conductivity type source region 4 is formed only in the active region, and no corresponding injection window needs to be formed in the terminal region.
[0055] S33: Implanting ions of the first conductivity type through the implantation window. In this application, the implanted ions in the first conductivity type source region 4 are N ions, with an implantation energy of 50 KeV-1000 KeV and a doping dose of 1e11-5e15 cm⁻¹. 2 .
[0056] S4: As Figure 5 As shown, an active region of second conductivity type P region 5, a boundary region of second conductivity type P region 502, and nine spaced-apart terminal regions of second conductivity type P region 501 are formed on the first conductivity type epitaxial layer 2; and the terminal regions of second conductivity type P region 501 overlap with the terminal regions of second conductivity type body region 301; wherein, the active region of second conductivity type P region 5 is located within the active region, the terminal regions of second conductivity type P region 501 are located within the terminal region, and the boundary regions of second conductivity type P region 502 are located at the boundary between the active region and the terminal region. Specifically, it includes: S41. Remove the silicon dioxide and hard mask polysilicon 14 formed in step S3, and then deposit a certain thickness of hard mask polysilicon 14 on the first conductivity type epitaxial layer 2. Remove the hard mask polysilicon 14 by photolithography, development, and etching to form the injection windows corresponding to the active region second conductivity type P region 5, the boundary region second conductivity type P region 502, and the terminal region second conductivity type P region 501; the photoresist thickness during the photolithography process is not less than 0.9um; S42. Implanting second conductivity type ions onto the first conductivity type epitaxial layer through the implantation window; the second conductivity type ions are Al ions, and the second conductivity type ion implantation is formed by multiple implantations, with an implantation energy of 50 KeV-1000 KeV and a doping dose of 1e11-5e15 cm⁻¹. 2 .
[0057] In this application, the injection windows of the second conductivity type P region 501 in the terminal region are distributed at equal intervals, and the size of each injection window is the same and adjustable. The number of injection windows is 9.
[0058] It should be noted that, in the first direction, that is, from the active region to the terminal region, the second conductivity type P region 501 of the terminal region is successively the first terminal region second conductivity type P region 501 to the ninth terminal region second conductivity type P region 501; then the positions of the second first terminal region second conductivity type P region 501 and the fourth first terminal region second conductivity type P region 501 overlap with the two terminal region second conductivity type body regions 301.
[0059] like Figure 2 As shown, the distance between the first terminal region, second conductivity type P region 501, and the boundary region, second conductivity type P region 502, is S1. The dimensions of the nine terminal regions, second conductivity type P regions 501, in the first direction are W1, W2, W3, W4, W5, W6, W7, W8, and W9, respectively. The distances between adjacent terminal regions, second conductivity type P regions 501, are S2, S3, S4, S5, S6, S7, S8, and S9, respectively. In this embodiment, dimensions S1-S9 are consistent, dimensions W1-W9 are consistent, and dimensions S1-S9 are smaller than dimensions W1-W9.
[0060] S5: As Figure 6 As shown, an active region of the first conductivity type JFET region 6 and two spaced-apart terminal regions of the first conductivity type JFET region 601 are formed on the first conductivity type epitaxial layer 2; wherein, the two terminal regions of the first conductivity type JFET region 601 overlap with the sixth terminal region of the second conductivity type P region 501 and the eighth terminal region of the second conductivity type P region 501, respectively; specifically including: S51: Remove the hard mask polysilicon 14 from step S4, and deposit the hard mask polysilicon 14 on the first conductivity type epitaxial layer 2. S52: Perform photolithography, development, and etching on the hard mask polysilicon 14 to form the injection windows of the active region first conductivity type JFET region 6 and the terminal region first conductivity type JFET region 601.
[0061] In this application, the first conductivity type JFET region 601 of the two terminal regions overlaps with the second conductivity type P region 501 of the sixth terminal region and the second conductivity type P region 501 of the eighth terminal region, respectively.
[0062] When designing the injection window, it is important to note that a corresponding cutoff ring 701 injection window should be set on the side of the termination region away from the active region. The cutoff ring 701 and the first conductivity type JFET region 601 of the termination region are injected and formed synchronously. The injection parameters and formation process of the two are the same. The cutoff ring 701 is located between the repeating termination device units and is used to achieve the separation between two adjacent repeating units.
[0063] S53: Implanting ions of the first conductivity type through the implantation window; wherein the first conductivity type ions are N ions, formed by multiple implantations, with an implantation energy of 30 KeV-1000 KeV and a doping dose of 1e11-5e15 cm⁻¹. 2 ; S54: High-temperature annealing is performed using a furnace tube process; the high-temperature annealing temperature is 1600℃-1800℃, and the annealing time is 10min-120min. High-temperature annealing can activate ions and repair lattice damage.
[0064] S6: Forming the source, drain, and gate on the epitaxial layer 2 of the first conductivity type; specifically including: S61: A gate oxide layer 7, a field oxide layer 9, and a gate polysilicon 8 are formed on the first conductivity type epitaxial layer 2. Specifically, the gate oxide layer 7 is formed by a thermal oxidation process. The thermal oxidation temperature is 1300℃-1500℃, and the thickness of the gate oxide layer 7 is 400A-550A.
[0065] A field oxide layer 9 of a certain thickness is deposited on the gate oxide layer 7; the field oxide layer 9 is etched by photolithography, development and etching processes, either by dry or wet methods; the thickness of the field oxide layer 9 is 10000A-40000A.
[0066] A layer of gate polysilicon 8 is deposited, and the gate polysilicon 8 is formed by photolithography, development and etching of polysilicon; the thickness of the gate polysilicon 8 is 3000A-6000A.
[0067] S62: An interlayer dielectric layer 10, a source metal 11, a passivation layer 12, and a polyimide (PI) layer 13 are deposited on the first conductivity type epitaxial layer 2. Specifically, this includes: An interlayer dielectric layer 10 of a certain thickness is deposited, and then gate contact holes and source contact holes are selectively etched; wherein, the thickness of the interlayer dielectric layer 10 is 10000A-15000A; An ohmic contact is formed using metallic Ni, followed by the deposition of source metal 11, passivation layer 12, and polyimide PI layer 13. In this application, the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.
[0068] S63: Metallization is performed on the back side of the first conductivity type substrate 1.
[0069] In this embodiment, there are two body regions 301 of the second conductivity type in the terminal region, nine P regions 501 of the second conductivity type in the terminal region, and two JFET regions 601 of the first conductivity type in the terminal region. The two body regions 301 of the second conductivity type in the terminal region overlap with the second and fourth P regions 501 of the second conductivity type in the terminal region, and the two JFET regions 601 of the first conductivity type in the terminal region overlap with the sixth and eighth JFET regions 601 of the first conductivity type in the terminal region. That is, one P region 501 of the second conductivity type in the terminal region is reserved on the left side of the terminal region, and one P region 501 of the second conductivity type in the terminal region is reserved on the right side of the terminal region. The two body regions 301 of the second conductivity type in the terminal region are separated by one P region 501 of the second conductivity type in the terminal region, and the two JFET regions 601 of the first conductivity type in the terminal region are separated by one P region 501 of the second conductivity type in the terminal region. This allows the breakdown potential to increase sequentially from left to right.
[0070] Figure 1 This is a schematic cross-sectional view of an existing planar gate SiC MOSFET termination structure. In the upper part of the epitaxial layer 2 of the first conductivity type in the termination region, there are n individual P-regions 501 of the second conductivity type in the termination region (n>1), but no JFET region 601 of the first conductivity type in the termination region and no body region 301 of the second conductivity type in the termination region. Depending on the breakdown voltage, the number and size of the P-regions 501 of the second conductivity type in the termination region will vary. For example, with a breakdown voltage greater than 800V, the termination region size in the prior art needs to be greater than 120µm.
[0071] like Figure 7 The embodiments of the present invention exhibit superior breakdown voltage performance compared to existing technologies, while still meeting device requirements. Figure 1 The size of the terminal region needs to be greater than 120um. However, this application optimizes the second conductivity type body region, the second conductivity type P region, and the first conductivity type JFET region within the terminal region, thereby reducing the overall size of the terminal region and ensuring that the size of the terminal region is less than or equal to 60um. Using the device structure of this application can reduce the terminal size, save the terminal region area, and improve the utilization rate of the device on the wafer.
[0072] It is understood that the above embodiments only illustrate preferred embodiments of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can freely combine the above technical features without departing from the concept of the present invention, and can also make several modifications and improvements, all of which fall within the protection scope of the present invention. Therefore, all equivalent transformations and modifications made with respect to the scope of the claims of the present invention should fall within the scope of the claims of the present invention.
Claims
1. A method for fabricating a SiC MOSFET termination structure, characterized in that, include: S1: An epitaxial layer of the first conductivity type is formed on a substrate of the first conductivity type; S2: An active region second conductivity type body region and at least two spaced-apart terminal regions second conductivity type body regions are formed on the first conductivity type epitaxial layer; S3: A first conductivity type source region is formed in the second conductivity type body region of the active region; S4: An active region of second conductivity type P, a boundary region of second conductivity type P, and M spaced-apart terminal regions of second conductivity type P are formed on the first conductivity type epitaxial layer; and the terminal regions of second conductivity type P overlap with the terminal regions of second conductivity type body regions; M is an integer greater than or equal to 4; S5: An active region of the first conductivity type JFET region and at least two spaced-apart terminal regions of the first conductivity type JFET region are formed on the first conductivity type epitaxial layer; the terminal region of the first conductivity type JFET region overlaps with the terminal region of the second conductivity type P region, and the terminal region of the first conductivity type JFET region is located on the side of the terminal region of the second conductivity type body region away from the active region; S6: The source, drain, and gate are formed on the epitaxial layer of the first conductivity type.
2. The method for fabricating a SiC MOSFET termination structure according to claim 1, characterized in that, At least one terminal region second conductivity type P region is provided between the terminal region second conductivity type body region and the boundary region second conductivity type P region; at least one terminal region second conductivity type P region is provided between two adjacent second conductivity type body regions.
3. The method for fabricating a SiC MOSFET termination structure according to claim 1, characterized in that, A cutoff ring is provided on the side of the terminal region away from the active region. At least one terminal region of the second conductivity type P is provided between the first conductivity type JFET region of the terminal region and the cutoff ring. At least one terminal region of the second conductivity type P is provided between two adjacent first conductivity type JFET regions.
4. The method for fabricating a SiC MOSFET termination structure according to claim 1, characterized in that, In the first direction, the distance between the M terminal regions of the second conductivity type P region is equal, and the size of the M terminal regions of the second conductivity type P region is equal in the first direction; the first direction refers to the direction from the active region to the terminal region.
5. The method for fabricating a SiC MOSFET termination structure according to claim 4, characterized in that, In the first direction, the distance between the first terminal region of the second conductivity type P region and the active region is equal to the distance between the M terminal regions of the second conductivity type P regions.
6. The method for fabricating a SiC MOSFET termination structure according to claim 1, characterized in that, Step S2 includes: Hard mask polysilicon is deposited on the epitaxial layer of the first conductivity type; The hard mask polysilicon is photolithographically etched, developed, and etched to form the injection windows of the active region second conductivity type body region and the terminal region second conductivity type body region; Ions of the second conductivity type are injected through the injection window.
7. The method for fabricating a SiC MOSFET termination structure according to claim 6, characterized in that, Step S3 includes: A layer of silicon dioxide is deposited on the surface of the polycrystalline silicon of the hard mask. Photolithography, development, and etching are performed on silicon dioxide to form an injection window for the first conductivity type source region located between the polysilicon in the hard mask. Ions of the first conductivity type are injected through the injection window.
8. The method for fabricating a SiC MOSFET termination structure according to claim 1, characterized in that, Step S5 includes: Hard mask polysilicon is deposited on the epitaxial layer of the first conductivity type; The hard mask polysilicon is photolithographically lithographically etched, developed, and etched to form the injection windows of the active region first conductivity type JFET region and the terminal region first conductivity type JFET region; Ions of the first conductivity type are injected through the injection window; High-temperature annealing is performed using a furnace tube process; the high-temperature annealing temperature is 1600℃-1800℃, and the high-temperature annealing time is 10min-120min.
9. The method for fabricating a SiC MOSFET termination structure according to claim 1, characterized in that, Step S6 includes: A gate oxide layer, a field oxide layer, and a gate polysilicon layer are formed on the epitaxial layer of the first conductivity type. An interlayer dielectric layer, a source metal, a passivation layer, and a polyimide (PI) layer are deposited on the first conductivity type epitaxial layer.
10. A SiC MOSFET termination structure, characterized in that, It is prepared based on the method for preparing a SiCMOSFET termination structure according to any one of claims 1-9.