Method of manufacturing trench power device and device
By using segmented growth of polycrystalline silicon and oxygen-containing gas to block grain growth, the problems of increased gate resistance and wafer warpage in trench power devices have been solved, achieving trench power devices with low resistivity and high manufacturing yield.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2026-03-02
- Publication Date
- 2026-07-10
AI Technical Summary
As the pitch of trench power devices shrinks, the gate resistance and power consumption increase due to the compression of the trench filling space, as well as the wafer stress accumulation and warping problems caused by coarse grains and poor uniformity during polysilicon growth.
A segmented growth process is used to grow polycrystalline silicon within the same process formulation. Oxygen-containing gas is introduced between two adjacent growth processes to block grain growth, forming fine and uniform polycrystalline silicon grains and avoiding the formation of silicon dioxide interlayers. The gate is formed by combining dry etch-back and chemical mechanical polishing processes.
It significantly reduces the resistivity of polysilicon, optimizes the dynamic power consumption characteristics of devices, improves wafer warpage, and enhances manufacturing yield and electrical reliability.
Smart Images
Figure CN122373431A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a method and device for manufacturing a trench-type power device. Background Technology
[0002] In the manufacturing process of trench power devices, polysilicon is typically used as the gate material. With the continuous iteration and upgrading of semiconductor technology, the device pitch is constantly shrinking, leading to a gradual reduction in the critical size of the trench, which greatly compresses the filling space of the gate polysilicon.
[0003] The compression of the fill space directly leads to an increase in gate resistance, resulting in a significant increase in dynamic power consumption of the device. Many factors affect gate resistance, with the resistivity of the polysilicon material itself being a key factor. Studies have shown that, given a specific design and doping concentration, the grain size and uniformity of the polysilicon have a significant impact on resistivity. Generally, a uniform and smaller grain size can effectively reduce the resistivity of polysilicon.
[0004] Traditional processes typically employ a single, continuous growth method to fill polysilicon, which often results in continuously increasing grain size and uneven size distribution during growth, making it difficult to meet the low gate resistance requirements of high-performance power devices. Furthermore, large-grain polysilicon can generate significant wafer stress in subsequent processes, leading to wafer warping.
[0005] Therefore, how to obtain polycrystalline silicon gates with fine and uniform grains to reduce gate resistance has become a pressing technical problem that needs to be solved. Summary of the Invention
[0006] The technical problems to be solved by this invention are the increase in gate resistance and power consumption caused by the compression of trench filling space as the pitch of trench power devices shrinks, and the problems of wafer stress accumulation and warping caused by coarse grains and poor uniformity during polysilicon growth.
[0007] This invention provides a method for manufacturing a trench-type power device, comprising:
[0008] Step 1: Grow a gate dielectric layer within the formed trench;
[0009] Step 2: Polycrystalline silicon is grown in the trench and on the substrate surface. The growth of polycrystalline silicon is carried out in multiple segments within the same process formula. Oxygen-containing gas is introduced between two adjacent polycrystalline silicon growth processes to block the growth process of polycrystalline silicon grains and to prevent the formation of silicon dioxide interlayers between polycrystalline silicon layers.
[0010] Step 3: Remove excess polysilicon from the substrate surface to form the gate of the trench power device.
[0011] Preferably, in step two, the number of segments in the polycrystalline silicon growth is two or more.
[0012] Preferably, in step two, the polycrystalline silicon growth is performed using either chemical vapor deposition or atomic layer deposition.
[0013] Preferably, in step two, the chemical vapor deposition process includes any one of low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, rapid thermal chemical vapor deposition, or atmospheric pressure chemical vapor deposition.
[0014] Preferably, in step two, the oxygen-containing gas includes one or more of oxygen, nitrous oxide, nitrogen monoxide, or ozone.
[0015] Preferably, in step two, the oxygen-containing gas is introduced for 1-5 minutes, and the gas flow rate is 0.5-3 sccm.
[0016] Preferably, in step three, excess polysilicon is removed by a dry etch-back process and / or a chemical mechanical polishing process.
[0017] Preferably, in step one, the gate dielectric layer comprises silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric material, or a combination thereof.
[0018] The present invention also provides a trench power device, wherein the gate is formed by any of the above manufacturing methods, and the gate is composed of multi-segment grown polycrystalline silicon.
[0019] As described above, the manufacturing method and device of the trench-type power device of the present invention have the following beneficial effects:
[0020] This invention achieves precise control over grain size without introducing a silicon dioxide insulating layer by employing a segmented growth process within the same process formulation and utilizing oxygen-containing gas to interrupt the continuous growth of polycrystalline silicon grains. This method significantly refines polycrystalline silicon grains and improves their morphological uniformity, thereby substantially reducing the bulk resistivity of polycrystalline silicon, decreasing gate resistance, and optimizing the dynamic power consumption characteristics of the device. Simultaneously, the improved microstructure helps balance and release thermal stress during deposition, significantly improving wafer warpage and extending the processing window for subsequent photolithography and planarization processes. Furthermore, this process is completed within a single process formulation, requiring no additional manufacturing steps or equipment investment, effectively improving device performance and manufacturing yield while maintaining low production costs. Attached Figure Description
[0021] Figure 1 This is a schematic diagram of a manufacturing process for a trench-type power device;
[0022] Figure 2 The diagram shows a cross-sectional structure of a trench-type power device. Detailed Implementation
[0023] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0024] Please see Figure 1 and Figure 2 , Figure 1 The basic process flow of a trench power device manufacturing method is shown. Figure 2 The cross-sectional structure of the trench-type power device manufactured using this process is shown during the deposition stage.
[0025] This manufacturing method includes:
[0026] Before performing step one, a trench is first formed on substrate 101. Substrate 101 may include single-crystal silicon, epitaxial silicon, silicon carbide, gallium nitride, or silicon-on-insulator. Substrate 101 has a first surface and a second surface opposite to the first surface. The specific process for forming the trench may include depositing a hard mask layer on the first surface of substrate 101 using a chemical vapor deposition process, and then removing part of the hard mask layer and substrate 101 material downwards using a photolithography process and anisotropic etching process, thereby forming an opening with a predetermined aspect ratio within substrate 101. The etching process may include reactive ion etching (RIE) or inductively coupled plasma etching (ICP). By adjusting the pressure, power, and bias voltage of the etching gas, it is possible to ensure that the trench sidewall morphology is flat and controlled.
[0027] Step 1: Grow a gate dielectric layer 102 within the formed trench.
[0028] In some embodiments, in step one, the gate dielectric layer 102 comprises silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material, or a combination thereof. Specifically, the gate dielectric layer 102 is formed on the sidewalls, bottom, and top surface of the substrate 101 by deposition or thermal growth processes. If a high-k dielectric material is used, hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), or hafnium silicon oxide (HfSiOx) can be selected. These materials can be used to form thin films with excellent step coverage using atomic layer deposition (ALD) processes. By introducing a high-k dielectric, its higher electrical constant can be used to increase the gate coupling capability of the device, while reducing the physical leakage current with the same equivalent oxide layer thickness. The formation of the gate dielectric layer 102 provides an electrically insulating basis and a reliable nucleation interface for subsequent polysilicon deposition.
[0029] Step 2: Polycrystalline silicon is grown in the trench and on the surface of substrate 101. The growth of polycrystalline silicon is carried out in multiple segments within the same process formula. Oxygen-containing gas is introduced between two adjacent polycrystalline silicon growth segments to block the growth process of polycrystalline silicon grains and to prevent the formation of silicon dioxide interlayers between polycrystalline silicon layers.
[0030] In some embodiments, in step two, the number of segments in the polycrystalline silicon growth is two or more. For example... Figure 2 As shown, polysilicon growth begins with the formation of a first polysilicon segment 103 on the gate dielectric layer 102. Subsequently, after an oxygen-containing gas pulse is introduced, a second polysilicon segment 104 is formed on the first polysilicon segment 103. In other examples, this deposition cycle can be repeated multiple times to form more polysilicon segments. By dividing the originally continuously grown thickness into multiple segments, the grain growth of each segment is intervened by subsequent nucleation processes before reaching the set thickness. This segmented growth strategy results in the polysilicon within the entire trench being composed of a series of small, discontinuously grown grains. Segmented growth achieved within a single process formulation through automated gas switching allows for proactive control of grain size without adding additional process steps or hardware costs.
[0031] In some embodiments, in step two, polycrystalline silicon growth employs either chemical vapor deposition (CVD) or atomic layer deposition (ALD). Within a deposition apparatus such as a reduced-pressure CVD furnace, the substrate 101 is heated to decompose the reaction precursor. The precursor gas can be silane (SiH4), dichlorosilane (Si2H6), dichlorosilane, or trichlorosilane. Using a segmented process allows for multiple reconfigurations of the chemical environment of the reaction chamber during deposition, increasing the adsorption probability of reactants on the sidewalls of the deep trenches, thereby obtaining a polycrystalline silicon film with excellent filling performance and no internal gaps.
[0032] In some embodiments, step two involves a chemical vapor deposition process including low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), rapid thermal chemical vapor deposition (RTCVD), or atmospheric pressure chemical vapor deposition (APCVD). A suitable deposition mode can be selected based on the device's thermal budget requirements. For example, rapid RCVD can shorten the exposure time of polysilicon at high temperatures, while LCVD increases the mean free path of gas molecules by reducing operating pressure, ensuring shape preservation and growth within complex trench structures.
[0033] In some embodiments, in step two, the oxygen-containing gas includes one or more of oxygen, nitrous oxide, nitric oxide, or ozone, preferably oxygen. These oxygen-containing gases, acting as surface modifiers, enter the reaction chamber between adjacent deposition sub-stages. This in-situ treatment process can alter the surface state in real time, thereby effectively intervening in the subsequent microscopic evolution of the thin film.
[0034] In some online embodiments, in step two, the introduction of oxygen-containing gas is controlled for a short time and the flow rate of the oxygen-containing gas is controlled for a small flow rate. The short time can be a preset duration, and the small flow rate can be set to a preset flow rate standard. For example, the introduction time of the oxygen-containing gas is 1-5 minutes, and the gas flow rate is 0.5-3 sccm. The purpose of introducing oxygen-containing gas is to form a discontinuous cluster of oxygen atoms adsorbed on the polycrystalline silicon surface after the previous deposition stage. Due to the extremely short introduction time and small flow rate, this sub-monolayer oxygen atom coverage is sufficient to disrupt the long-range order of the lattice and force subsequently grown silicon atoms to seek new nucleation centers by occupying the active growth sites of silicon atoms, thereby effectively suppressing grain coarsening. This mechanism ensures that the grains inside both polycrystalline silicon 103 and polycrystalline silicon 104 remain within a uniform and fine size range. Because the oxygen atom coverage is insufficient to establish a complete chemical bond network, no electrically insulating silicon dioxide physical barrier is formed at the interface between polysilicon 103 and polysilicon 104, ensuring that the gate polysilicon still has a good electrical path in the vertical direction. Experimental data show that this controlled oxidation pulse mechanism can reduce the resistivity of polysilicon, thereby optimizing the gate resistance and reducing device switching losses.
[0035] In some embodiments, in addition to the segmented deposition described above, an in-situ doping process can also be performed. During polysilicon deposition, a doping precursor gas, such as phosphine containing phosphorus or diborane containing boron, is introduced to achieve a predetermined doping concentration in polysilicon 103 and polysilicon 104. This in-situ doping layered deposition method ensures excellent electrical pathway distribution in the conductive material deep within the trenches. Furthermore, by refining the grain size and introducing multi-segment interfaces, internal stress accumulated during the deposition process and cooling can be effectively absorbed and released. This stress buffering mechanism significantly improves the warpage of substrate 101 after the process, enhancing the alignment accuracy and yield of subsequent chemical mechanical polishing and photolithography processes.
[0036] Step 3: Remove excess polysilicon from the surface of substrate 101 to form the gate of the trench power device.
[0037] In some embodiments, in step three, excess polysilicon is removed using a dry etching-back process and / or a chemical mechanical polishing (CMP) process. For example, a fluorine-based plasma dry etching process can be used to quickly remove the polysilicon portion originally deposited on the top surface of substrate 101. Subsequently, a chemical mechanical polishing (CMP) process is used for surface planarization. The polishing slurry, through the synergistic effect of chemical oxidation and mechanical grinding, completely removes the polysilicon outside the trench and trims the polysilicon height inside the trench to be flush with the top surface of the trench. This combined process can eliminate the loading effect caused by the difference in etching rate, resulting in a gate structure with a smooth morphology and no residue.
[0038] A trench-type power device, characterized in that the gate of the trench-type power device is formed by any of the manufacturing methods described above. The gate is composed of multi-segment grown polycrystalline silicon.
[0039] By employing the segmented growth and in-situ oxygen atom blocking techniques described above, the gate material remaining within the trench exhibits a fine and highly uniform grain morphology. Due to the controlled grain size, the polysilicon displays a stable electrical response. This process not only effectively reduces gate resistance and optimizes the dynamic power consumption characteristics of the device, but also enhances the electrical reliability and lifetime stability of the gate structure under high-frequency operating loads due to the improved microstructure.
[0040] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0041] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for manufacturing a trench-type power device, characterized in that, At least including: Step 1: Grow a gate dielectric layer within the formed trench; Step 2: Polycrystalline silicon is grown in the trench and on the substrate surface. The growth of polycrystalline silicon is carried out in multiple segments within the same process formula. Oxygen-containing gas is introduced between two adjacent polycrystalline silicon growth processes to block the growth process of polycrystalline silicon grains and to prevent the formation of silicon dioxide interlayers between polycrystalline silicon layers. Step 3: Remove excess polysilicon from the substrate surface to form the gate of the trench power device.
2. The method for manufacturing a trench-type power device according to claim 1, characterized in that: In step two, the polycrystalline silicon growth is divided into two or more segments.
3. The method for manufacturing a trench-type power device according to claim 1, characterized in that: In step two, polycrystalline silicon growth is performed using either chemical vapor deposition or atomic layer deposition.
4. The method for manufacturing a trench-type power device according to claim 3, characterized in that: In step two, the chemical vapor deposition process includes any one of low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, rapid thermal chemical vapor deposition, or atmospheric pressure chemical vapor deposition.
5. The method for manufacturing a trench-type power device according to claim 1, characterized in that: In step two, the oxygen-containing gas includes one or more of oxygen, nitrous oxide, nitrogen monoxide, or ozone.
6. The method for manufacturing a trench-type power device according to claim 1, characterized in that: In step two, the oxygen-containing gas is introduced for 1-5 minutes, and the gas flow rate is 0.5-3 sccm.
7. The method for manufacturing a trench-type power device according to claim 1, characterized in that: In step three, excess polysilicon is removed by dry etch-back process and / or chemical mechanical polishing process.
8. The method for manufacturing a trench-type power device according to claim 1, characterized in that: In step one, the gate dielectric layer comprises silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric material, or a combination thereof.
9. A trench-type power device, characterized in that, The gate of the trench power device is formed by the manufacturing method of any one of claims 1 to 8, wherein the gate is composed of multi-segment grown polycrystalline silicon.