Semiconductor device
By designing wavy metal electrode layers or raised/recessed structures in semiconductor devices, the problem of passivation layer cracking caused by inconsistent thermal expansion coefficients has been solved, improving device performance and reliability, and expanding the range of material choices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HUNAN SANAN SEMICON CO LTD
- Filing Date
- 2024-12-30
- Publication Date
- 2026-07-10
AI Technical Summary
In semiconductor devices, the inconsistency in the thermal expansion coefficients of the metal and the passivation layer leads to a risk of cracking in the passivation layer, affecting device performance and reliability.
The peripheral surface of the metal electrode layer is designed to be wavy or to form multiple protrusions and depressions to increase the boundary area, expand the space for thermal expansion, and reduce the risk of passivation layer cracking caused by differences in thermal expansion coefficients.
It effectively reduces the risk of passivation layer cracking, improves device performance and reliability, and expands the range of material choices to accommodate differences in thermal expansion coefficients.
Smart Images
Figure CN122373437A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of electronic device technology, and more particularly to a semiconductor device. Background Technology
[0002] In semiconductor devices, such as power devices, the thermal expansion of the passivation layer dielectric and the metal has a significant impact on device performance and reliability. This is particularly true in silicon carbide materials, where the difference in thermal expansion coefficients between the metal (e.g., aluminum) and the passivation layer can lead to thermal stress within the passivation layer, increasing the risk of cracking and severely affecting device performance and reliability. Therefore, effectively reducing the risk of passivation layer cracking is a pressing technical problem that needs to be solved. Summary of the Invention
[0003] In view of this, embodiments of the present invention provide a semiconductor device to improve device performance and reliability by reducing the risk of passivation layer cracking.
[0004] On one hand, an embodiment of the present invention provides a semiconductor device, which includes, for example, a semiconductor substrate, a metal electrode layer, and an inorganic passivation layer. The metal electrode layer is disposed on the semiconductor substrate and forms an electrical contact with the semiconductor substrate. The peripheral surface of the metal electrode layer has a plurality of protrusions and recesses located between each pair of adjacent protrusions. The inorganic passivation layer is disposed on the semiconductor substrate, covering the plurality of protrusions and the recesses of the metal electrode layer, and partially exposing the upper surface of the metal electrode layer opposite to the semiconductor substrate.
[0005] On the other hand, another embodiment of the present invention provides a semiconductor device, for example including: a semiconductor substrate, a metal electrode layer, and an inorganic passivation layer. The metal electrode layer is disposed on the semiconductor substrate and forms an electrical contact with the semiconductor substrate. The inorganic passivation layer is disposed on the semiconductor substrate, covering the metal electrode layer and partially exposing it. The metal electrode layer has a lower surface facing the semiconductor substrate, an upper surface facing away from the semiconductor substrate, and a peripheral side surface connecting the lower surface and the upper surface, the peripheral side surface being a wavy surface extending circumferentially on the metal electrode layer.
[0006] The above embodiments of the present invention can have the following beneficial effects: By designing the boundary between the metal electrode layer and the inorganic passivation layer, such as the peripheral surface of the metal electrode layer, as a wavy surface (or wavy boundary), for example, forming multiple protrusions and depressions between each pair of adjacent protrusions, the boundary area of the metal electrode layer can be increased, expanding the thermal expansion space of the metal electrode layer. This effectively reduces the risk of cracking of the inorganic passivation layer caused by the difference in thermal expansion coefficients between the metal peripheral surface and the inorganic passivation layer, thereby improving the performance and reliability of the device. Furthermore, it also helps to expand the range of choices for matching the thermal expansion coefficients of the metal and inorganic passivation layer materials. Attached Figure Description
[0007] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
[0008] Figure 1A This is a partial structural cross-sectional schematic diagram of a semiconductor device provided in an embodiment of the present invention.
[0009] Figure 1B for Figure 1A A top view of the semiconductor device shown.
[0010] Figure 2 This is a partial cross-sectional view of the semiconductor substrate in a method for fabricating a semiconductor device according to an embodiment of the present invention.
[0011] Figure 3 In order to be in Figure 2 The diagram shows a partial cross-sectional view of the semiconductor substrate after a field oxide layer has been formed.
[0012] Figure 4 In order to be in Figure 3 The diagram shows a partial cross-sectional view of the structure after a metal material layer is formed on the semiconductor substrate and the field oxide layer.
[0013] Figure 5A To Figure 4 The diagram shows a partial cross-sectional view of the metal electrode layer after the metal material layer is patterned to form a metal electrode layer.
[0014] Figure 5B To remove Figure 4 The top view of the structure behind the mask layer is shown.
[0015] Figure 6 This is a partial structural cross-sectional schematic diagram of another semiconductor device provided in an embodiment of the present invention.
[0016] Figure 7 This is a partial structural cross-sectional schematic diagram of another semiconductor device provided in an embodiment of the present invention.
[0017] [Explanation of Key Figure Markings]
[0018] 10. Semiconductor device; 11. Semiconductor substrate; 110. Silicon carbide substrate; 112. Silicon carbide epitaxial layer; 13. Field oxide layer; 15. Metal electrode layer; 15T. Upper surface; 15B. Lower surface; 15S. Peripheral side surface; 17. Inorganic passivation layer; 18. Organic protective layer; 19. Second electrode layer; AA. Active region; TA. Peripheral region; M1, M2. Mask layer; CH. Contact hole; 150. Metal material layer; d. Diameter; 152. Protrusion; 154. Recess. Detailed Implementation
[0019] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0020] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.
[0021] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0022] It should also be noted that the division of multiple embodiments in this invention is only for the convenience of description and should not constitute a special limitation. Features in various embodiments can be combined and referenced in each other without contradiction.
[0023] See Figure 1A , Figure 1B and Figure 5BAn embodiment of the present invention provides a semiconductor device 10, comprising: a semiconductor substrate 11, a metal electrode layer 15, and an inorganic passivation layer 17. The metal electrode layer 15 is disposed on the semiconductor substrate 11 and forms an electrical contact with the semiconductor substrate 11, such as a Schottky contact or an ohmic contact. The peripheral sidewalls (or peripheral sidewalls) 15S of the metal electrode layer 15 have a plurality of protrusions 152 and recesses 154 located between each pair of adjacent protrusions 152. The inorganic passivation layer 17 is disposed on the semiconductor substrate 11, covering the plurality of protrusions 152 and the recesses 154 of the metal electrode layer 15, and partially exposing the upper surface 15T of the metal electrode layer 15 facing away from the semiconductor substrate 11.
[0024] This embodiment increases the boundary area of the metal electrode layer 15 by forming multiple protrusions 152 and recesses 154 between each pair of adjacent protrusions 152 on the peripheral side surface 15S of the metal electrode layer 15, thereby expanding the thermal expansion space of the metal electrode layer 15. This effectively reduces the risk of passivation layer cracking caused by the difference in thermal expansion coefficients between the metal and the inorganic passivation layer 17, thus improving the performance and reliability of the device. Furthermore, it also helps to expand the range of choices for the thermal expansion coefficients of the metal and inorganic passivation layer materials. For example, the metal electrode layer 15 can be made of metal materials such as Al, AlCu, and AlSiCu, which have different thermal expansion coefficients. The inorganic passivation layer 17 can be made of inorganic dielectric materials such as SiO2, SiN, and SiON, which also have different thermal expansion coefficients. By adopting this structural design of the metal electrode layer 15 of this embodiment, the metal and inorganic dielectric materials with the largest difference in thermal expansion coefficients can be selected for combination as the materials of the metal electrode layer 15 and the inorganic passivation layer 17, respectively. Furthermore, it is understood that the boundary of the inorganic passivation layer 17 contacting the metal electrode layer 15 will correspondingly form a recess and a protrusion that are mutually compatible with the protrusion 152 and the recess 154.
[0025] In some embodiments, see Figure 1A and Figure 1BThe semiconductor device 10 further includes, for example, a field oxide layer 13. The field oxide layer 13 is disposed on the semiconductor substrate 11 and forms contact holes CH to expose a portion of the semiconductor substrate 11. A metal electrode layer 15 fills the contact holes CH to form an electrical contact with the semiconductor substrate 11 and extends toward the field oxide layer 13 to partially overlap with it. The inorganic passivation layer 17 is located on the side of the field oxide layer 13 facing away from the semiconductor substrate 11. In this embodiment, because the metal electrode layer 15 partially overlaps with the field oxide layer 13, the peripheral side surface 15S of the metal electrode layer 15 is located on the side of the field oxide layer 13 facing away from the semiconductor substrate 11. Thus, during the etching process, such as wet etching, to form the protrusions 152 and recesses 154 on the peripheral side surface 15S, the presence of the field oxide layer 13 protects the upper surface of the semiconductor substrate 11 from damage. Additionally, for example, the field oxide layer 13 may be a thermal oxide layer, a CVD-deposited oxide layer, or a multilayer stacked structure of thermal oxide layer and CVD-deposited oxide layer, with a thickness in the range of 0.5μm-1μm, such as 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm or 1μm, and its material may be silicon oxide.
[0026] In some embodiments, see Figure 1A and Figure 1B The semiconductor substrate 11, for example, has an active region AA and a peripheral region TA surrounding the active region AA. In terms of layer structure, the semiconductor substrate 11 includes, for example, a silicon carbide substrate 110 and a silicon carbide epitaxial layer 112, the silicon carbide epitaxial layer 112 being located on the side of the silicon carbide substrate 110 facing the metal electrode layer 15. The silicon carbide substrate 110 has a crystal form, for example, 4H SiC or 6H SiC, and the doping concentration range of the silicon carbide substrate 110 is, for example, 1E19-5E20 / cm³. 3 The thickness of the silicon carbide epitaxial layer 112 ranges, for example, from 1 μm to 100 μm, and the doping concentration ranges, for example, from 1E14 to 5E16 / cm. 3 That is, the doping concentration of the silicon carbide substrate 110 is greater than the doping concentration of the silicon carbide epitaxial layer 112. Furthermore, both the active region AA and the peripheral region TA have, for example, ion-implanted regions, and these ion-implanted regions can have the same conductivity type (e.g., p-type, which can be p...). + And the conductivity type of the silicon carbide substrate 110 and the silicon carbide epitaxial layer 112 (e.g., n-type, which can be n respectively) + n -The field oxide layer 13 has contact holes CH that expose the active region AA. The metal electrode layer 15 is disposed in the active region AA to form an electrical contact with the semiconductor substrate 11 and extends from the active region AA toward the peripheral region TA. The overlap length between the metal electrode layer 15 and the field oxide layer 13 is, for example, greater than 0 μm and less than or equal to 50 μm, and the thickness of the metal electrode layer 15 is, for example, 3 μm-6 μm, such as 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, 5.5 μm or 6 μm. As an example, the metal electrode layer 17 includes, but is not limited to, any one or more metal combinations such as aluminum (Al), silver (Ag), and copper (Cu), and metal solid solutions formed by any one or more metals such as Al, Ag, and Cu with elements such as nitrogen (N) and silicon (Si); the metal electrode layer 17 can be a single-layer metal structure or a multi-layer metal structure. The inorganic passivation layer 17 can be deposited using any one or more dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride. For example, the thickness of the inorganic passivation layer 17 is in the range of 0.3μm-2μm, such as 0.3μm, 0.5μm, 0.7μm, 0.9μm, 1μm, 1.5μm, 1.8μm, or 2μm.
[0027] In some embodiments, see Figure 5B Each protrusion 152 is, for example, an arc-shaped protrusion, distributed circumferentially along the metal electrode layer 15, for example, on all four sides of the metal electrode layer 15. Of course, it is understood that these arc-shaped protrusions may also be distributed only on two or three opposite sides of the metal electrode layer 15, or even on a single side of the metal electrode layer 15. In this embodiment, each protrusion 152 is an arc-shaped protrusion. The arc design allows for a smooth transition of stress at the edges, resulting in a more uniform stress distribution at the edges of the arc, without significant stress concentration, thus reducing local stress concentration. Furthermore, in other embodiments, each protrusion 152 may also be a polygonal protrusion, such as a triangular protrusion or a trapezoidal protrusion.
[0028] In some embodiments, see Figure 5B Each protrusion 152 is, for example, an arc-shaped protrusion with a diameter d greater than 4 micrometers, such as 4.5μm, 5μm, 5.5μm, 6μm, 6.5μm, 7μm, 8μm, 9μm, or 10μm. Furthermore, the recess 154 between two adjacent protrusions 152 can also be an arc-shaped recess with a diameter greater than 4 micrometers. In this embodiment, the edge stress distribution of the arc-shaped protrusions is more uniform, which can effectively reduce the concentration of local stress. It is also worth mentioning that each protrusion 152 is not limited to an arc-shaped protrusion; it can also be other arc-shaped protrusions.
[0029] In some embodiments, see Figure 1A , Figure 1B and Figure 5B The metal electrode layer 15 has a lower surface 15B facing the semiconductor substrate 11, and a peripheral side surface 15S connecting the upper surface 15T and the lower surface 15B. Each protrusion 152 extends from the lower surface 15B to the upper surface 15T on the peripheral side surface 15S. In other words, each protrusion 152 may be a columnar protrusion extending from the lower surface 15B to the upper surface 15T, such as a semi-cylindrical protrusion or a prismatic protrusion.
[0030] In some embodiments, see Figure 1A and Figure 6 The semiconductor device 10 further includes, for example, an organic protective layer 18 disposed on the semiconductor substrate 11, wherein the organic protective layer 18 covers the inorganic passivation layer 17 and partially exposes the upper surface 15T of the metal electrode layer 15. The material of the protective layer 19 is, for example, an organic material such as polyimide, but this embodiment of the invention is not limited thereto. As an example, the thickness of the organic protective layer 18 is, for example, 5 μm-10 μm.
[0031] In some embodiments, see Figure 6 The semiconductor device 10 further includes, for example, a second electrode layer 19, which is disposed on the side of the semiconductor substrate 11 opposite to the metal electrode layer 15 and forms an electrical contact, such as an ohmic contact, with the semiconductor substrate 11. For example, the second electrode layer 19 is formed by vapor deposition of Ti / Ni / Ag, and has a thickness of, for example, 2 μm, but the embodiments of the present invention are not limited thereto.
[0032] To facilitate a clearer understanding of the semiconductor device 10 in this embodiment, the following will be combined with... Figures 1A to 6 A method for manufacturing the semiconductor device 10 is described.
[0033] First, after cleaning and polishing the n-type silicon carbide substrate 110, an n-type silicon carbide epitaxial layer 112 is grown on the silicon carbide substrate 110 using MOCVD. The thickness of the epitaxial layer 112 is, for example, 1 μm-100 μm, and the doping concentration is, for example, 1E14-5E16 / cm. 3 And then polish and grind to obtain such Figure 2 The semiconductor substrate 11 shown.
[0034] Next, a silicon oxide layer with a thickness of, for example, 0.5 μm-1 μm is deposited on the silicon carbide epitaxial layer 112. Photoresist is then spin-coated and patterned on the deposited silicon oxide surface to obtain a mask layer M1. Then, etching, for example wet etching, is used to open the deposited silicon oxide to form contact holes CH, exposing a portion of the silicon carbide epitaxial layer 112, and obtaining… Figure 3 The field oxygen layer 13 shown is wet etching under the following conditions: temperature 20℃-40℃, time 20 minutes-60 minutes.
[0035] After forming the field oxide layer 13, the mask layer M1 is removed, and a metal material layer 150 with a thickness of, for example, 3 μm-6 μm is deposited on the semiconductor substrate 11. The metal material layer 150 fills the contact hole CH and extends to cover the field oxide layer 13. Figure 4 As shown.
[0036] Then, photoresist is spin-coated onto the metal material layer 150, and the spin-coated photoresist is patterned using photolithography to obtain a mask layer M2. Subsequently, dry etching is used to transfer the morphology of the mask layer M2 onto the metal material layer 150 to obtain the metal electrode layer 15, as shown below. Figure 5A As shown in the figure. After removing the mask layer M2, the result is as shown in the figure. Figure 5B The structure shown. Through the analysis of... Figure 5B Annealing the structure shown allows the metal electrode layer 15 to form an electrical contact, such as a Schottky contact, with the silicon carbide epitaxial layer 112 of the semiconductor substrate 11.
[0037] After the metal electrode layer 15 is fabricated, a silicon oxide layer and a silicon nitride layer are deposited sequentially, with thicknesses of, for example, 0.3 μm-2 μm; then, the deposited silicon oxide and silicon nitride layers are dry etched to obtain... Figure 1A and Figure 1B The inorganic passivation layer 17 is shown.
[0038] Furthermore, an organic protective layer 18 with a thickness of, for example, 5 μm-10 μm can be formed by spin-coating polyimide and then exposing and baking it. Figure 6 As shown. Alternatively, a 2μm thick Ti / Ni / Ag layer can be deposited on the side of the silicon carbide substrate 110 facing away from the silicon carbide epitaxial layer 112, as... Figure 6 The second electrode layer 19 is shown.
[0039] In some embodiments, see Figure 7The semiconductor device 10 may also omit the field oxide layer 13. The metal electrode layer 15 is disposed on the semiconductor substrate 11 and forms an electrical contact with the semiconductor substrate 11, such as a Schottky contact or an ohmic contact. The peripheral side surface 15S of the metal electrode layer 15 also has a plurality of protrusions 152 and a recess 154 located between each two adjacent protrusions 152 (see reference). Figure 5B The inorganic passivation layer 17 is disposed on the semiconductor substrate 11, covering the plurality of protrusions 152 and the recesses 154 of the metal electrode layer 15, and partially exposing the upper surface 15T of the metal electrode layer 15 away from the semiconductor substrate 11.
[0040] Please see again. Figure 1A , Figure 1B and Figure 5B Another embodiment of the present invention provides a semiconductor device 10, which includes, for example, a semiconductor substrate 11, a metal electrode layer 15, and an inorganic passivation layer 17. The metal electrode layer 15 is disposed on the semiconductor substrate 11 and forms an electrical contact with the semiconductor substrate 11. The inorganic passivation layer 17 is disposed on the semiconductor substrate 11, covering the metal electrode layer 15 and partially exposing the metal electrode layer 15. The metal electrode layer 15 has a lower surface 15B facing the semiconductor substrate 11, an upper surface 15T facing away from the semiconductor substrate 11, and a peripheral side surface 15S connecting the lower surface 15B and the upper surface 15T. The peripheral side surface 15S is a wavy surface extending circumferentially on the metal electrode layer 15. In this embodiment, the peripheral surface 15S of the metal electrode layer 15 is designed as a wavy surface, creating a wavy boundary between the inorganic passivation layer 17 and the metal electrode layer 15. This increases the boundary area of the metal electrode layer 15 and expands its thermal expansion space, effectively reducing the risk of passivation layer cracking caused by the difference in thermal expansion coefficients between the metal and the inorganic passivation layer 17, thereby improving device performance and reliability. Furthermore, it also helps to broaden the range of suitable thermal expansion coefficients for the metal and inorganic passivation layer materials. For example, the metal electrode layer 15 can be made of metals such as Al, AlCu, and AlSiCu, which have different thermal expansion coefficients. The inorganic passivation layer 17 can be made of inorganic dielectric materials such as SiO2, SiN, and SiON, which also have different thermal expansion coefficients. By adopting this structural design of the metal electrode layer 15 in this embodiment, the metal and inorganic dielectric materials with the largest difference in thermal expansion coefficients can be selected for combination as the materials for the metal electrode layer 15 and the inorganic passivation layer 17, respectively.
[0041] As stated above, in some embodiments, see Figure 5BThe wavy surface may be located on all four sides of the metal electrode layer 15, but the embodiments of the present invention are not limited to this order. It may also be located only on two or three opposite sides of the metal electrode layer 15, or even only on one side of the metal electrode layer 15.
[0042] In some embodiments, see Figure 1A , Figure 1B and Figure 5B The semiconductor device 10 further includes, for example, a field oxide layer 13 disposed on the semiconductor substrate 11 and forming contact holes CH to expose a portion of the semiconductor substrate 11. The metal electrode layer 15 fills the contact holes CH to form an electrical contact with the semiconductor substrate 11 and extends toward the field oxide layer 13 to partially overlap it. The inorganic passivation layer 17 is located on the side of the field oxide layer 13 facing away from the semiconductor substrate 11, and the wavy surface is located on the side of the field oxide layer 13 facing away from the semiconductor substrate 11 and is covered by the inorganic passivation layer 17.
[0043] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.
Claims
1. A semiconductor device, characterized in that, include: Semiconductor substrate; A metal electrode layer is disposed on the semiconductor substrate and forms an electrical contact with the semiconductor substrate. The peripheral side surface of the metal electrode layer has a plurality of protrusions and a recess located between each two adjacent protrusions. as well as An inorganic passivation layer is disposed on the semiconductor substrate, the inorganic passivation layer covering the plurality of protrusions and recesses of the metal electrode layer and partially exposing the upper surface of the metal electrode layer opposite to the semiconductor substrate.
2. The semiconductor device according to claim 1, characterized in that, Each of the protrusions is an arc-shaped protrusion.
3. The semiconductor device according to claim 2, characterized in that, Each of the protrusions is an arc-shaped protrusion with a diameter greater than 4 micrometers.
4. The semiconductor device according to claim 1, characterized in that, The metal electrode layer has a lower surface facing the semiconductor substrate, the peripheral side surface is connected between the upper surface and the lower surface, and each of the protrusions extends from the lower surface to the upper surface on the peripheral side surface.
5. The semiconductor device according to any one of claims 1 to 4, characterized in that, Also includes: An organic protective layer is disposed on the semiconductor substrate, wherein the organic protective layer covers the inorganic passivation layer and partially exposes the upper surface of the metal electrode layer.
6. The semiconductor device according to any one of claims 1 to 4, characterized in that, Also includes: The second electrode layer is disposed on the side of the semiconductor substrate opposite to the metal electrode layer and forms an electrical contact with the semiconductor substrate.
7. The semiconductor device according to any one of claims 1 to 4, characterized in that, Also includes: A field oxide layer is disposed on the semiconductor substrate and a contact hole is formed to expose a portion of the semiconductor substrate; The metal electrode layer fills the contact hole to form an electrical contact with the semiconductor substrate and extends toward the field oxide layer to partially overlap with it. The inorganic passivation layer is located on the side of the field oxide layer opposite to the semiconductor substrate.
8. The semiconductor device according to claim 7, characterized in that, The thickness of the field oxygen layer is 0.5-1 micrometer; and / or, the thickness of the metal electrode layer is 3-6 micrometers; and / or, the thickness of the inorganic passivation layer is 0.3-2 micrometers.
9. A semiconductor device, characterized in that, include: Semiconductor substrate; A metal electrode layer is disposed on the semiconductor substrate and forms an electrical contact with the semiconductor substrate; as well as An inorganic passivation layer is disposed on the semiconductor substrate, the inorganic passivation layer covering the metal electrode layer and partially exposing the metal electrode layer. The metal electrode layer has a lower surface facing the semiconductor substrate, an upper surface facing away from the semiconductor substrate, and a peripheral side surface connecting the lower surface and the upper surface. The peripheral side surface is a wavy surface extending circumferentially in the metal electrode layer.
10. The semiconductor device according to claim 9, characterized in that, include: A field oxide layer is disposed on the semiconductor substrate and a contact hole is formed to expose a portion of the semiconductor substrate; The metal electrode layer fills the contact hole to form an electrical contact with the semiconductor substrate and extends toward the field oxide layer to partially overlap with it. The inorganic passivation layer is located on the side of the field oxide layer away from the semiconductor substrate, and the wavy surface is located on the side of the field oxide layer away from the semiconductor substrate and is covered by the inorganic passivation layer.