Semiconductor device
By designing a structure in a semiconductor device with a gate insulating layer height difference of less than 0.1 μm between the active region and the transition region, the problems of passivation layer deformation and shedding are solved, thereby improving the reliability and electrical performance of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2026-07-10
AI Technical Summary
The passivation layer in semiconductor devices is prone to deformation, cracking, and detachment, which affects the electrical performance and reliability of the devices.
Design a semiconductor device structure in which the top surface of the first gate insulating layer in the active region is lower than the top surface of the second gate insulating layer in the transition region, and the source electrode layer is disposed on one side of the top surface of the first gate insulating layer, such that the height difference between the top surface of the source electrode layer and the top surface of the second gate insulating layer is less than or equal to 0.1 μm, thereby achieving the planarization of the transition region structure and avoiding the deformation and peeling of the passivation layer caused by thermal stress.
By flattening the transition region structure, the risk of stress concentration failure is reduced, thereby improving the reliability and electrical performance of semiconductor devices.
Smart Images
Figure CN122373438A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device. Background Technology
[0002] Silicon carbide (SiC), as a representative of third-generation semiconductor materials, has become an important research subject for high-frequency high-voltage devices due to its excellent physical properties such as wide bandgap, high thermal conductivity, high breakdown voltage, and high electron mobility, as well as its performance under high temperature, high power, and high radiation conditions. Its superior performance under high voltage and low on-resistance requirements has made it a focus of attention in both industry and research.
[0003] The active area of a power device directly affects its electrical characteristics; a larger area results in lower on-resistance. In power devices, the thermal expansion of the substrate, passivation layer dielectric, and metal is also a key factor affecting device performance and reliability.
[0004] In related technologies, semiconductor devices suffer from problems such as easy deformation, cracking, or even detachment of the passivation layer, which affects the electrical performance and reliability of the devices. Summary of the Invention
[0005] This application provides a semiconductor device to solve the problems of easy deformation, cracking, and peeling of the passivation layer in semiconductor devices in related technologies.
[0006] To solve the above-mentioned technical problems, one technical solution adopted in this application is: to provide a semiconductor device, comprising:
[0007] Substrate;
[0008] A semiconductor epitaxial layer is disposed on the substrate; the semiconductor epitaxial layer includes an active region, a terminal region surrounding the active region, and a transition region connecting the active region and the terminal region; within the active region, the semiconductor epitaxial layer has a plurality of semiconductor cells spaced apart, each of the semiconductor cells extending from the surface of the semiconductor epitaxial layer away from the substrate toward the substrate, and each semiconductor cell includes an adjoining well region, a well region contact region, and a source region;
[0009] A gate oxide layer covers the active region;
[0010] A gate electrode layer is disposed on the side of the gate oxide layer away from the substrate;
[0011] A gate insulating layer covering the gate electrode layer;
[0012] A source electrode layer is disposed on the side of the gate insulating layer away from the substrate and is electrically connected to the source region through a first opening;
[0013] The gate insulating layer includes a first gate insulating layer located in the active region and a second gate insulating layer located in the transition region; the top surface of the first gate insulating layer is lower than the top surface of the second gate insulating layer; the source electrode layer is located in the active region and disposed on one side of the top surface of the first gate insulating layer; the absolute value of the height difference between the top surface of the source electrode layer and the top surface of the second gate insulating layer is less than or equal to 0.1 μm.
[0014] In some embodiments, the top surface of the source electrode layer is flush with the top surface of the second gate insulating layer.
[0015] In some embodiments, the thickness of the first gate insulating layer is less than the thickness of the second gate insulating layer.
[0016] In some embodiments, the semiconductor device further includes an insulating dielectric layer; the insulating dielectric layer is disposed between the gate electrode layer and the gate oxide layer; the insulating dielectric layer includes a first insulating dielectric layer located in the active region and a second insulating dielectric layer located in the transition region;
[0017] The gate electrode layer includes a gate electrode portion and a gate connection portion connected to each other. The gate electrode portion is located in the active region and disposed between the first insulating dielectric layer and the first gate insulating layer. The gate connection portion is located in the transition region and disposed between the second insulating dielectric layer and the second gate insulating layer. The second gate insulating layer has a second opening, thereby exposing the gate connection portion.
[0018] In some embodiments, the thickness of the first insulating dielectric layer is less than the thickness of the second insulating dielectric layer.
[0019] In some embodiments, the semiconductor device further includes:
[0020] An interconnect dielectric layer; the interconnect dielectric layer covers the active region, the terminal region, and the transition region; within the active region, the interconnect dielectric layer has a third opening, exposing the source electrode layer; within the transition region, the interconnect dielectric layer has a fourth opening; the fourth opening communicates with the second opening;
[0021] A conductive pad layer is disposed on the side of the interconnect dielectric layer away from the substrate; the conductive pad layer includes a source pad layer and a gate pad layer disposed with insulating spacing; the source pad layer is electrically connected to the source electrode layer through the third opening, and the gate pad layer is electrically connected to the gate connection portion through the fourth opening and the second opening.
[0022] In some embodiments, the gate pad layer is disposed at the edge of the active region and extends from the active region to the transition region, and the source pad layer surrounds the gate pad layer; the portion of the gate pad layer located in the transition region is electrically connected to the gate connection portion through the fourth opening and the second opening.
[0023] In some embodiments, within the transition region, the semiconductor epitaxial layer has a transition doped region, and the interconnect dielectric layer further has a fifth opening through which the transition doped region is exposed; the source pad layer is electrically connected to the transition doped region through the fifth opening.
[0024] In some embodiments, the outer edge of the source pad layer is flush with the outer edge of the terminal region; the transition doped region and the fifth opening surround the active region.
[0025] In some embodiments, the semiconductor device further includes a passivation layer, the passivation layer comprising:
[0026] The first annular passivation layer surrounds the outer edge of the source pad layer and covers the outer edge of the source pad layer.
[0027] The second annular passivation layer surrounds the outer edge of the gate pad layer and covers the outer edge of the gate pad layer and the inner edge of the source pad layer.
[0028] The beneficial effects of this application are as follows: Unlike existing technologies, this application discloses a semiconductor device, comprising: a substrate; a semiconductor epitaxial layer disposed on the substrate, the semiconductor epitaxial layer including an active region, a terminal region surrounding the active region, and a transition region connecting the active region and the terminal region; within the active region, the semiconductor epitaxial layer has a plurality of spaced semiconductor cells, each extending from the surface of the semiconductor epitaxial layer away from the substrate towards the substrate; each semiconductor cell including an adjoining well region, a well contact region, and a source region; a gate oxide layer covering the active region; and a gate electrode layer. The gate oxide layer is disposed on the side away from the substrate; a gate insulating layer covers the gate electrode layer; a source electrode layer is disposed on the side of the gate insulating layer away from the substrate and is electrically connected to the source region through a first opening; wherein, the gate insulating layer includes a first gate insulating layer located in the active region and a second gate insulating layer located in the transition region; the top surface of the first gate insulating layer is lower than the top surface of the second gate insulating layer; the source electrode layer is located in the active region and disposed on the top surface of the first gate insulating layer; the absolute value of the height difference between the top surface of the source electrode layer and the top surface of the second gate insulating layer is less than or equal to 0.1 μm. By setting the top surface of the first gate insulating layer in the active region to be lower than the top surface of the second gate insulating layer in the transition region, and placing the source electrode layer in the active region and located on one side of the top surface of the first gate insulating layer, the height difference between the top surface of the source electrode layer and the top surface of the second gate insulating layer is small, and the two top surfaces can be kept basically flush. This makes the layers containing the source electrode layer and the second gate insulating layer of the semiconductor device relatively flat, avoiding the formation of a step between the second gate insulating layer and the source electrode layer in the transition region. This achieves flattening of the transition region structure, which helps to improve the problem of thermal stress inside the passivation layer formed at high temperature due to the inconsistency of the thermal expansion coefficients of the metal and the passivation layer of the semiconductor device, thus reducing the risk of stress concentration failure and improving the reliability of the semiconductor device. Attached Figure Description
[0029] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:
[0030] Figure 1 This is a top view schematic diagram of the semiconductor device provided in this application;
[0031] Figure 2 yes Figure 1 A top view of one embodiment of the provided semiconductor device after removing the passivation layer;
[0032] Figure 3 yes Figure 1 A schematic diagram of cross-section AA of one embodiment of the provided semiconductor device;
[0033] Figure 4 yes Figure 3 A magnified view of a portion of region S in the middle;
[0034] Figure 5 yes Figure 1 A schematic diagram of a BB cross-section of one embodiment of the provided semiconductor device;
[0035] Figure 6 yes Figure 2 A schematic diagram of the AA cross-section of the provided semiconductor device;
[0036] Figure 7 yes Figure 2 A schematic diagram of the BB cross-section of the provided semiconductor device;
[0037] Figure 8 yes Figure 2 A schematic diagram of the AA cross-section of the provided semiconductor device after the conductive pad layer has been removed;
[0038] Figure 9 yes Figure 2 A schematic diagram of the BB cross-section of the provided semiconductor device after the conductive pad layer has been removed;
[0039] Figure 10 yes Figure 2 A schematic diagram of the AA cross section of the provided semiconductor device after removing the conductive pad layer and interconnect dielectric layer;
[0040] Figure 11 yes Figure 2 A schematic diagram of the BB cross-section of the provided semiconductor device after removing the conductive pad layer and interconnect dielectric layer.
[0041] Icon labels:
[0042] 100. Semiconductor device; 1. Substrate; 11. Active region; 12. Transition region; 13. Termination region; 14. Transition doped region; 2. Semiconductor epitaxial layer; 21. Semiconductor cell; 211. Well region; 212. Well region contact region; 213. Source region; 22. Ohmic contact layer; 3. Gate oxide layer; 4. Gate electrode layer; 41. Gate electrode portion; 42. Gate connection portion; 5. Gate insulating layer; 51. First gate insulating layer; 52. Second gate Insulating layer; 53, First opening; 54, Second opening; 6, Insulating dielectric layer; 61, First insulating dielectric layer; 62, Second insulating dielectric layer; 7, Source electrode layer; 8, Interconnect dielectric layer; 81, Third opening; 82, Fourth opening; 83, Fifth opening; 9, Conductive pad layer; 91, Source pad layer; 92, Gate pad layer; 93, Sixth opening; 10, Passivation layer; 101, First annular passivation layer; 102, Second annular passivation layer. Detailed Implementation
[0043] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0044] The terms "first," "second," and "third" used in the embodiments of this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.
[0045] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0046] See Figures 1 to 11, Figure 1 This is a top view schematic diagram of the semiconductor device provided in this application. Figure 2 yes Figure 1 A top view schematic diagram of one embodiment of the provided semiconductor device after removing the passivation layer. Figure 3 yes Figure 1 A schematic diagram of cross-section AA of one embodiment of the provided semiconductor device. Figure 4 yes Figure 3 A magnified view of a portion of region S in the middle. Figure 5 yes Figure 1 A schematic diagram of the BB cross-section of one embodiment of the provided semiconductor device. Figure 6 yes Figure 2 A schematic diagram of the AA section of the provided semiconductor device. Figure 7 yes Figure 2 A schematic diagram of the BB cross-section of the provided semiconductor device. Figure 8 yes Figure 2 A schematic diagram of the AA cross-section of the provided semiconductor device after the conductive pad layer has been removed. Figure 9 yes Figure 2 A schematic diagram of the BB cross-section of the provided semiconductor device after the conductive pad layer has been removed. Figure 10 yes Figure 2 The provided schematic diagram shows the AA cross-section of the semiconductor device after the conductive pad layer and interconnect dielectric layer have been removed. Figure 11 yes Figure 2 A schematic diagram of the BB cross-section of the provided semiconductor device after removing the conductive pad layer and interconnect dielectric layer.
[0047] See Figures 1 to 11 This application provides a semiconductor device 100, which includes a substrate 1 (Sub), a semiconductor epitaxial layer 2 (Epi), a gate oxide layer 3, a gate electrode layer 4, a gate insulating layer 5, and a source electrode layer 7. The semiconductor epitaxial layer 2 is disposed on the substrate 1 and includes an active region 11, a termination region 13 surrounding the active region 11, and a transition region 12 connecting the active region 11 and the termination region 13. Within the active region 11, the semiconductor epitaxial layer 2 has a plurality of spaced semiconductor cells 21, each extending from the surface of the semiconductor epitaxial layer 2 away from the substrate 1 toward the substrate 1. Each semiconductor cell 21 includes an adjoining well region 211, a well contact region 212, and a source region 213. The gate oxide layer 3 covers the active region 11, and the gate electrode layer 4 is disposed on the side of the gate oxide layer 3 away from the substrate 1. Specifically, the gate electrode layer 4 can be a polysilicon layer or a metal layer. A gate insulating layer 5 covers the gate electrode layer 4, and a source electrode layer 7 is disposed on the side of the gate insulating layer 5 away from the substrate 1, and is electrically connected to the source region 213 through a first opening 53. Specifically, as shown... Figure 10 and Figure 11As shown, the first opening 53 penetrates the gate insulating layer 5 and the gate oxide layer 3 within the active region 11 along the thickness direction of the semiconductor device 100, and exposes the source region 213 of the semiconductor cell 21. A portion of the source electrode layer 7 passes through the first opening 53 and is electrically connected to the source region 213 of the semiconductor cell 21. Specifically, in some embodiments, such as... Figures 3 to 7 As shown, an ohmic contact layer 22 is disposed on the surface of the source region 213 of the semiconductor cell 21 away from the substrate 1, and a portion of the source electrode layer 7 passes through the first opening 53 and is electrically connected to the source region 213 of the semiconductor cell 21 through the ohmic contact layer 22.
[0048] Among them, see Figures 1 to 7 The gate insulating layer 5 includes a first gate insulating layer 51 located within the active region 11 and a second gate insulating layer 52 located within the transition region 12. The top surface of the first gate insulating layer 51 is lower than the top surface of the second gate insulating layer 52. Specifically, the top surface of the first gate insulating layer 51 refers to the surface of the first gate insulating layer 51 that is away from the substrate 1, and the top surface of the second gate insulating layer 52 refers to the surface of the second gate insulating layer 52 that is away from the substrate 1. The source electrode layer 7 is located within the active region 11 and is disposed on one side of the top surface of the first gate insulating layer 51. Specifically, the source electrode layer 7 is only located within the active region 11, that is, the source electrode layer 7 is only located on one side of the top surface of the first gate insulating layer 51, and no source electrode layer 7 is disposed within the transition region 12. The absolute value of the height difference between the top surface of the source electrode layer 7 (i.e., the surface of the source electrode layer 7 away from the substrate 1) and the top surface of the second gate insulating layer 52 is less than or equal to 0.1 μm. Specifically, the height difference between the top surface of the source electrode layer 7 and the top surface of the second gate insulating layer 52 is in the range of -0.1 μm to 0.1 μm, for example, it can be in the range of -0.05 μm to 0.05 μm, or it can be in the range of -0.02 μm to 0.02 μm. That is, the height of the top surface of the source electrode layer 7 above the top surface of the second gate insulating layer 52 is less than or equal to 0.1 μm, or the height of the top surface of the source electrode layer 7 below the top surface of the second gate insulating layer 52 is less than or equal to 0.1 μm.
[0049] It is understood that in this application, by configuring the gate insulating layer 5 to include a first gate insulating layer 51 located in the active region 11 and a second gate insulating layer 52 located in the transition region 12, and configuring the top surface of the first gate insulating layer 51 in the active region 11 to be lower than the top surface of the second gate insulating layer 52 in the transition region 12, and configuring the source electrode layer 7 in the active region 11 and located on one side of the top surface of the first gate insulating layer 51, the absolute value of the height difference between the top surface of the source electrode layer 7 and the top surface of the second gate insulating layer 52 is less than or equal to 0.1 μm, making the height difference between the top surface of the source electrode layer 7 and the top surface of the second gate insulating layer 52 small, and the heights of the two top surfaces can be kept basically flush, thereby making the semiconductor device... The top surface of the source electrode layer 7 and the second gate insulating layer 52 of device 100 is relatively flat. The active region 11 and the transition region 12 are basically at the same height in this layer. This avoids the formation of a step in the transition region 12 due to the large difference in height between the top surface of the second gate insulating layer 52 and the top surface of the source electrode layer 7. This achieves the flattening of the transition region 12 structure. It is beneficial to improve the problem of thermal stress inside the passivation layer 10 formed at high temperature due to the inconsistency of the thermal expansion coefficients between the metal and the passivation layer 10 of the semiconductor device 100. This can lead to deformation, cracking or even detachment of the passivation layer 10. This reduces the risk of failure of the semiconductor device 100 due to stress concentration and improves the reliability of the semiconductor device 100.
[0050] Specifically, in some embodiments, substrate 1 can be an N-type silicon carbide substrate 1, and semiconductor epitaxial layer 2 can be an N-type silicon carbide epitaxial layer. After cleaning and polishing the N-type silicon carbide substrate 1, the N-type silicon carbide epitaxial layer can be grown on substrate 1 using MOCVD (chemical vapor deposition). The thickness of the N-type silicon carbide epitaxial layer can be 1 μm-100 μm, and the concentration is 1E14 cm⁻¹. -3 -5E16cm -3 After growing an N-type silicon carbide epitaxial layer, polishing and grinding are performed, and then ion implantation and dielectric growth of the active region 11 and the terminal region 13 are achieved according to the conventional process flow.
[0051] In some implementations, see Figures 3 to 11 The top surface of the source electrode layer 7 is flush with the top surface of the second gate insulating layer 52 (e.g., Figure 10 and Figure 11As shown in the diagram, there is no height difference between the top surface of the source electrode layer 7 and the top surface of the second gate insulating layer 52; the two top surfaces are located on the same plane. It can be understood that the top surface of the source electrode layer 7 is not a smooth plane; the top surface of the source electrode layer 7 has multiple recesses corresponding to the first opening 53. However, in the non-recessed areas, the top surface of the source electrode layer 7 is flush with the top surface of the second gate insulating layer 52. Because the top surface of the source electrode layer 7 is flush with the top surface of the second gate insulating layer 52, no step is formed on the top surface of the layer containing the source electrode layer 7 and the second gate insulating layer 52 at the transition region 12. This maximizes the flatness of the structure above the transition region 12, resulting in a relatively flat film structure when the semiconductor device 100 is fabricating the remaining film structures located on the top surface side of the source electrode layer 7 and the second gate insulating layer 52. Consequently, when fabricating the passivation layer 10, it is more conducive to improving the problem of thermal stress inside the passivation layer 10 formed at high temperature due to the inconsistency of the thermal expansion coefficients between the metal and the passivation layer 10 of the semiconductor device 100, which can lead to deformation, cracking, or even detachment of the passivation layer 10. This more effectively reduces the risk of stress concentration failure of the semiconductor device 100 and is more conducive to improving the reliability of the semiconductor device 100.
[0052] Specifically, in some embodiments, the thickness of the source electrode layer 7 is approximately 0.8 μm to 1.2 μm, so that the top surface of the source electrode layer 7 is substantially flush with the top surface of the second gate insulating layer 52, and a stable electrical connection with the source region 213 of the semiconductor cell 21 can be achieved through the first opening 53. In some embodiments, during the fabrication of the semiconductor device 100, after depositing the metal layer of the source electrode layer 7, a portion of the metal layer can cover the top surface of the second gate insulating layer 52 located in the transition region 12. A portion of the metal layer on one side of the top surface of the second gate insulating layer 52 located in the transition region 12 can be removed by etching, leaving only the portion of the metal layer located in the active region 11 to form the source electrode layer 7, and ensuring that the top surface of the source electrode layer 7 is substantially flush with the top surface of the second gate insulating layer 52.
[0053] In one embodiment, the ohmic contact layer 22 is disposed only within the first opening 53, and not on the top surface of the second gate insulating layer 52 located in the transition region 12. This results in a smaller recess depth of the top surface of the source electrode layer 7 corresponding to the first opening 53, and a higher flatness between the top surface of the entire source electrode layer 7 and the top surface of the second gate insulating layer 52. Specifically, see... Figures 3 to 11In some embodiments, the thickness of the first gate insulating layer 51 is less than the thickness of the second gate insulating layer 52, so that the top surface of the first gate insulating layer 51 is lower than the top surface of the second gate insulating layer 52. This allows the top surface of the source electrode layer 7, after being formed on the top surface of the first gate insulating layer 51, to remain substantially flush with the top surface of the second gate insulating layer 52. This ensures that the absolute value of the height difference between the top surface of the source electrode layer 7 and the top surface of the second gate insulating layer 52 is less than or equal to 0.1 μm, thereby facilitating the planarization of the transition region 12 and solving the problems of deformation, cracking, or even detachment of the passivation layer 10.
[0054] In other embodiments, the thickness of the first gate insulating layer 51 may not be less than the thickness of the second gate insulating layer 52. For example, the second gate insulating layer 52 can be directly raised by other film layers; or, the thickness of other film layers located on the side of the first gate insulating layer 51 near the substrate 1 can be set to be less than the thickness of other film layers located on the side of the second gate insulating layer 52 near the substrate 1, so that when depositing the first gate insulating layer 51 and the second gate insulating layer 52, even if the thickness of the first gate insulating layer 51 is greater than or equal to the thickness of the second gate insulating layer 52, a height difference can be formed between the top surface of the first gate insulating layer 51 and the top surface of the second gate insulating layer 52, so that the top surface of the first gate insulating layer 51 is lower than the top surface of the second gate insulating layer 52. The specific configuration can be designed as needed, and this application does not limit it.
[0055] Specifically, in some implementation methods, see [link to implementation details]. Figures 3 to 11 The semiconductor device 100 further includes an insulating dielectric layer 6, which is disposed between the gate electrode layer 4 and the gate oxide layer 3 (e.g., Figure 4 (As shown). The insulating dielectric layer 6 includes a first insulating dielectric layer 61 (as shown). Figure 4 and Figure 5 As shown in the diagram, the first insulating dielectric layer 61 is located within the active region 11, and the second insulating dielectric layer 62 is located within the transition region 12. The gate electrode layer 4 includes a gate electrode portion 41 and a gate connection portion 42 connected to each other. The gate electrode portion 41 is located within the active region 11 and is disposed between the first insulating dielectric layer 61 and the first gate insulating layer 51. The gate connection portion 42 is located within the transition region 12 and is disposed between the second insulating dielectric layer 62 and the second gate insulating layer 52.
[0056] That is, the first insulating dielectric layer 61, the gate electrode portion 41, and the first gate insulating layer 51 are all located within the active region 11, and the gate electrode portion 41 is located on the side of the first insulating dielectric layer 61 away from the substrate 1, and the first gate insulating layer 51 is located on the side of the gate electrode portion 41 away from the substrate 1. The second insulating dielectric layer 62, the gate connection portion 42, and the second gate insulating layer 52 are all located within the transition region 12, and the gate connection portion 42 is located on the side of the second insulating dielectric layer 62 away from the substrate 1, and the second gate insulating layer 52 is located on the side of the gate connection portion 42 away from the substrate 1.
[0057] Among them, see Figures 3 to 11 The second gate insulating layer 52 has a second opening 54, which exposes the gate connection portion 42 (e.g., Figure 11 (As shown). Specifically, the second opening 54 extends through the second gate insulating layer 52 located within the transition region 12 along the thickness direction of the semiconductor device 100 to expose the gate connection portion 42 located within the transition region 12, facilitating contact and electrical connection between the gate connection portion 42 and the subsequently fabricated gate pad layer 92.
[0058] For details, see Figures 3 to 11 In some embodiments, the thickness of the first insulating dielectric layer 61 is less than the thickness of the second insulating dielectric layer 62. That is, the top surface of the first insulating dielectric layer 61 located in the active region 11 is lower than the top surface of the second insulating dielectric layer 62 located in the transition region 12, thereby creating a height difference between the layers containing the first insulating dielectric layer 61 and the second insulating dielectric layer 62. This facilitates the fabrication of the gate electrode portion 41 and the first gate insulating layer 51 above the first insulating dielectric layer 61. After fabricating the gate connection portion 42 and the second gate insulating layer 52 above the second insulating dielectric layer 62, the top surface of the first gate insulating layer 51 located in the active region 11 is lower than the top surface of the second gate insulating layer 52 located in the transition region 12. This further facilitates the fabrication of the source electrode layer 7 on the top surface of the first gate insulating layer 51, ensuring that the absolute value of the height difference between the top surface of the source electrode layer 7 and the top surface of the second gate insulating layer 52 is less than 0.1 μm, thus solving the problem of deformation, cracking, or even detachment of the passivation layer 10. The larger thickness of the second insulating dielectric layer 62 is beneficial for better insulation between the gate connection portion 42 and the transition doped region 14.
[0059] In other embodiments, the thickness of the first insulating dielectric layer 61 may not be less than the thickness of the second insulating dielectric layer 62, and the second insulating dielectric layer 62 may be raised by other insulating film layers; alternatively, during the subsequent fabrication of the first gate insulating layer 51 and the second gate insulating layer 52, other methods may be adopted to make the top surface of the first gate insulating layer 51 lower than the top surface of the second gate insulating layer 52. For example, during the deposition of the first gate insulating layer 51 and the second gate insulating layer 52, the thickness of the deposited first gate insulating layer 51 may be directly made less than the thickness of the second gate insulating layer 52, or a portion of the first gate insulating layer 51 may be etched away by etching or other methods, thereby making the top surface of the first gate insulating layer 51 located in the active region 11 lower than the top surface of the second gate insulating layer 52 located in the transition region 12. Specific designs can be made as needed, and this application does not limit this.
[0060] See Figures 3 to 11 In some embodiments, the semiconductor device 100 further includes an interconnect dielectric layer 8 and a conductive pad layer 9. The interconnect dielectric layer 8 covers the active region 11, the terminal region 13, and the transition region 12; that is, the interconnect dielectric layer 8 covers the entire surface of the source electrode layer 7 and the side of the second gate insulating layer 52 away from the substrate 1. The material of the interconnect dielectric layer 8 may include any one or more of silicon oxide, silicon nitride, or polyimide (PI).
[0061] Within the active region 11, the interconnect dielectric layer 8 has a third opening 81, which exposes the source electrode layer 7. Specifically, as shown... Figure 3 and Figure 8 As shown, the interconnect dielectric layer 8 within the active region 11 has multiple third openings 81. These third openings 81 penetrate the interconnect dielectric layer 8 along the thickness direction of the semiconductor device 100, exposing the source electrode layer 7 through these openings. The third openings 81 can be arranged in an array or arbitrarily. (See also...) Figures 3 to 9 Within the transition region 12, the interconnecting medium layer 8 has a fourth opening 82, which is connected to the second opening 54.
[0062] like Figure 5 and Figure 9 As shown, the interconnect dielectric layer 8 in the transition region 12 has a fourth opening 82 at a position corresponding to the second opening 54 in the second gate insulating layer 52. The fourth opening 82 penetrates the interconnect dielectric layer 8 along the thickness direction of the semiconductor device 100 and communicates with the second opening 54 in the second gate insulating layer 52, so that the gate connection portion 42 is exposed through the second opening 54 and the fourth opening 82.
[0063] See Figures 2 to 7The conductive pad layer 9 is disposed on the side of the interconnect dielectric layer 8 away from the substrate 1. Specifically, the conductive pad layer 9 covers the active region 11, the terminal region 13, and the transition region 12. For example, the conductive pad layer 9 covers the entire surface of the interconnect dielectric layer 8 away from the substrate 1. The conductive pad layer 9 includes a source pad layer 91 and a gate pad layer 92 that are insulated from each other. Specifically, in some embodiments, the source pad layer 91 is disposed around the gate pad layer 92. In one specific embodiment, such as... Figure 2 As shown, the gate pad layer 92 is disposed at the edge of the active region 11 and extends from the active region 11 to the transition region 12 but does not extend to the terminal region 13. The source pad layer 91 surrounds the gate pad layer 92. That is, the active region 11, the terminal region 13, and the transition region 12 are all provided with the source pad layer 91, while the gate pad layer 92 is only located in the transition region 12 and the active region 11, and is not provided in the terminal region 13. The source pad layer 91 and the gate pad layer 92 are spaced apart, specifically, as shown... Figure 2 , Figure 5 and Figure 7 As shown, the source pad layer 91 and the gate pad layer 92 are spaced apart by a sixth opening 93, which can be an annular opening surrounding the gate pad layer 92. Part of the sixth opening 93 is located in the active region 11, and part is located in the transition region 12. In other embodiments, the portion of the sixth opening 93 located in the transition region 12 can also extend to the terminal region 13.
[0064] The source pad layer 91 is electrically connected to the source electrode layer 7 through the third opening 81, and the gate pad layer 92 is electrically connected to the gate connection portion 42 through the fourth opening 82 and the second opening 54. Specifically, as shown... Figure 3 As shown, the source pad layer 91 located on the side of the interconnect dielectric layer 8 away from the substrate 1 is directly electrically connected to the source electrode layer 7 located on the side of the interconnect dielectric layer 8 closer to the substrate 1 through multiple third openings 81 in the active region 11. Figure 5 As shown, the gate pad layer 92 located on the side of the interconnect dielectric layer 8 away from the substrate 1 is electrically connected to the gate connection portion 42 through the interconnected fourth opening 82 and second opening 54 in the transition region 12, thereby realizing the electrical connection between the gate pad layer 92 and the gate electrode layer 4. Specifically, a portion of the gate pad layer 92 located in the transition region 12 is electrically connected to the gate connection portion 42 through the fourth opening 82 and the second opening 54, while the gate pad layer 92 located in the active region 11 is completely located on the surface of the interconnect dielectric layer 8 away from the substrate 1.
[0065] It can be understood that the interconnect dielectric layer 8 is an interlayer dielectric layer between multiple metals, separating the gate pad layer 92 from the source electrode layer 7. The gate pad layer 92 and the source pad layer 91 are disposed on the side of the interconnect dielectric layer 8 away from the substrate 1. By providing a third opening 81 and a fourth opening 82 communicating with the second opening 54 in the interconnect dielectric layer 8, the source pad layer 91 can be electrically connected to the source electrode layer 7 through the third opening 81, and the gate pad layer 92 can be electrically connected to the gate connection portion 42 through the fourth opening 82 and the second opening 54 in the transition region 12. By using a multilayer metal interconnect method, the original gate pad layer 92 is disposed above the source electrode layer 7, freeing up the area of the active region 11 originally occupied by the gate pad layer 92, thereby increasing the area of the active region 11. This helps to reduce the on-resistance and improve the electrical performance of the semiconductor device 100. Meanwhile, although the multilayer metal interconnect structure is prone to stress concentration failure, by setting the absolute value of the height difference between the top surface of the source electrode layer 7 and the top surface of the second gate insulating layer 52 to be less than or equal to 0.1 μm, and by placing the gate pad layer 92 on the side of the interconnect dielectric layer 8 away from the substrate 1, and electrically connecting it to the gate connection portion 42 through the fourth opening 82 and the second opening 54 in the transition region 12, the structure above the transition region 12 is flattened, reducing the steps formed by the film layer above the transition region 12. This can also more effectively reduce the risk of stress concentration failure caused by multilayer metal interconnect. Thus, while increasing the area of the active region 11 and improving electrical performance, it also effectively improves the problem of shear stress at the interface between the metal and the passivation layer 10 during temperature cycling due to the large difference in thermal expansion coefficients between the chip molding compound, the metal and the passivation layer 10, which leads to stress concentration and causes the passivation layer 10 to deform, crack or even fall off, thereby improving the reliability of the power device.
[0066] See Figures 3 to 11 In some embodiments, within the transition region 12, the semiconductor epitaxial layer 2 has a transition doped region 14, and the interconnect dielectric layer 8 also has a fifth opening 83 (e.g., Figure 3 , Figure 8 and Figure 9 As shown, the transition doped region 14 is exposed through the fifth opening 83, and the source pad layer 91 is electrically connected to the transition doped region 14 through the fifth opening 83. Specifically, the fifth opening 83 is located in the transition region 12, and the fifth opening 83 sequentially penetrates the interconnect dielectric layer 8, the second gate insulating layer 52, and the second insulating dielectric layer 62 along the thickness direction of the semiconductor device 100, so that the transition doped region 14 in the semiconductor epitaxial layer 2 of the transition region 12 is exposed through the fifth opening 83. A portion of the source pad layer 91 located in the transition region 12 passes through the fifth opening 83 and makes contact with the transition doped region 14.
[0067] See Figures 2 to 7In some implementations, the outer edge of the source pad layer 91 is flush with the outer edge of the terminal region 13 (e.g., Figure 2 As shown), the transition doped region 14 and the fifth opening 83 can surround the active region 11. That is, within the transition region 12, a transition doped region 14 is provided around the active region 11, and the fifth opening 83 is annular and surrounds the active region 11, so that the source pad layer 91 can achieve a full circumference of electrical connection with the transition doped region 14 through the annular fifth opening 83 around the active region 11 (specifically within the transition region 12).
[0068] See Figures 1 to 7 The semiconductor device 100 also includes a passivation layer 10, which covers the outermost layer of the semiconductor device 100. The material of the passivation layer 10 may include any one or a combination of silicon oxide, silicon nitride, or polyimide (PI).
[0069] In some implementations, such as Figure 1 As shown, the passivation layer 10 includes a first annular passivation layer 101 and a second annular passivation layer 102. The first annular passivation layer 101 surrounds the outer edge of the source pad layer 91 and covers its outer edge; the second annular passivation layer 102 surrounds the outer edge of the gate pad layer 92 and covers both its outer edge and the inner edge of the source pad layer 91. The passivation layer 10 provides a physical barrier for the semiconductor device 100, preventing damage from external environmental factors such as moisture, dust, and chemicals. This helps improve the long-term stability and lifespan of the semiconductor device 100. Simultaneously, it can reduce or eliminate surface defect states, improving electrical characteristics.
[0070] Since the top surface of the first gate insulating layer 51 in this application is lower than the top surface of the second gate insulating layer 52, and the absolute value of the height difference between the top surface of the source electrode layer 7 and the top surface of the second gate insulating layer 52 is less than or equal to 0.1 μm, the top surface of the source electrode layer 7 and the top surface of the second gate insulating layer 52 can be basically kept flush, and no step is formed above the transition region 12. The structure above the transition region 12 is relatively flat. By reasonably designing the stacking method of the metal and passivation layer 10 above the transition region 12 and the position of multiple openings, the planarization of the transition region 12 is achieved. Therefore, when the first annular passivation layer 101 and the second annular passivation layer 102 are formed, the risk of stress concentration failure caused by the multilayer metal interconnect structure can be effectively reduced. The problem of deformation, cracking or even detachment of the passivation layer 10 caused by the difference in thermal expansion coefficients between the metal and the passivation layer 10 during temperature cycling can be effectively improved, thereby improving the reliability and electrical performance of the semiconductor device 100.
[0071] In other embodiments, the substrate 1 and the semiconductor epitaxial layer 2 of the semiconductor device 100 may not be made of silicon carbide. The stacking method of the multiple films and passivation layer 10 and the design method of the multiple openings described above in this application can also be applied to all power devices made of materials such as silicon and gallium nitride, which can expand the application range of the semiconductor device 100. While increasing the area of the active region 11, it can solve the problem of cracking or even falling off of the passivation layer 10 caused by the difference in thermal expansion coefficients between the metal and the passivation layer 10, thereby improving the electrical performance and reliability of the semiconductor device 100.
[0072] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
Claims
1. A semiconductor device, characterized in that, include: Substrate; A semiconductor epitaxial layer is disposed on the substrate; the semiconductor epitaxial layer includes an active region, a terminal region surrounding the active region, and a transition region connecting the active region and the terminal region; within the active region, the semiconductor epitaxial layer has a plurality of semiconductor cells spaced apart, each of the semiconductor cells extending from the surface of the semiconductor epitaxial layer away from the substrate toward the substrate, and each semiconductor cell includes an adjoining well region, a well region contact region, and a source region; A gate oxide layer covers the active region; A gate electrode layer is disposed on the side of the gate oxide layer away from the substrate; A gate insulating layer covering the gate electrode layer; A source electrode layer is disposed on the side of the gate insulating layer away from the substrate and is electrically connected to the source region through a first opening; The gate insulating layer includes a first gate insulating layer located in the active region and a second gate insulating layer located in the transition region; the top surface of the first gate insulating layer is lower than the top surface of the second gate insulating layer; the source electrode layer is located in the active region and disposed on one side of the top surface of the first gate insulating layer; the absolute value of the height difference between the top surface of the source electrode layer and the top surface of the second gate insulating layer is less than or equal to 0.1 μm.
2. The semiconductor device according to claim 1, characterized in that, The top surface of the source electrode layer is flush with the top surface of the second gate insulating layer.
3. The semiconductor device according to claim 1, characterized in that, The thickness of the first gate insulating layer is less than the thickness of the second gate insulating layer.
4. The semiconductor device according to any one of claims 1-3, characterized in that, The semiconductor device further includes an insulating dielectric layer; the insulating dielectric layer is disposed between the gate electrode layer and the gate oxide layer; the insulating dielectric layer includes a first insulating dielectric layer located in the active region and a second insulating dielectric layer located in the transition region; The gate electrode layer includes a gate electrode portion and a gate connection portion connected to each other. The gate electrode portion is located in the active region and disposed between the first insulating dielectric layer and the first gate insulating layer. The gate connection portion is located in the transition region and disposed between the second insulating dielectric layer and the second gate insulating layer. The second gate insulating layer has a second opening, thereby exposing the gate connection portion.
5. The semiconductor device according to claim 4, characterized in that, The thickness of the first insulating dielectric layer is less than the thickness of the second insulating dielectric layer.
6. The semiconductor device according to claim 4, characterized in that, The semiconductor device further includes: An interconnect dielectric layer; the interconnect dielectric layer covers the active region, the terminal region, and the transition region; within the active region, the interconnect dielectric layer has a third opening, exposing the source electrode layer; within the transition region, the interconnect dielectric layer has a fourth opening; the fourth opening communicates with the second opening; A conductive pad layer is disposed on the side of the interconnect dielectric layer away from the substrate; the conductive pad layer includes a source pad layer and a gate pad layer disposed with insulating spacing; the source pad layer is electrically connected to the source electrode layer through the third opening, and the gate pad layer is electrically connected to the gate connection portion through the fourth opening and the second opening.
7. The semiconductor device according to claim 6, characterized in that, The gate pad layer is disposed at the edge of the active region and extends from the active region to the transition region, and the source pad layer surrounds the gate pad layer; the portion of the gate pad layer located in the transition region is electrically connected to the gate connection portion through the fourth opening and the second opening.
8. The semiconductor device according to claim 6, characterized in that, Within the transition region, the semiconductor epitaxial layer has a transition doped region, and the interconnect dielectric layer also has a fifth opening through which the transition doped region is exposed; the source pad layer is electrically connected to the transition doped region through the fifth opening.
9. The semiconductor device according to claim 8, characterized in that, The outer edge of the source pad layer is flush with the outer edge of the terminal region; the transition doped region and the fifth opening surround the active region.
10. The semiconductor device according to claim 6, characterized in that, The semiconductor device further includes a passivation layer, the passivation layer comprising: The first annular passivation layer surrounds the outer edge of the source pad layer and covers the outer edge of the source pad layer. The second annular passivation layer surrounds the outer edge of the gate pad layer and covers the outer edge of the gate pad layer and the inner edge of the source pad layer.