A layout structure for mitigating warpage of medium voltage sgt-mosfet wafer

Abstract

This invention discloses a layout structure for mitigating wafer warpage in medium-voltage SGT-MOSFETs, relating to the technical field of semiconductor chip manufacturing. The structure includes: a peripheral cutoff ring, a first device unit, a second device unit, and a third device unit. Each device unit has an independent cutoff ring on its periphery, which partially overlaps with the peripheral cutoff ring, dividing the peripheral cutoff ring into a first region, a second region, and a third region. The drains of the first, second, and third device units are all connected to the wafer substrate, and the gates are connected in parallel. The field plates are all connected to the source electrode. The field plates of the first and second device units are connected across the unit and to the source electrode. The trench extension direction of the first and third device units is perpendicular to the trench extension direction of the second device unit. This invention effectively solves the wafer warpage problem caused by structural stress accumulation and weakened rigidity during the manufacturing process of large-size medium-voltage SGT-MOSFET devices.

Description

Technical Field

[0001] This invention relates to the technical field of semiconductor chip manufacturing, and more particularly to a layout structure for mitigating wafer warpage of medium-voltage SGT-MOSFETs. Background Technology

[0002] In the fabrication of medium-voltage shielded gate trench metal-oxide-semiconductor field-effect transistors (SGT-MOSFETs), wafer warpage is a common and critical process challenge. The primary cause of wafer warpage stems from the deep trenches in the device structure and the thick field oxide layer formed on their inner sides. During device fabrication, these two structures introduce significant localized stresses. Specifically, the deeper the trench etching and the thicker the inner oxide layer, the greater the stress generated, leading to a greater degree of overall wafer warpage.

[0003] Furthermore, as device sizes continue to increase, the structural rigidity of the wafer itself weakens, further amplifying the stress-induced deformation effect and making warpage particularly prominent in large-size devices. For example, when wafer warpage exceeds 175 micrometers, it severely affects the alignment accuracy in the photolithography process, leading to pattern transfer failure or preventing the wafer from entering the photolithography machine altogether. This forces the wafer production process to be interrupted, reducing device yield and increasing manufacturing costs and production cycle. Summary of the Invention

[0004] This invention provides a layout structure to mitigate wafer warpage of medium-voltage SGT-MOSFETs, solving the wafer warpage problem caused by structural stress accumulation and reduced rigidity during the manufacturing process of large-size medium-voltage SGT-MOSFET devices.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: The present invention provides a layout structure for mitigating wafer warpage of medium-voltage SGT-MOSFET, comprising: a peripheral cutoff ring, and a first device unit, a second device unit, and a third device unit sequentially disposed inside the peripheral cutoff ring; Each device unit is surrounded by an independent cutoff ring, which partially overlaps with the peripheral cutoff ring to divide the peripheral cutoff ring into a first region, a second region, and a third region in sequence. The first device unit, the second device unit, and the third device unit are located in the first region, the second region, and the third region, respectively. The drains of the first device unit, the second device unit, and the third device unit are all connected to the wafer substrate, the gates are connected in parallel, and the field plates are all connected to the source electrodes. The field plate electrodes of the first device unit and the second device unit are connected to the source electrode across the unit, and the field plate electrode of the third device unit is connected to the source electrode in the third region. The trench extension direction of the first device unit and the third device unit is perpendicular to the trench extension direction of the second device unit.

[0006] In one possible implementation, the field plate electrode in the central region of the first device unit is connected to the source electrode of the first device unit; the field plate electrodes at both ends of the first device unit are connected across units to the source electrode of the third device unit.

[0007] In one possible implementation, the field plate electrode in the central region of the second device unit is connected to the source electrode of the second device unit; the field plate electrode of the second device unit near the end of the first device unit is connected to the source electrode of the first device unit, and the field plate electrode of the second device unit near the end of the third device unit is connected to the source electrode of the third device unit.

[0008] In one possible implementation, the field plate electrodes of the central region and the two end edges of the third device unit are all connected to the source electrode of the third device unit.

[0009] In one possible implementation, the trenches of the first device unit and the third device unit extend along a first preset direction, and the trench of the second device unit extends along a second preset direction; the lengths of the first device unit and the third device unit in the second preset direction are equal, and equal to half the length of the second device unit in the second preset direction.

[0010] In one possible implementation, the active region metal orientation of the edge field plate electrodes connecting the two ends of the first device unit is perpendicular to the trench extension direction of the first device unit; the active region metal orientation of the edge field plate electrodes connecting the two ends of the third device unit is perpendicular to the trench extension direction of the third device unit.

[0011] In one possible implementation, multiple pressure-resistant rings are provided at intervals in the first region located around the first device unit, the second region located around the second device unit, and the third region located around the third device unit.

[0012] In one possible implementation, the metal wiring of the gate is disposed around the periphery of the overall device consisting of the first device unit, the second device unit, and the third device unit, and passes through the region between the first device unit and the second device unit, as well as the region between the second device unit and the third device unit.

[0013] The layout structure for mitigating wafer warpage of medium-voltage SGT-MOSFETs provided in this embodiment of the invention defines an alternating trench layout within a multi-unit parallel structure composed of a first device unit, a second device unit, and a third device unit. This collaboratively controls the distribution of mechanical stress and electric field at the layout level, effectively solving the wafer warpage problem caused by the accumulation of structural stress and weakening of rigidity during the manufacturing process of large-size medium-voltage SGT-MOSFET devices while reducing the parasitic interconnect resistance of the output capacitor.

[0014] The layout structure for mitigating wafer warpage of medium-voltage SGT-MOSFETs provided in this embodiment of the invention comprises a first device unit, a second device unit, and a third device unit that are independent of each other and connected in parallel. The drain of each device unit is connected to the wafer substrate, that is, each device unit shares the drain. The gates of each device unit are connected in parallel to form a unified gate control node, thereby realizing the synchronous turn-on and turn-off of the three device units electrically.

[0015] The layout structure for mitigating wafer warpage of medium-voltage SGT-MOSFETs provided in this embodiment of the invention features an independent cutoff ring around each device unit to physically isolate the device units, thereby effectively suppressing lateral leakage current between the device units.

[0016] In the layout structure for mitigating wafer warpage of medium-voltage SGT-MOSFET provided in this embodiment of the invention, the field plate electrodes of each device unit are connected to the source electrode, and the source electrode is grounded. This connection method enables the field plate electrodes of the device unit to play the role of electric field modulation. Attached Figure Description

[0017] Figure 1 A simplified top view of the overall layout of a layout structure for mitigating wafer warpage of a medium-voltage SGT-MOSFET, provided in an embodiment of the present invention; Figure 2 for Figure 1 A simplified cross-sectional diagram at point A-A' is used to show the trench structure of the first device unit, the second device unit, and the third device unit, as well as the arrangement of the withstand ring, peripheral stop ring, gate electrode, or source electrode between these three regions. Figure 3 for Figure 1 The enlarged view in section B shows the trench, source, and gate layout structure of the first and second device unit regions. Figure 4 for Figure 1 The enlarged view in section C shows the trench, source, and gate layout structures of the second and third device unit regions.

[0018] Figure labels and descriptions: 1. Peripheral cutoff ring; 11. Cutoff ring isolating the first and second device units; 12. Cutoff ring isolating the second and third device units; 2. First device unit; 21. Connection between the field plate electrode and the source electrode of the first device unit; 22. Source electrode of the first device unit; 23. First trench array; 3. Second device unit; 31. Connection between the field plate electrode and the source electrode of the second device unit; 32. Source electrode of the second device unit; 33. Second trench array; 4. Third device unit; 41. Connection between the field plate electrode and the source electrode of the third device unit; 42. Source electrode of the third device unit; 43. Third trench array; 5. Gate metal; 51. Gate pad; 52. Gate electrode between the first and second device units; 53. Gate electrode between the second and third device units; 6. Source electrode led out from the first device unit; 7. Source electrode led out from the third device unit; 8. Voltage withstand ring; 9. Peripheral metal of the source electrode of the third device unit. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more. Furthermore, the use of "based on" or "according to" implies openness and inclusiveness, because processes, steps, calculations, or other actions "based on" or "according to" one or more of the stated conditions or values ​​may in practice be based on additional conditions or beyond the stated values.

[0021] To address the wafer warpage problem caused by structural stress accumulation and reduced rigidity during the manufacturing process of large-size medium-voltage SGT-MOSFET devices, this invention provides a layout structure to mitigate wafer warpage in medium-voltage SGT-MOSFETs.

[0022] like Figure 1 , Figure 2As shown, this embodiment of the invention provides a layout structure for mitigating wafer warpage of a medium-voltage SGT-MOSFET, including: a peripheral cutoff ring 1, and a first device unit 2, a second device unit 3, and a third device unit 4 sequentially disposed inside the peripheral cutoff ring 1.

[0023] Each device unit is provided with an independent cutoff ring around its periphery. The independent cutoff ring partially overlaps with the peripheral cutoff ring 1, so that the peripheral cutoff ring 1 is divided into a first region, a second region and a third region in sequence. The first device unit 2, the second device unit 3 and the third device unit 4 are located in the first region, the second region and the third region respectively.

[0024] A cutoff ring 11 is provided between the first device unit 2 and the second device unit 3 to isolate the first device unit and the second device unit 3, and a cutoff ring 12 is provided between the second device unit 3 and the third device unit 4 to isolate the second device unit and the third device unit 4.

[0025] In other words, an independent cutoff ring is set around each device unit to separate the device units through physical isolation, thereby effectively suppressing the lateral leakage current between the device units.

[0026] The drains of the first device unit 2, the second device unit 3, and the third device unit 4 are all connected to the wafer substrate, the gates are connected in parallel, and the field plate electrodes are all connected to the source electrodes.

[0027] The device unit as a whole consists of a first device unit 2, a second device unit 3, and a third device unit 4 that are independent of each other and connected in parallel. The drain of each device unit is connected to the wafer substrate, that is, each device unit shares the drain. The gates of each device unit are connected in parallel to form a unified gate control node, thereby realizing the synchronous turn-on and turn-off of the three device units electrically. The field plate electrode of each device unit is connected to the source electrode, and the source electrode is grounded. This connection method allows the field plate electrode of the device unit to play the role of electric field modulation.

[0028] The field plate electrodes of the first device unit 2 and the second device unit 3 are connected to the source electrode across the unit, and the field plate electrode of the third device unit 4 is connected to the source electrode in the third region.

[0029] The trench extension direction of the first device unit 2 and the third device unit 4 is perpendicular to the trench extension direction of the second device unit 3.

[0030] In other words, this solution combines the field plate electrode design scheme of each device unit with the orthogonal trench design scheme of different device units. Through the joint control of the layout structure, the mechanical stress and electrical performance are optimized simultaneously, thereby solving the manufacturing bottleneck of large-size chips. At the same time, it reduces the parasitic resistance of the field plate connection line of the device output capacitor and increases the switching speed of the device.

[0031] The layout structure for mitigating wafer warpage of medium-voltage SGT-MOSFETs provided in this embodiment of the invention defines an alternating trench layout within a multi-unit parallel structure composed of a first device unit 2, a second device unit 3, and a third device unit 4. This collaboratively controls the distribution of mechanical stress and electric field at the layout level, effectively solving the wafer warpage problem caused by the accumulation of structural stress and weakening of rigidity during the manufacturing process of large-size medium-voltage SGT-MOSFET devices while reducing the parasitic interconnect resistance of the output capacitor.

[0032] Furthermore, the field plate electrode in the central region of the first device unit 2 is connected to the source electrode of the first device unit 2; the field plate electrodes at both ends of the first device unit 2 are connected across units to the source electrode of the third device unit 4.

[0033] Furthermore, the field plate electrode in the central region of the second device unit 3 is connected to the source electrode of the second device unit 3; the field plate electrode of the second device unit 3 near the end of the first device unit 2 is connected to the source electrode of the first device unit 2, and the field plate electrode of the second device unit 3 near the end of the third device unit 4 is connected to the source electrode of the third device unit 4.

[0034] Furthermore, the field plate electrodes in the central region and at both ends of the third device unit 4 are all connected to the source electrode of the third device unit 4.

[0035] Specifically, this design not only connects the field plate electrode in the central region to its own source electrode within each device unit (first device unit 2, second device unit 3, and third device unit 4), but also adds field plate electrodes at both ends of the device unit. This means adding additional field plate-source connection points at the edge regions of the device unit. This layout significantly enhances the electrical connection density between the field plate electrode (shielding gate) and the source electrode (source), more effectively suppresses the charge coupling effect caused by potential difference changes between the shielding gate and the semiconductor substrate (drain region), and reduces the output capacitance C during device switching. OSS The parasitic resistance of the field plate electrodes is reduced, thereby increasing the switching speed of the device. This design, while maintaining the basic device structure and process, achieves improved wafer warpage and enhanced device switching performance through innovative layout interconnection.

[0036] Furthermore, based on the concept that different trench orientations can offset wafer warpage, the trenches of the first device unit 2 and the third device unit 4 extend along a first preset direction, and the trench of the second device unit 3 extends along a second preset direction. The lengths of the first device unit 2 and the third device unit 4 in the second preset direction are equal, and are equal to half the length of the second device unit 3 in the second preset direction.

[0037] Among them, the trench of the first device unit 2 is the first trench array 23, the trench of the second device is the second trench array 33, and the trench of the third device is the third trench array 43.

[0038] Specifically, this invention defines two basic trench orientation configuration modes, both of which serve the aforementioned cross-unit field plate connection system, together constituting a complete stress management solution: In one embodiment of the present invention, participants Figure 3 , Figure 4 The trenches of the first device unit 2 and the third device unit 4 extend laterally (X direction), and the trench of the second device unit 3 extends longitudinally (Y direction). The trench orientation matches the field plate electrode partitioning and cross-unit connection scheme of each device unit described above. Furthermore, the above-mentioned dimensional design helps to balance the stress introduced by the deep trench structure, thereby suppressing wafer warpage.

[0039] In another embodiment of the present invention, the trenches of the first device unit 2 and the third device unit 4 extend longitudinally (Y direction), and the trenches of the second device unit 3 extend laterally (X direction). When this trench setting direction is adopted, the connection relationship of the field plate electrodes needs to be adapted to ensure that the synergistic effect of electric field modulation and stress management is maintained.

[0040] Furthermore, the active region metal orientation of the edge field plate electrodes connecting the two ends of the first device unit 2 is perpendicular to the trench extension direction of the first device unit 2; the active region metal orientation of the edge field plate electrodes connecting the two ends of the third device unit 4 is perpendicular to the trench extension direction of the third device unit 4.

[0041] Specifically, this design further reduces the overall stress on the wafer and decreases wafer warpage.

[0042] like Figure 2 As shown, furthermore, multiple pressure-resistant rings 8 are provided at intervals in the first region located around the first device unit 2, the second region located around the second device unit 3, and the third region located around the third device unit 4.

[0043] In this embodiment of the invention, the multi-turn withstand voltage ring 8 is specifically set to 6 turns. The withstand voltage ring 8 is used to alleviate the transverse electric field in the terminal area and ensure that the expected breakdown voltage is achieved.

[0044] like Figure 1 , Figure 2 As shown, the gate metal 5 of the gate is further disposed around the overall device composed of the first device unit 2, the second device unit 3 and the third device unit 4, and passes through the area between the first device unit 2 and the second device unit 3, as well as the area between the second device unit 3 and the third device unit 4.

[0045] The sources of the first device unit 2, the second device unit 3, and the third device unit 4 are interconnected during packaging via wire bonding, ultimately connecting to the same source pin in the package. A gate pad 51 is located at the center of the bottom of the device for connecting the package gate pin. The gate metal 5 is arranged around the entire device unit, passing through the area between the first device unit 2 and the second device unit 3 to form a gate electrode 52 between the first device unit and the second device unit; and passing through the area between the second device unit 3 and the third device unit 4 to form a gate electrode 53 between the second device unit and the third device unit, thereby realizing the interconnection of the gates of each device unit.

[0046] The thin line arranged vertically in the middle of the first device unit 2 is the connection point 21 between the field plate electrode and the source electrode of the first device unit; the thin line arranged horizontally in the middle of the second device unit 3 is the connection point 31 between the field plate electrode and the source electrode of the second device unit; and the thin line arranged vertically in the middle of the third device unit 4 is the connection point 41 between the field plate electrode and the source electrode of the third device unit.

[0047] The third device also has metal 9 surrounding the source electrode of the third device unit at both ends.

[0048] like Figures 1-4 As shown, in this embodiment, the first device unit 2, the second device unit 3, and the third device unit 4 are all disposed within the peripheral cutoff ring 1. By setting an independent cutoff ring around each device unit, the peripheral cutoff ring 1 is divided into a first region, a second region, and a third region in sequence, so that the first device unit 2, the second device unit 3, and the third device unit 4 are located in the first region, the second region, and the third region, respectively, thereby forming physical isolation and effectively suppressing the transverse leakage current between each device unit.

[0049] The first device unit 2 includes a source electrode 22 of the first device unit, the second device unit 3 includes a source electrode 32 of the second device unit, and the third device unit 4 includes a source electrode 42 of the third device unit.

[0050] Regarding the field plate electrode layout, the field plate electrode at the left edge of the first device unit 2 is connected across the unit to the source electrode of the third device unit 4, and the field plate electrode at the right edge is connected similarly; the field plate electrode at the lower edge of the second device unit 3 is connected to the source electrode 6 led out from the first device unit below it. The gate metal 5 is led out from the gate pad, connected to the first device unit 2, and wired along the outside of the entire device unit. The gate metal 5 also includes a gate electrode 52 between the first device unit and the second device unit, and a gate electrode between the second device unit 3 and the third device unit 4, thereby realizing the parallel connection and synchronous switching control of the gates of each device unit.

[0051] The field plate electrodes at the left and right edges of the third device unit 4 are not connected across units, but are directly connected to their own source electrodes. Meanwhile, the field plate electrode at the upper edge of the second device unit 3 is connected to the source electrode 7 led out from the third device unit. After connecting the first device unit 2 and the second device unit 3, the gate metal 5 continues to extend to the third device unit 4 and passes through the area between the second device unit 3 and the third device unit 4 to achieve connection with the second device unit 3, thereby completing the parallel connection of the gates of all device units.

[0052] Regarding the trench layout, the first trench array 23 extends along the X direction, the second trench array 33 extends along the Y direction, and the third trench array 43 extends along the X direction. This trench layout, in conjunction with the multi-unit parallel structure and field plate electrode connection network in this invention, systematically regulates and counteracts the internal process stress of the chip, thereby effectively suppressing wafer warpage.

[0053] The layout structure for mitigating wafer warpage of medium-voltage SGT-MOSFETs of the present invention is applicable to SGT-MOSFET devices of 150V~250V, and is especially suitable for situations where the chip size is large and the area of ​​a single chip is significant.

[0054] Specifically, this invention targets large-size 150V~250V SGT-MOSFET devices manufactured on 8-inch wafers, with fewer than 900 MOSFETs per wafer per chip area. Through a unique layout design, a stress compensation mechanism is introduced from the device design stage, effectively suppressing overall wafer deformation caused by the combined effects of accumulated stress from deep trenches and thick field oxygen, and reduced rigidity of the large-size chip. Simultaneously, this layout structure reduces the parasitic resistance of the device's output capacitor connection lines, increasing the device's switching speed. Without excessively increasing process complexity or cost, this layout structure aims to improve wafer flatness and process window in key processes such as photolithography, ensuring the manufacturing feasibility and product reliability of large-size SGT devices.

[0055] Furthermore, this invention is not a simple orthogonal trench structure design, but a set of design rules specifically designed for medium-voltage (150~250V), large-size (gross die less than 900), multi-unit parallel SGT-MOSFET device structures, which coordinates the trench direction with the field plate network. The core of this rule is that, in order to cope with wafer warpage caused by specific process stresses, this invention not only specifies a specific alternation sequence of trench directions between different device units, but also mandates that it must be implemented and optimized together with a predefined, asymmetric cross-unit field plate potential connection system.

[0056] This overall scheme, which forcibly couples and coordinates the "spatial orientation layout" with the "circuit potential interconnection", aims to achieve synchronous optimization of mechanical stress and electrical performance through joint control of the layout architecture, thereby solving the manufacturing bottleneck problem of large-size chips. At the same time, it reduces the parasitic resistance of the field plate connection line of the device output capacitor, increases the switching speed of the device, and the collaborative system as a whole has substantial characteristics that are different from the existing single orthogonal trench design.

[0057] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions within the technical scope disclosed in the present invention should be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A layout structure for mitigating wafer warpage in medium-voltage SGT-MOSFETs, characterized in that, include: A peripheral cutoff ring, and a first device unit, a second device unit, and a third device unit sequentially disposed inside the peripheral cutoff ring; Each device unit is surrounded by an independent cutoff ring, which partially overlaps with the peripheral cutoff ring to divide the peripheral cutoff ring into a first region, a second region, and a third region in sequence. The first device unit, the second device unit, and the third device unit are located in the first region, the second region, and the third region, respectively. The drains of the first device unit, the second device unit, and the third device unit are all connected to the wafer substrate, the gates are connected in parallel, and the field plates are all connected to the source electrodes. The field plate electrodes of the first device unit and the second device unit are connected to the source electrode across the unit, and the field plate electrode of the third device unit is connected to the source electrode in the third region. The trench extension direction of the first device unit and the third device unit is perpendicular to the trench extension direction of the second device unit.

2. The layout structure for mitigating wafer warpage of medium-voltage SGT-MOSFET according to claim 1, characterized in that, The field plate electrode in the central region of the first device unit is connected to the source electrode of the first device unit; the field plate electrodes at both ends of the first device unit are connected across units to the source electrode of the third device unit.

3. The layout structure for mitigating wafer warpage of medium-voltage SGT-MOSFET according to claim 2, characterized in that, The field plate electrode in the central region of the second device unit is connected to the source electrode of the second device unit; the field plate electrode of the second device unit near the end of the first device unit is connected to the source electrode of the first device unit, and the field plate electrode of the second device unit near the end of the third device unit is connected to the source electrode of the third device unit.

4. The layout structure for mitigating wafer warpage of the medium-voltage SGT-MOSFET according to claim 5, characterized in that, The field plate electrodes in the central region and at both ends of the third device unit are all connected to the source electrode of the third device unit.

5. The layout structure for mitigating wafer warpage of the medium-voltage SGT-MOSFET according to claim 4, characterized in that, The grooves of the first device unit and the third device unit extend along a first preset direction, and the groove of the second device unit extends along a second preset direction; the lengths of the first device unit and the third device unit in the second preset direction are equal, and are equal to half the length of the second device unit in the second preset direction.

6. The layout structure for mitigating wafer warpage of the medium-voltage SGT-MOSFET according to claim 5, characterized in that, The active region metal orientation of the edge field plate electrodes connecting the two ends of the first device unit is perpendicular to the trench extension direction of the first device unit; the active region metal orientation of the edge field plate electrodes connecting the two ends of the third device unit is perpendicular to the trench extension direction of the third device unit.

7. The layout structure for mitigating wafer warpage of medium-voltage SGT-MOSFET according to claim 1, characterized in that, Multiple pressure-resistant rings are provided at intervals in the first region located around the first device unit, the second region located around the second device unit, and the third region located around the third device unit.

8. The layout structure for mitigating wafer warpage of medium-voltage SGT-MOSFET according to claim 1, characterized in that, The gate metal of the gate is disposed around the periphery of the overall device composed of the first device unit, the second device unit and the third device unit, and passes through the area between the first device unit and the second device unit, and the area between the second device unit and the third device unit.

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