A method for forming a semiconductor structure and a semiconductor structure

By forming multilayer photolithographic patterning layers and sidewall layers in a semiconductor structure, the problems of process limitations and complex processes are solved, achieving smaller trench step size and higher pattern transfer accuracy, reducing costs, and making it suitable for advanced integrated circuit manufacturing.

CN122373701APending Publication Date: 2026-07-10
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Filing Date
2026-04-14
Publication Date
2026-07-10

AI Technical Summary

Technical Problem

In existing technologies, pattern step size formation is limited by process technology and the formation process is complex. Extreme ultraviolet lithography equipment is expensive and has limited production capacity, making it difficult to be widely adopted in the semiconductor manufacturing field.

Method used

By sequentially forming a first photolithographic pattern layer, a first bump, a second photolithographic pattern layer, a second bump, and a third bump, and combining the self-aligned patterning processing of the first sidewall layer and the second sidewall layer, a second hard mask layer is formed and the dielectric layer is etched, simplifying the process flow and breaking through the resolution limit of photolithography equipment.

Benefits of technology

Without relying on extreme ultraviolet lithography equipment, the process flow is simplified, smaller trench step size is achieved, the fidelity of pattern transfer and trench position accuracy are improved, and the process complexity and manufacturing cost are reduced, making it suitable for large-scale advanced integrated circuit manufacturing.

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Abstract

The application provides a semiconductor structure forming method and a semiconductor structure. The method comprises the following steps: providing an initial substrate comprising a dielectric layer, a first metal oxide layer, a first sacrificial layer, a second metal oxide layer, a second sacrificial layer and a first stack layer; forming a first photoetching pattern layer on the side of the first stack layer away from the dielectric layer; etching the second sacrificial layer to form a first bump; forming a second photoetching pattern layer on the side of the first bump away from the dielectric layer; etching the second metal oxide layer to form a second bump and a third bump; forming a first sidewall layer; performing a photoetching process on the first sidewall layer to form a first hard mask layer; forming a second sidewall layer; removing part of the second sidewall layer to form a second hard mask layer; and etching the dielectric layer to form a plurality of grooves. Through twice exposure and corresponding hard mask etching, and cooperating with a self-aligned quadruple pattern technology, the process limitation can be overcome, and the step length of the adjacent grooves formed is less than 22 nm.
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