Wafer cutting method, wafer cutting system, and chip

Abstract

Disclosed are a wafer cutting method, a wafer cutting system and a chip. The wafer cutting method comprises: obtaining a wafer provided with a die; forming a first groove of a sealing ring surrounding the die on a cutting lane adjacent to the die; forming a second groove surrounding the sealing ring on the cutting lane; wherein the second groove is located on a side of the first groove away from the sealing ring; and cutting the wafer along a cutting path located on the cutting lane and on a side of the second groove away from the first groove to separate out the die. The embodiments of the present disclosure can reduce the possibility of cracks extending to the inside of the chip in subsequent processes, thereby facilitating the protection of the structural integrity and function of the chip and improving the reliability, service life and yield of the chip.

Description

Technical Field

[0001] This disclosure relates to semiconductor technology, and in particular to a wafer dicing method, a wafer dicing system, and a chip. Background Technology

[0002] In chip packaging, wafer dicing is an essential and crucial process. Related technologies typically employ mechanical dicing, which is prone to edge chipping and microcracks. These cracks can propagate into the chip during subsequent processes, affecting its structural integrity and functionality, and reducing its reliability and lifespan. Summary of the Invention

[0003] To address the aforementioned technical problems, this disclosure provides a wafer dicing method, a wafer dicing system, and a chip.

[0004] According to one aspect of the present disclosure, a wafer dicing method is provided, comprising: Obtain a wafer with grains. A first groove is formed on the cutting channel adjacent to the grain to form a sealing ring around the grain; A second groove is formed around the sealing ring on the cutting channel; wherein the second groove is located on the side of the first groove away from the sealing ring; The wafer is cut along a cutting path located on the side of the second groove away from the first groove to separate the grains.

[0005] According to another aspect of the present disclosure, a wafer dicing system is provided, the wafer dicing system including a worktable, a laser device, a mechanical dicing device, and a computer; The worktable is used to hold the wafers with grains prepared on them; The computer includes a processor, the processor being configured to: Control the image sensor to acquire images including the wafer; Based on the image, the laser device is controlled to form a first groove of a sealing ring around the grain on the cutting track adjacent to the grain; Based on the image, the laser device is controlled to form a second groove around the sealing ring on the cutting path; wherein the second groove is located on the side of the first groove away from the sealing ring; Based on the image, the mechanical cutting device is controlled to cut the wafer along a cutting path located on the side of the second groove away from the first groove, in order to separate the grains.

[0006] According to another aspect of the present disclosure, a chip is provided, including a die for packaging into the chip, the die being obtained by applying the above-described wafer dicing method to a wafer.

[0007] Based on the wafer dicing method, wafer dicing system, and chip provided in the above embodiments of this disclosure, for a wafer with a die, a first groove and a second groove can be formed on the dicing path adjacent to the die to form a sealing ring around the die. The wafer can be diced along a dicing path located on the side of the second groove away from the first groove to separate the die. It should be noted that the first groove is located between the dicing path and the sealing ring of the die, and the second groove is also located between the dicing path and the sealing ring of the die. Even if chipping and microcracks occur due to wafer dicing along the dicing path, at the second groove, the driving force for crack propagation will be reduced or changed in direction (e.g., it will propagate along the edge of the second groove instead of towards the die). At the first groove, the driving force for crack propagation will also be reduced or changed in direction (e.g., it will propagate along the edge of the first groove instead of towards the die). In this way, the second groove and the first groove can play a good role in isolating cracks, making it difficult for cracks to propagate to the sealing ring of the die, let alone into the interior of the die. Therefore, the embodiments of this disclosure can reduce the possibility of cracks propagating into the chip during subsequent processes, thereby helping to ensure the structural integrity and function of the chip, and improving the chip's reliability, lifespan and yield. Attached Figure Description

[0008] Figure 1 This is a schematic flowchart of a wafer dicing method provided by some exemplary embodiments of this disclosure.

[0009] Figure 2 This is a schematic diagram of the structure of a wafer with grains prepared in some exemplary embodiments of this disclosure.

[0010] Figure 3 This is a schematic diagram of the structure of a wafer with grains prepared in some other exemplary embodiments of this disclosure.

[0011] Figure 4 This is a schematic diagram of the structure of a wafer with grains prepared in some exemplary embodiments of the present disclosure.

[0012] Figure 5 This is a schematic flowchart of a wafer dicing method provided by some other exemplary embodiments of this disclosure.

[0013] Figure 6 This is a schematic diagram of the structure of a wafer dicing system provided in some exemplary embodiments of this disclosure. Detailed Implementation

[0014] To explain this disclosure, exemplary embodiments of the disclosure will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the disclosure, and not all of them. It should be understood that the disclosure is not limited to exemplary embodiments.

[0015] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0016] Application Overview Wafer dicing refers to separating the densely packed dies on a wafer. Subsequent processes such as die bonding, dispensing, and ball-mounting are then performed on the separated dies to ultimately obtain a packaged chip.

[0017] In related technologies, wafers are typically cut mechanically. This process applies high stress to brittle materials like silicon, easily leading to edge chipping and microcracks, especially in wafers at advanced process nodes, which are more prone to cracking due to the use of materials with ultra-low dielectric constants. In developing this disclosure, the inventors discovered that cracks can propagate into the chip during subsequent processes, affecting its structural integrity and functionality, and reducing its reliability and lifespan. Therefore, it is necessary to take measures to prevent crack propagation into the chip, thereby ensuring its structural integrity and functionality, and improving its reliability and lifespan.

[0018] Exemplary System To facilitate understanding of the following text, a brief introduction to wafers, grains, and dicing channels will be given first.

[0019] A wafer is a circular thin film made from ultra-high purity single crystal silicon, or semiconductor compounds such as gallium arsenide and silicon carbide, through processes such as crystal growth, slicing, chamfering, grinding, etching, polishing, and cleaning. It serves as the basic substrate for manufacturing semiconductor devices.

[0020] A die is a fully functional circuit unit manufactured on a wafer through processes such as thin film deposition, photolithography, etching, ion implantation, and thermal treatment. A die is typically an unpackaged, independent bare die. A die can also be called a bare die or simply a die.

[0021] A scribe track is a grid-like network of stripes on a wafer that physically separates the individual grains on the wafer and provides the physical cutting path for wafer dicing. Scribe tracks can also be called scribe lines.

[0022] Exemplary methods Embodiments of this disclosure provide a wafer dicing method. For example... Figure 1As shown, the wafer dicing method provided in the embodiments of this disclosure may include steps 110, 120, 130 and 140.

[0023] Step 110: Obtain a wafer with prepared grains.

[0024] Optionally, processes such as thin film deposition, photolithography, etching, ion implantation, and heat treatment can be repeatedly performed on the wafer to fabricate a large number of repeating circuit units on the wafer, where each circuit unit can be a grain, thereby obtaining a wafer with grains. That is, for a wafer with grains, the number of grains can be multiple, such as hundreds or thousands.

[0025] As an example, Figures 2 to 4 The diagram shows a partial schematic of a wafer with grains, including four grains. For ease of description, the grain located in the upper left corner will be referred to as the first grain, the grain located in the upper right corner as the second grain, the grain located in the lower left corner as the third grain, and the grain located in the lower right corner as the fourth grain.

[0026] Optionally, such as Figures 2 to 4 As shown, the third die may include a core circuit 210 and a sealing ring 220 surrounding the core circuit 210. The core circuit 210 is used to realize the complete function of the die. The sealing ring 220 is mainly used for: (1) stress isolation; (2) preventing moisture, pollutants, etc. from entering; and (3) structural reinforcement. In this way, the sealing ring 220 can protect the core circuit 210.

[0027] It should be noted that since the processing technology for each grain is similar, the following text mainly focuses on the processing technology for a single grain (e.g., the third grain).

[0028] Step 120: On the cutting path adjacent to the grain, a first groove is formed to form a sealing ring around the grain.

[0029] Optionally, a dicing adjacent to a grain refers to the stripe region on the wafer that is adjacent to the grain among all stripe regions belonging to a dicing. Unless otherwise specified, dicings in the following text refer to dicings adjacent to the grain. Figure 2 , Figure 3 For example, the cutting channel adjacent to the third grain can refer to the strip-shaped area distributed on the upper and right sides of the third grain, with the dashed line 225 as the center line. That is, the cutting channel adjacent to the third grain can be the strip-shaped area located between the sealing ring 220 of the third grain and the sealing ring 220 of other grains.

[0030] Optionally, a non-mechanical grooving method can be used to form a first groove on the grooving path that forms a sealing ring around the grain, thereby avoiding the introduction of mechanical stress during the formation of the first groove. Non-mechanical grooving methods include, but are not limited to, laser grooving, plasma grooving, and electron beam grooving. If the non-mechanical grooving method is specifically laser grooving, the first groove can also be referred to as 1st laser grooving. Figure 2 , Figure 3 For example, for the third grain, a first groove 230 can be formed around the sealing ring 220 on the cutting path. The first groove 230 can be located on the lower left side of the dashed line 225.

[0031] Step 130: A second groove is formed around the sealing ring on the cutting track; wherein the second groove is located on the side of the first groove away from the sealing ring.

[0032] Alternatively, a non-mechanical grooving method can be used to form a second groove around the sealing ring on the cutting path, located on the side of the first groove furthest from the sealing ring, to avoid introducing mechanical stress during the formation of the second groove. If the non-mechanical grooving method is specifically laser grooving, the second groove can also be referred to as 2nd laser grooving. Figure 2 , Figure 3 For example, for the third grain, a first groove 230 and a second groove 240 can be formed sequentially. The first groove 230 can be located between the sealing ring 220 and the second groove 240, and the second groove 240 and the first groove 230 can be set with a gap.

[0033] Step 140: Cut the wafer along the cutting path located on the side of the second groove away from the first groove to separate the grains.

[0034] Optionally, a cutting path can be defined on the side of the second groove furthest from the first groove on the kerf. For example, the centerline of the kerf can be used as the cutting path. However, the cutting path is not limited to the centerline of the kerf; there can be a slight offset between the cutting path and the centerline of the kerf. Using a cutting device, the wafer can be cut along the cutting path to separate the grains. This cutting device is, for example, but not limited to, a mechanical cutting device that uses a high-speed rotating ultra-thin diamond blade to cut the wafer and separate the grains. Figure 2 , Figure 3 For example, for the third grain, the dashed line 225 can be defined as the cutting path, and a high-speed rotating ultrathin diamond blade can be used to cut the wafer along the dashed line 225 to separate the third grain. The first, second, and fourth grains can be separated in a similar way, which will not be described in detail here.

[0035] In the embodiments of this disclosure, for a wafer with grains, a first groove and a second groove can be formed on the dicing path adjacent to the grains to form a sealing ring around the grains. The wafer is then cut along a dicing path located on the side of the dicing path away from the first groove, thereby separating the grains. It should be noted that the first groove is located between the dicing path and the sealing ring of the grains, and the second groove is also located between the dicing path and the sealing ring of the grains. Even if edge chipping and microcracks occur due to wafer cutting along the dicing path, the driving force for crack propagation is reduced or changed in direction at the second groove (e.g., it changes to propagation along the edge of the second groove instead of towards the grains). At the first groove, the driving force for crack propagation is also reduced or changed in direction (e.g., it changes to propagation along the edge of the first groove instead of towards the grains). Thus, the second groove and the first groove can effectively isolate the cracks, making it difficult for the cracks to propagate to the sealing ring of the grains, let alone into the interior of the grains. Therefore, the embodiments of this disclosure can reduce the possibility of cracks propagating into the chip during subsequent processes, thereby helping to ensure the structural integrity and function of the chip, and improving the chip's reliability, lifespan and yield.

[0036] In some optional examples, the first slot and the second slot can satisfy: The first groove has a rounded or right-angle transition at the corner corresponding to the corner of the sealing ring. The second groove has a rounded or right-angle transition at the corner corresponding to the corner of the sealing ring.

[0037] In other words, the first and second slots can satisfy one of the following four conditions: Case 1: The body of the first groove has a rounded transition at the corner corresponding to the corner of the sealing ring, while the body of the second groove has a right-angle transition at the corner corresponding to the corner of the sealing ring.

[0038] Scenario 2: The body of the first groove has a rounded transition at the corner corresponding to the corner of the sealing ring, and the body of the second groove has a rounded transition at the corner corresponding to the corner of the sealing ring.

[0039] Case 3: The body of the first groove has a right-angle transition at the corner corresponding to the corner of the sealing ring, while the body of the second groove has a rounded corner transition at the corner corresponding to the corner of the sealing ring.

[0040] Case 4: The body of the first groove has a right-angle transition at the corner corresponding to the corner of the sealing ring, and the body of the second groove has a right-angle transition at the corner corresponding to the corner of the sealing ring.

[0041] Generally speaking, a corner refers to a location where at least two surfaces, edges, or structural components intersect. Figure 2 , Figure 3For example, for the third grain, the corner of the sealing ring 220 can be the area selected by the dashed box 250; the area on the body of the first groove 230 corresponding to the corner of the sealing ring can be the area selected by the dashed box 260; the area on the body of the second groove 240 corresponding to the corner of the sealing ring can be the area selected by the dashed box 270.

[0042] In some embodiments, such as Figure 2 As shown, the area selected by dashed box 260 can have rounded corners, and the area selected by dashed box 270 can have right-angled corners. That is, the first slot 230 can use a rounded corner design, and the second slot 240 can use a right-angled design. Here, the radius of the rounded corners of the area selected by dashed box 260 can be determined according to the actual situation, and this disclosure does not limit it.

[0043] In other embodiments, such as Figure 3 As shown, the areas selected by dashed box 260 can have rounded corners, and the areas selected by dashed box 270 can also have rounded corners. That is, both the first groove 230 and the second groove 240 can adopt a rounded corner design. Here, the rounded corner radii of the areas selected by dashed box 260 and dashed box 270 can be determined according to the actual situation, and this disclosure does not impose any limitations on this. Thus, the rounded corner radii of the areas selected by dashed box 260 and dashed box 270 can be the same or different.

[0044] In the embodiments of this disclosure, a first groove and a second groove can be formed on the cutting path. Either the first groove or the second groove can be designed with rounded corners or right angles. If a rounded corner design is used, it helps to release stress on the corresponding part of the body at the corner of the sealing ring, avoiding stress concentration, improving stress distribution, thereby reducing the driving force for crack propagation towards the grain. This further reduces the possibility of cracks propagating into the chip during subsequent processes, thus helping to further ensure the structural integrity and function of the chip, and improving the chip's reliability, lifespan, and yield. If a right angle design is used, it helps to reduce processing difficulty.

[0045] In some optional examples, the depth of the first slot can be greater than the depth of the second slot.

[0046] Optionally, the depth of the first trench refers to the distance between the top surface of the wafer and the bottom of the first trench, and the depth of the second trench refers to the distance between the top surface of the wafer and the bottom of the second trench. The depth of the first trench can be 1.1 times, 1.2 times, 1.5 times, 2 times, or other multiples of the depth of the second trench, which will not be listed here.

[0047] In the embodiments of this disclosure, the first trench is closer to the sealing ring of the wafer than the second trench, so the depth of the first trench can be greater than the depth of the second trench. Thus, compared to the second trench, the first trench can more effectively prevent cracks from propagating from different depths and can more effectively eliminate the energy generated by crack propagation. This further reduces the possibility of cracks propagating into the chip during subsequent processes, thereby helping to further ensure the structural integrity and functionality of the chip, and improving the chip's reliability, lifespan, and yield.

[0048] The above describes the case where the depth of the first slot is greater than the depth of the second slot. In actual implementation, the depth of the first slot can also be equal to the depth of the second slot.

[0049] In some optional examples, step 120 may include: At least two first grooves are formed on the cutting track, surrounding the sealing ring and spaced apart.

[0050] Optionally, a non-mechanical grooving method can be used to form N first grooves spaced apart around the sealing ring on the cutting path; where N can be an integer greater than or equal to 2. Figure 4 For example, for the third grain, N first grooves 230 can be formed around the sealing ring 220. Among the N first grooves 230, the first groove 230 adjacent to the sealing ring 220 can adopt a rounded corner design, and the first groove 230 not adjacent to the sealing ring 220 (e.g., the first groove 230 adjacent to the second groove 240) can adopt a rounded corner design or a right angle design.

[0051] In the embodiments of this disclosure, at least two first grooves are formed around the sealing ring and spaced apart on the cutting path, wherein each first groove can isolate the crack, thereby further reducing the possibility of the crack extending into the chip in subsequent processes, which in turn helps to further ensure the structural integrity and function of the chip, and improve the chip's reliability, service life and yield.

[0052] In some alternative examples, at least two first grooves can satisfy the following condition: for any two adjacent first grooves, the depth of the first groove closer to the sealing ring is greater than the depth of the first groove farther from the sealing ring.

[0053] Optionally, when N first grooves are formed around the sealing ring and spaced apart on the dicing path, the depths of the N first grooves can be different. Specifically, the depth of the first groove closer to the sealing ring is greater, and the depth of the first groove farther from the sealing ring is smaller. In this way, compared with the first groove farther from the sealing ring, the first groove closer to the sealing ring can more effectively prevent cracks from propagating from different depths, and can more effectively eliminate the energy generated by crack propagation. That is, at least two first grooves can intercept cracks layer by layer, and the interception effect gradually strengthens, thereby further reducing the possibility of cracks propagating into the chip in subsequent processes. This helps to further ensure the structural integrity and function of the chip, and improve the chip's reliability, lifespan, and yield.

[0054] The above describes the case where at least two first grooves have different depths. In practice, at least two first grooves can also have the same depth. As an example, along the direction away from the sealing ring, the depths of the N first grooves are denoted as d1, d2, d3, ..., dN, and the depth of the second groove is denoted as s. Then we have: d1≥d2≥d3≥……≥dN≥s.

[0055] In some optional examples, at least one of the following can be adapted to the width dimension of the cut track: The dimensions of the first slot; The dimensions of the second slot; The total number of slots in the first slot; The distance between two adjacent first grooves; The distance between the first and second slots adjacent to the second slot.

[0056] Optionally, the width of the kerf can refer to the distance between the two sealing rings of two adjacent grains. Figure 2 For example, for the third grain, the width of the kerf can refer to the distance between the sealing ring 220 of the third grain and the sealing ring 220 of the fourth grain, or the distance between the sealing ring 220 of the third grain and the sealing ring 220 of the first grain.

[0057] Optionally, the groove size of the first groove may include the width of the first groove. Here, the larger the width of the cutting track, the larger the width of the first groove can be; the smaller the width of the cutting track, the smaller the width of the first groove can be.

[0058] Optionally, the groove size of the second groove may include the width of the second groove. Here, the larger the width of the cutting track, the larger the width of the second groove can be; the smaller the width of the cutting track, the smaller the width of the second groove can be.

[0059] Optionally, the total number of the first slots is N as mentioned above. Here, the larger the width of the cutting track, the larger the value of N can be; the smaller the width of the cutting track, the smaller the value of N can be.

[0060] Optionally, the larger the width of the cutting channel, the greater the distance between two adjacent first grooves; the smaller the width of the cutting channel, the smaller the distance between two adjacent first grooves. Furthermore, the larger the width of the cutting channel, the greater the distance between the first and second grooves adjacent to the second groove; the smaller the width of the cutting channel, the smaller the distance between the first and second grooves adjacent to the second groove.

[0061] In the embodiments of this disclosure, the parameters associated with the first groove and / or the second groove can be adapted to the width of the dicing channel, which helps to ensure the rationality of these parameters and thus effectively reduces the possibility of cracks propagating into the chip during subsequent processes.

[0062] In some optional examples, step 120 may include: Using laser equipment, a first groove is formed on the cutting track to create a sealing ring around the grain; Step 130, forming a second groove around the sealing ring on the cutting path, may include: Using laser equipment, a second groove is formed around the sealing ring on the cutting track; Step 140, cutting the wafer along the dicing path located on the side of the second groove furthest from the first groove, includes: The wafer is cut using a mechanical cutting device along a cutting path located on the side of the second groove away from the first groove.

[0063] Alternatively, laser equipment is a precision machining device that uses a laser beam to ablate or etch grooves into the kerf track on a wafer. Laser equipment includes, but is not limited to, laser grooving machines. Mechanical cutting equipment is a precision machining device that uses a high-speed rotating ultra-thin diamond blade to cut into the kerf track on a wafer through physical contact and mechanical grinding. Mechanical cutting equipment includes, but is not limited to, abrasive wheel cutting machines.

[0064] In the embodiments of this disclosure, a laser device can be used to laser-etch grooves on the dicing track to form a first groove and a second groove around the sealing ring. This avoids introducing mechanical stress during the formation of the first and second grooves, thus preventing cracks caused by mechanical stress. Subsequently, a cutting path can be determined on the side of the dicing track away from the first groove, and a laser device can be used to laser-etch grooves along the cutting path. Guided by the grooves etched in this laser etching, a mechanical cutting device can be used to mechanically cut along the cutting path to separate the die from the wafer. In this way, wafer cutting can be effectively achieved through the coordinated work of the laser device and the mechanical cutting device, minimizing the possibility of cracks propagating into the chip during subsequent processes.

[0065] In some optional examples, such as Figure 5 As shown, the wafer dicing method provided in the embodiments of this disclosure may further include steps 510, 520 and 530.

[0066] Step 510: Remove the residue from the first and second tanks.

[0067] Generally, the first and second tanks formed using laser equipment contain a lot of residue, such as, but not limited to, charred organic matter, microparticles, and spatter. If these residues are not treated, they may cause a series of serious reliability, electrical, and process problems, ultimately affecting the chip's reliability, lifespan, and yield. Therefore, the first and second tanks can be cleaned to remove these residues. For example, high-pressure deionized water can be used to rinse the first and second tanks. Alternatively, chemical cleaning solutions can be used for wet cleaning of the first and second tanks.

[0068] Step 520: Remove the modified layer caused by the laser equipment in the first and second slots.

[0069] Generally, the laser beam emitted by laser equipment causes a modified layer to form in the first and second grooves. This modified layer includes amorphous silicon, cracks, residual stress, and locally fused weld fragments. If this modified layer is not treated, cracks may propagate into the grains during subsequent mechanical cutting. Therefore, the modified layer can be removed. For example, it can be lightly wet-etched first, followed by deionization treatment.

[0070] Step 530: Apply a crack-resistant layer to the first and second grooves.

[0071] Optionally, after removing the modified layer, the first and second tanks can be dried, and the tank walls can be inspected for any remaining obvious modified layer, charred bands, residue, etc. If the tank walls of the first and second tanks do not have obvious modified layer, charred bands, residue, etc., an anti-cracking layer can be applied to the first and second tanks. The material of the anti-cracking layer is, for example, but not limited to, organic polymer materials such as polyimide and benzocyclobutene.

[0072] In the embodiments of this disclosure, the first and second trenches formed using laser equipment can not only remove residues and modified layers formed within the trenches, but also coat them with an anti-crack layer. This helps avoid reliability, electrical, and process problems that residues may cause, and also helps avoid crack propagation problems that the modified layer may cause. Furthermore, the anti-crack layer enhances crack resistance, further reducing the likelihood of cracks propagating into the chip during subsequent processes. This, in turn, helps to further ensure the structural integrity and functionality of the chip, improving its reliability, lifespan, and yield.

[0073] In summary, in the embodiments of this disclosure, multiple laser grooves (e.g., forming a first groove and a second groove) can be performed on the die to effectively alleviate the stress during mechanical cutting. Furthermore, at least the grooves near the sealing ring of the die can be designed with rounded corners to avoid stress concentration and smooth stress distribution. This effectively reduces the risk of crack propagation caused by mechanical cutting, improves chip reliability and yield, and effectively reduces the risk of chip corner chipping, improving chip edge quality and performance.

[0074] Exemplary System Embodiments of this disclosure also provide a wafer dicing system. For example... Figure 6 As shown, the wafer dicing system includes a worktable 610, a laser device 620, a mechanical dicing device 630, and a computer 640; The worktable 610 is used to hold the wafers with grains prepared on it; Computer 640 includes processor 6402, which is configured to: Control the image sensor 650 to acquire images, including those of the wafer; Based on the image, the laser device 620 is controlled to form a first groove on the cutting track adjacent to the grain, forming a sealing ring around the grain; Based on the image, the laser device 620 is controlled to form a second groove around the sealing ring on the cutting track; wherein the second groove is located on the side of the first groove away from the sealing ring; Based on the image, the mechanical cutting device 630 is controlled to cut the wafer along a cutting path located on the side of the second groove away from the first groove, in order to separate the grains.

[0075] Optionally, the stage 610 can support a wafer with prepared grains on its top. As an example, the wafer with prepared grains can be fixed to the stage 610 by means of vacuum adsorption, electrostatic adsorption, mechanical clamping, etc.

[0076] Optionally, the definitions of laser device 620 and mechanical cutting device 630 can be referred to the relevant description in the exemplary method section above, and will not be repeated here.

[0077] Optionally, the computer 640 can be a highly integrated and intelligent computer numerical control system used to schedule and control the laser device 620, the mechanical cutting device 630, the image sensor 650, etc., enabling them to work collaboratively. The image sensor 650 is, for example, but not limited to, a monocular camera or a binocular camera. The processor 6402 included in the computer 640 is, for example, but not limited to, a central processing unit (CPU). The processor 6402 can communicate with the image sensor 650, the laser device 620, and the mechanical cutting device 630 respectively; this communication connection can be either wired or wireless.

[0078] In embodiments of this disclosure, processor 6402 can send a first control signal to image sensor 650 to control image sensor 650 to acquire images of a wafer containing wafers. Processor 6402 can use image processing algorithms to process the images acquired by image sensor 650 to determine the specific locations of dicing paths adjacent to the wafer and the sealing rings of the wafers. Based on this, it can plan parameters such as the location, shape, and size (including width and depth) of the first groove, the location, shape, and size of the second groove, and information about the cutting path. Processor 6402 can send a second control signal carrying the planned parameters to laser device 620 to control laser device 620 to sequentially form the first and second grooves on the dicing paths according to the planned parameters. Additionally, processor 6402 can send a third control signal carrying information about the planned cutting path to laser device 620 to control mechanical cutting device 630 to cut the wafer along the cutting path to separate the wafers.

[0079] Thus, even if chipping and microcracks occur due to wafer dicing along the dicing path, the first and second grooves effectively isolate the cracks, making it difficult for them to propagate to the die's sealing ring, let alone into the die itself. Therefore, the embodiments of this disclosure reduce the likelihood of cracks propagating into the chip during subsequent processes, thereby helping to ensure the chip's structural integrity and functionality, and improving its reliability, lifespan, and yield.

[0080] In some alternative examples, the body of the first groove has a rounded transition at the corner corresponding to the corner of the sealing ring, and the body of the second groove has a right-angle transition at the corner corresponding to the corner of the sealing ring.

[0081] In some alternative examples, the body of the first groove has a rounded transition at the corner corresponding to the corner of the sealing ring, and the body of the second groove has a rounded transition at the corner corresponding to the corner of the sealing ring.

[0082] In some alternative examples, the body of the first groove has a right-angle transition at the corner corresponding to the corner of the sealing ring, and the body of the second groove has a rounded transition at the corner corresponding to the corner of the sealing ring.

[0083] In some alternative examples, the body of the first groove has a right-angle transition at the location corresponding to the corner of the sealing ring, and the body of the second groove has a right-angle transition at the location corresponding to the corner of the sealing ring.

[0084] In some optional examples, the depth of the first slot is greater than the depth of the second slot.

[0085] In some alternative examples, the processor 6402 is specifically configured to, when controlling the laser device 620 to form a first groove of a sealing ring around the grain on a kerf adjacent to the grain: The laser device 620 is controlled to form at least two first grooves on the cutting track, which are spaced apart and surround the sealing ring.

[0086] In some optional examples, at least two first grooves satisfy the following condition: for any two adjacent first grooves, the depth of the first groove closer to the sealing ring is greater than the depth of the first groove farther from the sealing ring.

[0087] In some optional examples, at least one of the following is adapted to the width dimension of the cut track: The dimensions of the first slot; The dimensions of the second slot; The total number of slots in the first slot; The distance between two adjacent first grooves; The distance between the first and second slots adjacent to the second slot.

[0088] Optionally, after separating the grains by dicing the wafer, a microscope or other inspection equipment can be used to check the integrity of the grain edges to ensure there are no cracks or chipping. Additionally, stress testing can be used to verify the effect of rounded corner design and multiple laser grooving on improving stress distribution.

[0089] In the system disclosed herein, the various optional embodiments, optional implementation methods and optional examples disclosed in the above exemplary method section can be flexibly selected and combined as needed to achieve the corresponding functions and effects, and this disclosure does not list them all.

[0090] The beneficial technical effects corresponding to the exemplary embodiments of this system can be found in the corresponding beneficial technical effects in the exemplary method section above, and will not be repeated here.

[0091] Exemplary chip Embodiments of this disclosure also provide a chip. The chip provided in the embodiments of this disclosure can be any type of chip, such as, but not limited to, intelligent driving chips, intelligent cockpit chips, image processing chips, etc. The chip provided in the embodiments of this disclosure may include a die for packaging into a chip, the die being obtained by wafer dicing using any of the wafer dicing methods described in the above embodiments. This helps reduce the possibility of cracks inside and at the edges of the chip, thereby helping to ensure the structural integrity and functionality of the chip, and improving the chip's reliability, lifespan, and yield.

[0092] The basic principles of this disclosure have been described above with reference to specific embodiments. However, the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0093] Various modifications and variations can be made to this disclosure without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A wafer dicing method, comprising: Obtain a wafer with grains. A first groove is formed on the cutting channel adjacent to the grain to form a sealing ring around the grain; A second groove is formed around the sealing ring on the cutting channel; wherein the second groove is located on the side of the first groove away from the sealing ring; The wafer is cut along a cutting path located on the side of the second groove away from the first groove to separate the grains.

2. The method according to claim 1, wherein, The body of the first groove has a rounded or right-angle transition at the corner corresponding to the corner of the sealing ring; The second groove has a rounded or right-angle transition at the corner corresponding to the corner of the sealing ring.

3. The method according to claim 1, wherein, The depth of the first groove is greater than the depth of the second groove.

4. The method according to any one of claims 1-3, wherein, The first groove, formed on the dicing channel adjacent to the grain, to create a sealing ring around the grain, includes: At least two first grooves are formed on the cutting channel, surrounding the sealing ring and spaced apart.

5. The method according to claim 4, wherein, At least two of the first grooves satisfy the following condition: for any two adjacent first grooves, the depth of the first groove closer to the sealing ring is greater than the depth of the first groove farther from the sealing ring.

6. The method according to claim 4, wherein, At least one of the following is compatible with the width dimension of the cutting track: The dimensions of the first groove; The dimensions of the second groove; The total number of the first slots; The distance between two adjacent first slots; The distance between the first slot and the second slot adjacent to the second slot.

7. The method according to any one of claims 1-3, wherein, The first groove, formed on the dicing channel adjacent to the grain, to create a sealing ring around the grain, includes: Using a laser device, the first groove, forming a sealing ring around the grain, is formed on the cutting path; The second groove formed on the cutting channel around the sealing ring includes: Using the laser device, a second groove is formed around the sealing ring on the cutting path; The cutting of the wafer along a cutting path located on the side of the second groove away from the first groove includes: The wafer is cut using a mechanical cutting device along the cutting path located on the side of the second groove away from the first groove, in the cutting channel.

8. The method according to claim 7, further comprising: Remove residues from the first and second tanks; Remove the modified layer created by the laser device in the first and second slots; Apply a crack-resistant layer to the first and second grooves.

9. A wafer dicing system, the wafer dicing system comprising a worktable, a laser device, a mechanical dicing device, and a computer; The worktable is used to hold the wafers with grains prepared on them; The computer includes a processor, the processor being configured to: Control the image sensor to acquire images including the wafer; Based on the image, the laser device is controlled to form a first groove of a sealing ring around the grain on the cutting track adjacent to the grain; Based on the image, the laser device is controlled to form a second groove around the sealing ring on the cutting path; wherein... The second groove is located on the side of the first groove away from the sealing ring; Based on the image, the mechanical cutting device is controlled to cut the wafer along a cutting path located on the side of the second groove away from the first groove, in order to separate the grains.

10. A chip comprising a die for packaging into the chip, the die being obtained by dicing a wafer using any one of the wafer dicing methods described in claims 1-8.

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