A method and system for identifying wafer dark cracks during wafer testing
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JINGLONG TECH SUZHOU
- Filing Date
- 2026-06-10
- Publication Date
- 2026-07-10
Smart Images
Figure CN122373774A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of wafer dark crack identification technology in wafer testing, and specifically to a method and system for identifying wafer dark cracks in wafer testing. Background Technology
[0002] Wafers are the fundamental material for semiconductor chip manufacturing, and their quality directly determines the performance and yield of the final chip. During wafer manufacturing and subsequent processing, dark cracks are a common and highly dangerous latent defect, typically manifesting as micro-cracks inside or on the surface of the wafer, which are difficult to detect early using conventional optical inspection. If not identified in time, dark cracks can easily propagate during subsequent processes such as thinning, dicing, and packaging, leading to wafer breakage or chip failure, resulting in significant cost losses and production delays. Therefore, achieving rapid and accurate identification of dark cracks during the wafer testing stage is crucial for improving the quality control level of semiconductor manufacturing.
[0003] However, existing methods for identifying wafer dark cracks still have significant shortcomings. Traditional optical imaging inspection techniques are easily affected by factors such as impurities, scratches, textures, and lighting conditions on the wafer surface, leading to misjudgments or missed detections. This is especially true for early dark cracks at the micrometer or even submicrometer level, where the resolution and contrast of optical imaging often fail to meet detection requirements, resulting in a low detection rate for micro-cracks. Some contact or destructive inspection techniques employ physical probe scanning, ultrasonic scanning, or stress testing. These methods typically require specialized inspection equipment and lengthy inspection times, making them incompatible with wafer batch testing processes. Furthermore, the equipment investment and maintenance costs are high, and they may cause secondary damage to the wafer. During wafer probing, conventional electrical tests primarily determine the electrical performance of the chip based on electrical parameters and functional logic. However, early dark cracks may not yet have caused obvious electrical failures or may only manifest as localized stress anomalies, making it difficult for test results to directly reflect the presence of dark cracks. Even if abnormal failure distributions are observed during electrical testing, existing systems lack mechanisms to automatically trigger physical re-inspections, making it easy for dark cracks to be missed and flow into subsequent processes. Furthermore, some improvement solutions attempt to optimize test templates or perform batch-to-batch yield analysis using historical test data, but their core remains offline statistics or post-event optimization, failing to respond in real-time to suspected dark crack signals during testing. Existing solutions generally separate electrical testing from physical measurement, failing to build a unified framework for equipment linkage and multi-dimensional data fusion, making it difficult to balance detection efficiency and identification accuracy. In summary, how to identify dark cracks in real-time, efficiently, and cost-effectively during wafer testing, especially accurately detecting minute dark cracks, while avoiding significant impact on normal testing cycles, has become a pressing technical problem in this field.
[0004] Therefore, existing technologies still need further development. Summary of the Invention
[0005] The purpose of this invention is to overcome the above-mentioned technical deficiencies and provide a method and system for identifying wafer dark cracks in wafer testing, so as to solve the problems existing in the prior art.
[0006] To achieve the above-mentioned technical objectives, according to a first aspect of the present invention, the present invention provides a method for identifying wafer dark cracks during wafer testing, comprising: S100: Acquire electrical test data uploaded in real time by the tester during wafer testing; S200. Determine whether the electrical test data meets the dark crack triggering rule according to the preset check conditions. If it does, control the probe tester to perform physical measurement on the current wafer. The physical measurement includes thickness measurement and image acquisition. S300. Obtain the results of the physical measurement, and identify and determine the hidden cracks based on the results of the physical measurement using a preset analysis model.
[0007] Specifically, the method for determining whether the electrical test data meets the dark crack triggering rule based on preset checkpoint conditions includes: Analyzing the distribution of failed chips in the wafer test pattern generated from the electrical test data, when the failed chips are distributed in a cross shape, and the number of failed chips in the cross-shaped area meets the preset failure rules, and the failure rate in the cross-shaped area is lower than the preset threshold, it is determined that the dark crack triggering rule is met.
[0008] Specifically, the preset failure rules include: Taking the center of the cross-shaped region as a reference, n chips above, below, left, and right of the center of the cross-shaped region are all failed chips, where n is an adjustable positive integer.
[0009] Specifically, the method for controlling the probe probe to perform physical measurements on the current wafer further includes: Before performing thickness measurement and image acquisition, the probe prober is controlled to perform wafer alignment.
[0010] Specifically, the thickness measurement includes: Thickness measurements were performed on five designated areas of the wafer: the top, middle, bottom, left, and right sides, resulting in five sets of thickness data.
[0011] Specifically, the preset analysis model is a multimodal fusion model, including: The image feature extraction branch is used to extract texture features related to dark cracks from the acquired images; The thickness feature extraction branch is used to extract thickness distribution features from thickness data; The feature fusion layer is used to fuse image features with thickness features; A classifier is used to output the crack identification result and confidence level based on the fused features.
[0012] Specifically, the method further includes: The server establishes a communication connection with the probe tester and the testing machine via the TCP / IP protocol. The server acts as the control terminal, sending instructions to the probe tester and the testing machine, and receiving electrical test data uploaded by the testing machine and physical measurement results uploaded by the probe tester.
[0013] Specifically, the method for identifying and determining hidden cracks based on the results of the physical measurements using a preset analysis model includes: When the preset analysis model determines that a dark crack exists, the server issues an abnormal warning message and stops subsequent testing of the current wafer; When the preset analysis model determines that there are no hidden cracks, the server sends a continue testing instruction to the testing machine.
[0014] According to a second aspect of the present invention, a system for identifying wafer dark cracks during wafer testing is provided, comprising a testing machine and a probe tester, and further comprising a server, wherein the server is communicatively connected to the testing machine and the probe tester respectively, and the server comprises: Acquisition module: Used to acquire electrical test data uploaded in real time by the tester during wafer testing; Control module: Used to determine whether the electrical test data meets the dark crack triggering rules according to the preset check conditions. If it does, the probe tester is controlled to perform physical measurements on the current wafer. The physical measurements include thickness measurement and image acquisition. Identification module: used to acquire the results of the physical measurements and to identify and determine the hidden cracks based on the results of the physical measurements using a preset analysis model.
[0015] Beneficial effects: This invention provides a method and system for identifying wafer dark cracks during wafer testing. By acquiring electrical test data from the testing machine in real time and making judgments, it can quickly capture dark crack signals without affecting the normal testing cycle. This avoids high-cost physical measurements on all wafers, significantly improving detection efficiency and reducing detection costs. When a dark crack rule is triggered, the probe microanalyzer automatically performs thickness measurement and image acquisition, realizing multi-dimensional data fusion of electrical anomalies and physical characteristics. This overcomes the deficiency that a single electrical test cannot directly identify early physical dark cracks. Based on the acquired physical measurement results, a preset analysis model is used to identify and judge dark cracks, enabling accurate identification of tiny dark cracks. This effectively avoids missed and false judgments, greatly improving the accuracy and reliability of wafer dark crack detection, and ensuring the yield and production safety of subsequent processes. Attached Figure Description
[0016] Figure 1This is a flowchart of a method for identifying wafer dark cracks during wafer testing provided in a specific embodiment of the present invention; Figure 2 This is a schematic diagram of the system composition of the wafer dark crack identification system provided in a specific embodiment of the present invention; Figure 3 This is a flowchart illustrating the rules for determining the triggering of dark cracks provided in a specific embodiment of the present invention; Figure 4 This is a timing diagram illustrating the interaction between the server, the testing machine, and the probe tester provided in a specific embodiment of the present invention. Figure 5 This is a wafer testing method provided in a specific embodiment of the present invention. Figure 1 ; Figure 6 This is a wafer testing method provided in a specific embodiment of the present invention. Figure 2 ; Figure 7 This is a wafer testing method provided in a specific embodiment of the present invention. Figure 3 ; The reference numerals in the above figures are as follows: 101. Cross-shaped distribution; 102. Cross-shaped area. Detailed Implementation
[0017] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Based on the embodiments in this application, other similar embodiments obtained by those skilled in the art without creative effort should all fall within the scope of protection of this application. Furthermore, directional terms mentioned in the following embodiments, such as "up," "down," "left," and "right," are only for reference to the directions in the accompanying drawings; therefore, the directional terms used are for illustrative purposes and not for limiting the invention.
[0018] Before providing a further detailed description of the embodiments of this application, some of the nouns and terms involved in the embodiments of this application will be explained. The nouns and terms involved in the embodiments of this application are subject to the following interpretations.
[0019] (1) Electrical test data: refers to the data generated by the tester when performing electrical performance tests on each chip (die) on the wafer, such as the pass / fail status of each chip, specific electrical parameter values, etc. These data can be collected and analyzed in real time, and their spatial distribution on the wafer can be visualized as a wafer map, thus intuitively reflecting the distribution pattern of failed chips.
[0020] (2) Dark crack triggering rules: refers to a set or more pre-set logical rules used to analyze electrical test data in real time to determine whether the current wafer has suspected dark crack features, thereby deciding whether to trigger the subsequent physical measurement process. Dark crack triggering rules are the key link connecting electrical screening and physical re-inspection.
[0021] (3) Physical measurement: refers to the measurement of non-electrical properties of a wafer using a probe tester or other measuring equipment. In this application, physical measurement is a depth verification step performed on a wafer suspected of having dark cracks. Its purpose is to obtain data that can directly or indirectly characterize the physical morphology of dark cracks, such as local thickness changes and surface image features of the wafer.
[0022] (4) Preset analysis model: refers to a pre-trained algorithm model used to analyze physical measurement results to determine whether there is a dark crack. The preset analysis model can be a model based on traditional machine learning algorithms, a model based on deep learning (such as convolutional neural networks), or a composite model combining multiple algorithms. Its core function is to analyze the complex patterns related to dark cracks in physical measurement data.
[0023] (5) Multimodal fusion model: refers to a specific analysis model that can process and fuse data from different sources or types. In the preferred embodiment of this application, it specifically refers to a model that can process image data (visual modality) and thickness data (physical size modality) at the same time. By fusing information from the two modalities, it can achieve more accurate identification and judgment of dark cracks than relying on a single data source.
[0024] (6) Probe tester: refers to a device used in the wafer testing process to carry and accurately position the wafer, and to establish an electrical connection between the tester and the chip under test by accurately contacting the chip pads through probes on the probe card. In this application, in addition to performing conventional probe contact functions, the probe tester is also given the ability to perform physical measurement tasks such as wafer alignment, thickness measurement and image acquisition.
[0025] (7) Tester: refers to an automated test equipment (ATE) that generates test signals to excite the chip, collects the chip response signals, and analyzes the signals according to a preset test program to determine whether the chip’s electrical functions and performance are qualified. The tester is the source of the original electrical test data.
[0026] (8) Server: refers to the central control unit in the system constructed in this invention. It is usually one or a group of high-performance computers connected to the test machine and probe tester through the network. It is responsible for receiving, storing and analyzing data, running the dark crack trigger rule judgment logic and preset analysis model, and issuing control commands to the test machine and probe tester according to the analysis results. It is the core control unit of the entire identification method and system.
[0027] The present invention will be further described below with reference to the accompanying drawings and preferred embodiments.
[0028] Example 1 Please see Figure 1 This embodiment provides a method for identifying wafer dark cracks during wafer testing, including: acquiring electrical test data uploaded in real time by the tester during wafer testing; determining whether the electrical test data meets the dark crack triggering rules according to preset checkpoint conditions; if it does, controlling the probe tester to perform physical measurements on the current wafer, the physical measurements including thickness measurement and image acquisition; The results of the physical measurements are obtained, and the results of the physical measurements are used to identify and determine the hidden cracks through a preset analysis model.
[0029] It is understood that the above-mentioned technical solution of this embodiment solves the technical problems of low efficiency, high cost and insufficient ability to identify micro-cracks in the prior art. This solution uses real-time data generated by conventional electrical testing as a low-cost initial screening method. Through intelligent rule judgment, it triggers high-precision physical measurement re-inspection only for wafers with a high suspicion of dark cracks. Finally, it makes a precise judgment through a multi-dimensional data fusion analysis model, thereby constructing an efficient, accurate and automated closed-loop detection process.
[0030] See Figure 1 The specific implementation steps of the method for identifying wafer dark cracks in wafer testing in this embodiment are as follows: S100: Acquire electrical test data uploaded in real time by the tester during wafer testing; Understandably, the system acquires the electrical test data uploaded in real time by the tester during the wafer testing process. This step utilizes the data that will inevitably be generated in the wafer testing process, without adding any additional testing actions, ensuring zero impact on the normal testing cycle. The tester performs electrical tests on each chip on the wafer and sends the data stream containing the pass or fail information of each chip to the server in real time.
[0031] S200. Determine whether the electrical test data meets the dark crack triggering rule according to the preset check conditions. If it does, control the probe tester to perform physical measurement on the current wafer. The physical measurement includes thickness measurement and image acquisition. It should be noted that the server performs real-time analysis on the received electrical test data to determine whether it meets the preset dark crack triggering rules. The preset dark crack triggering rules aim to identify specific failure modes that are highly correlated with dark crack defects from a large amount of electrical data. Existing technologies often ignore the potential correlation between electrical failure distribution and physical defects, resulting in the dark crack signals being overwhelmed. This solution can keenly capture these signals by setting specific triggering rules.
[0032] Furthermore, if the judgment result meets the dark crack triggering rule, it means that the current wafer has a high risk of dark cracks. The system then controls the probe tester to perform physical measurements on the current wafer. This linkage control is the key to solving the problem of disconnect between electrical testing and physical measurement in the existing technology. As a more accurate detection method, physical measurement is targeted to high-risk samples, rather than performing general inspection on all wafers, thereby greatly saving time and cost. The above-mentioned physical measurement includes at least thickness measurement and image acquisition, with the aim of obtaining the physical state information of the wafer from different dimensions.
[0033] S300. Obtain the results of the physical measurement, and identify and determine the hidden cracks based on the results of the physical measurement using a preset analysis model.
[0034] It should be noted that the system acquires the results uploaded after the probe tester completes the physical measurement, and based on these results, performs the final identification and judgment of dark cracks through a preset analysis model. The preset algorithm model performs in-depth analysis of multi-source physical data, which solves the problems of traditional optical detection or single physical measurement methods being susceptible to interference and insensitive to small defects. By integrating multiple physical features, the model can make a more reliable judgment than single-dimensional information, thus achieving high-precision identification of early-stage small dark cracks.
[0035] Furthermore, in a preferred embodiment, the method for determining whether the electrical test data meets the dark crack triggering rule based on preset checkpoint conditions includes: analyzing the distribution of failed chips in the wafer test pattern generated by the electrical test data; when the failed chips present a cross-shaped distribution 101, and the number of failed chips in the cross-shaped area meets the preset failure rule, and the failure rate in the cross-shaped area is lower than a preset threshold, it is determined that the dark crack triggering rule is met.
[0036] It should be noted that the above-mentioned dark crack triggering rules include analyzing the distribution of failed chips in the wafer map generated from electrical test data. When the system identifies that the failed chips present a specific cross-shaped distribution 101 on the map, it will further determine whether the number of failed chips in the cross-shaped area meets a preset failure rule. In addition, in order to eliminate interference from non-dark crack factors such as regional failures caused by low overall yield, it will also check whether the failure rate in the cross-shaped area is lower than a preset threshold. Only when these conditions are met simultaneously will the system finally determine that the dark crack triggering rules are met.
[0037] Furthermore, the principle behind the aforementioned dark crack triggering rule is that wafer dark cracks are usually caused by stress, and stress tends to propagate along specific crystal orientations in single-crystal silicon materials. When this propagation path is projected onto the two-dimensional wafer surface, it often appears as an approximate straight line or cross shape. Therefore, the distribution of chip electrical failures caused by dark cracks on the Wafer Map naturally presents a cross shape consistent with the dark crack morphology. By setting this geometric feature as a triggering condition, the targeting of the screening can be greatly improved, effectively filtering out randomly distributed failure points unrelated to dark cracks, thereby solving the technical problem of lacking an effective dark crack electrical characteristic model in the prior art.
[0038] In another preferred embodiment, the aforementioned preset failure rule is described in more detail. Using the center of the identified cross-shaped distribution 101 as a reference, the rule requires that n consecutive chips in each of the four directions (up, down, left, and right) be considered failed chips. Here, n is a positive integer that can be flexibly adjusted according to actual needs, for example, it can be set to 3, 5, or 7. This design makes the rule configurable, adaptable to the different detection sensitivity requirements of wafer products of different sizes and process nodes. For some critical products or processes more sensitive to micro-cracks, a smaller n value (e.g., n=3) can be set to improve detection sensitivity, while for some products with large yield fluctuations, a larger n value (e.g., n=5 or 7) can be set to increase the specificity of the rule and avoid false triggering. Through this adjustable parameter, the flexibility and universality of the detection strategy are achieved.
[0039] Preferably, the specific implementation process for determining the triggering of dark cracks based on the cross-shaped failure rule includes the following steps: (1) Acquire and parse wafer test map: The test machine uploads the electrical test results of the current wafer in real time and generates a wafer test map. The server-side algorithm parses the coordinates of each chip (Die) and the corresponding failure mark in the map; (2) Identify cross-shaped failure areas: The server algorithm traverses the parsed coordinate data to identify the failure chip areas that are distributed in a cross shape in the wafer test image; (3) Verify the surrounding failure rules: For the identified cross-shaped area, traverse the coordinates of the chips around the area, count the number of failed chips, and verify whether the rule is met that n chips above, below, left and right of the cross-shaped center are all failed chips; where n is an adjustable positive integer, supporting multiple values such as 3, 5, and 7, to adapt to the different wafer products' requirements for the sensitivity of dark crack detection. (4) Verify the failure rate of the cross-shaped region: Calculate the failure rate of the cross-shaped region, that is, the proportion of the number of failed chips to the total number of chips in the region, and verify whether the failure rate is lower than a preset threshold to avoid misjudgment caused by regional failures (such as scratches, lithography abnormalities, etc.); In an optional embodiment, the cross-shaped region can be a region centered on the center of the cross-shaped distribution 101, with n as the parameter, see [reference]. Figures 5-7 The cross-shaped area can be square, circular, or a cross shape that is proportionally expanded. The cross-shaped area can be set according to the failure range that may be caused by regional failure. In some embodiments, the failure rate of all types of cross-shaped areas can be calculated. If any failure rate is lower than the threshold, the condition is met.
[0040] (5) Dual-condition judgment to trigger anomaly: If the above two conditions, namely the failure rule of the surrounding n chips and the failure rate of the area being lower than the preset threshold, are met at the same time, the server determines that the dark crack triggering rule is met, issues an anomaly warning message and triggers the subsequent physical measurement process; if either condition is not met, it is determined that the dark crack rule has not been triggered and the normal wafer testing process continues.
[0041] Understandably, the above process, through a combination of hardware-level rules and flexible configuration, enables rapid and accurate interception of the risk of wafer dark cracks, while avoiding false triggers caused by regional failures, thus ensuring a balance between testing efficiency and identification accuracy.
[0042] In one optional implementation, to ensure the accuracy of physical measurements, a crucial pre-step is added to the process of controlling the probe prober to perform physical measurements on the current wafer. Specifically, before performing thickness measurements and image acquisition, the server first controls the probe prober to perform a precise alignment operation on the wafer. The probe prober uses its optical system to identify preset alignment marks on the wafer and adjusts the position and angle of the wafer stage to establish a precise wafer coordinate system. By adopting this technical solution, it is ensured that subsequent thickness measurements and image acquisition can be performed at the preset precise positions. Without precise alignment, positional deviations between the measurement points and the acquisition areas will lead to inconsistent data, severely affecting the input quality of the analysis model and the accuracy of the final judgment. Therefore, by adding an alignment operation, the problem of data acquisition errors caused by inaccurate positioning is solved, laying a solid foundation for subsequent high-precision analysis.
[0043] Furthermore, in this embodiment, the thickness measurement specifically includes: performing thickness measurements on five designated areas of the wafer—the upper, middle, lower, left, and right sides—to obtain five sets of thickness data.
[0044] Understandably, the thickness measurement process has been refined. Thickness measurement is no longer limited to a single point; instead, it involves measuring the thickness of at least five designated areas on the wafer—the top, middle, bottom, left, and right—to obtain a set of thickness data. Dark cracks, as a physical defect, can cause stress concentration within the wafer, leading to micron- or even nanometer-level localized deformation or thickness anomalies on the wafer surface. Single-point measurement might miss these anomalous areas, while multi-point measurement can acquire overall thickness profile information for the wafer. By analyzing the differences, gradients, or deviations from standard values among these five sets of data, the non-uniform thickness distribution characteristics caused by dark cracks can be captured more effectively. Compared to single-point measurement, this method provides richer physical dimension information, significantly improving the ability to detect hidden physical defects.
[0045] Furthermore, in this embodiment, the preset analysis model is a multimodal fusion model, including: The image feature extraction branch is used to extract texture features related to dark cracks from the acquired images; The thickness feature extraction branch is used to extract thickness distribution features from thickness data; The feature fusion layer is used to fuse image features with thickness features; A classifier is used to output the crack identification result and confidence level based on the fused features.
[0046] It should be noted that the internal structure of the above multimodal fusion model is clear, mainly including an image feature extraction branch, a thickness feature extraction branch, a feature fusion layer, and a final classifier. This can make full use of the complementary information from different data sources to overcome the limitations of a single information source.
[0047] In some specific embodiments, the image feature extraction branch is typically constructed using a deep convolutional neural network (CNN). When the acquired wafer surface image is input into this branch, the CNN can automatically learn and extract deep texture features, edge contour features, and other microscopic visual patterns related to dark cracks through its multi-layer convolution and pooling operations. This solves the technical problem that traditional image processing algorithms rely on manually designed features and are sensitive to complex backgrounds and lighting changes.
[0048] Specifically, the thickness feature extraction branch is responsible for processing the five sets of thickness data obtained from the thickness measurement. This branch can be a relatively simple neural network (such as a multilayer perceptron MLP), or it can first calculate the mean, variance, range, gradient and other statistics of this set of data through feature engineering methods, and then input these statistical features into the network. The purpose is to extract thickness distribution features from discrete thickness readings that can reflect the overall thickness uniformity of the wafer, local bulges or depressions and other macroscopic deformation trends.
[0049] Subsequently, the feature fusion layer effectively combines the high-dimensional image feature vector output by the image feature extraction branch with the thickness feature vector output by the thickness feature extraction branch. The fusion method can be a simple concatenation, that is, connecting the two vectors end to end to form a longer vector, or a more complex weighted summation, attention mechanism, etc. Through fusion, the model can simultaneously consider the image features and thickness features of the wafer in the same feature space, realizing information complementarity and cross-validation.
[0050] Finally, the fused feature vector is fed into a classifier, which can be a Support Vector Machine (SVM), one or more fully connected layers followed by a Sigmoid or Softmax activation function. Based on the learned decision boundary, the classifier makes a final judgment on the fused features and outputs a specific dark crack identification result. It can also provide a confidence score, which quantifies the reliability of the judgment. Through this multimodal fusion architecture, the accuracy and robustness of the identification are greatly improved. For example, it can effectively distinguish between real microcracks and harmless surface scratches (scratches have image features but no thickness abnormalities), thus achieving a synergistic enhancement effect that is superior to single feature recognition.
[0051] Preferably, the specific process of analysis using a preset analysis model is as follows: (1) Input layer receives data: receives images of the blocked area collected by the needle probe and thickness data of five areas (upper, middle, lower, left and right); (2) Data preprocessing: Denoising and enhancement processing is performed on the acquired images. Enhancement processing includes histogram equalization, and thickness data is normalized to eliminate differences between different units. (3) Feature extraction: Use convolutional neural networks (CNN) to extract texture features and grayscale features related to dark cracks from the preprocessed images, calculate the mean, variance and other statistics of the normalized thickness data, and construct physical parameter feature vectors; (4) Feature fusion: Image features and thickness features are spliced together to form a multi-dimensional fusion feature vector to comprehensively depict the current state of the wafer; (5) Determine model classification: Use a pre-trained classifier, which is a support vector machine (SVM) or a neural network (NN). Input the fused feature vector into the classifier and output the dark crack identification result and the corresponding confidence level. The identification result is "dark crack" or "no dark crack". The confidence level is used to represent the probability of the judgment result. For example, 0.95 means that there is a 95% probability of judging it as a dark crack. (6) Output layer result response: The judgment result is transmitted to the server. The server triggers an abnormal alarm or sends a continue test instruction based on the judgment result, thereby realizing intelligent and accurate identification of wafer dark cracks.
[0052] Furthermore, the method for identifying wafer dark cracks during wafer testing in this embodiment also includes: The server establishes a communication connection with the probe tester and the testing machine via the TCP / IP protocol. The server acts as the control terminal, sending instructions to the probe tester and the testing machine, and receiving electrical test data uploaded by the testing machine and physical measurement results uploaded by the probe tester.
[0053] It should be noted that the server establishes a stable and reliable communication connection with the probe tester and the testing machine through the standard TCP / IP protocol. In the entire system, the server acts as the control end, while the probe tester and the testing machine act as the execution end. The server is responsible for issuing all operation instructions to the probe tester and the testing machine, such as starting the test, pausing the test, and performing physical measurements. It also acts as a data aggregation center, receiving real-time electrical test data uploaded by the testing machine and physical measurement results uploaded by the probe tester. This centralized control architecture ensures the uniformity of instructions and the orderliness of data flow, which is the foundation for realizing the entire automated closed-loop process.
[0054] Furthermore, in this embodiment, the method for identifying and determining dark cracks based on the results of the physical measurements using a preset analysis model includes: when the preset analysis model determines that a dark crack exists, the server issues an abnormal warning message and stops subsequent testing of the current wafer; when the preset analysis model determines that no dark crack exists, the server sends a continue testing instruction to the testing machine.
[0055] Understandably, based on the aforementioned communication architecture, this embodiment further provides an intelligent closed-loop control logic. After the preset analysis model in the server completes its judgment of the physical measurement results, it executes different subsequent actions based on the judgment result. Specifically, when the model determines that the current wafer has a dark crack, the server immediately takes intervention measures, such as sending an abnormality warning message to the factory's Manufacturing Execution System (MES) or equipment control console via the network, and automatically sending an instruction to the testing machine to stop any subsequent testing actions on the current wafer, thereby preventing defective wafers from flowing into the next process. Conversely, when the model determines that there is no dark crack, it indicates that the previous electrical abnormality may have been caused by other non-critical factors. The server sends an instruction to the testing machine to continue testing, allowing the testing process to resume seamlessly. This automated closed-loop control based on accurate judgment results not only achieves immediate interception of defects but also avoids unnecessary production line downtime, achieving the optimal balance between production efficiency and quality control.
[0056] Preferred, see Figure 4 This embodiment achieves closed-loop testing through multi-device linkage protocol and precise timing control. The specific process is as follows: (1) Connection establishment stage: The server, probe tester and tester are connected to the network through TCP / IP protocol. The server acts as the control terminal to realize command transmission and reception and status monitoring; (2) Testing phase: The test machine uploads the Touch Down test results to the server in real time. The server-side algorithm determines whether a stuck state is triggered based on the cross-shaped failure rule. (3) Blocking Trigger: If the blocking condition is met, the server immediately issues an instruction to stop the current action of the test machine, and at the same time instructs the test machine to perform wafer alignment, thickness measurement of the five regions (top, middle, bottom, left and right), and image acquisition of the blocking area. (4) Re-inspection stage: The needle tester transmits the measured thickness data and collected images back to the server, triggering the AI analysis process, and integrates the images and thickness data to determine the dark crack; (5) Judgment output: Based on the AI analysis results, the server outputs the command "Dark crack alarm" or "Continue testing". The entire command response latency is controlled within 5ms to ensure real-time performance and testing efficiency.
[0057] It should be noted that this embodiment provides a method for identifying wafer dark cracks during wafer testing. By analyzing electrical test data in real time and performing preliminary screening based on preset dark crack triggering rules, physical measurements are triggered only on wafers with high-risk dark crack characteristics, significantly improving detection efficiency and reducing detection costs. By combining electrical test failure modes with physical characteristics and making comprehensive judgments through a multi-modal fusion analysis model, this multi-dimensional data fusion approach can effectively compensate for the shortcomings of single electrical tests in detecting early physical defects and the susceptibility of single physical measurements to interference, greatly improving the accuracy and reliability of identifying micro dark cracks and effectively reducing the false negative and false positive rates. By coordinating the test machine and probe tester through a unified server, an automated closed-loop testing process is constructed, improving the level of intelligence and response speed of production.
[0058] Example 2 Please refer to it again. Figure 2 This application also provides a wafer dark crack identification system during wafer testing. The system includes a testing machine and a probe prober, and adds a server as a central control hub. This server establishes communication connections with both the testing machine and the probe prober. The server integrates an acquisition module, a control module, and an identification module. The acquisition module acquires electrical test data uploaded in real-time by the testing machine during wafer testing. The control module determines whether the electrical test data meets the dark crack triggering rules based on preset checkpoint conditions. If so, it controls the probe prober to perform physical measurements on the current wafer, including thickness measurement and image acquisition. The identification module acquires the results of the physical measurements and performs dark crack identification based on the results using a preset analysis model.
[0059] Specifically, the acquisition module receives and parses electrical test data uploaded by the testing machine in real time. The control module is the system's decision-making and scheduling center, responsible for executing the preset crack triggering rule judgment logic, and generating and sending corresponding control commands to the testing machine and probe tester based on the judgment results. For example, when the triggering rule is met, the control module issues a command to control the probe tester to perform physical measurements. The identification module is the core of the system's intelligent analysis, responsible for acquiring the physical measurement results (thickness and image) uploaded by the probe tester, and embedding a preset analysis model for calculating and analyzing this data, ultimately outputting a judgment on the existence of cracks.
[0060] In one specific embodiment, in order to enable the system to have the ability to learn and continuously evolve, the server also includes a storage module and a model training module. The storage module is designed to store historical test data in a structured manner for a long time, especially those wafer cases that have been triggered by physical measurements. It saves the electrical test data, physical measurement results (thickness, image) of each case, as well as the real label that is finally verified by manual review or subsequent processes, i.e. whether the wafer really has dark cracks, forming a dark crack sample database for a specific production line.
[0061] Furthermore, the model training module utilizes the training samples accumulated in the storage module to periodically or incrementally retrain the multimodal fusion model in the recognition module. By continuously learning from new samples, the model can continuously optimize its internal parameters, improve the recognition accuracy of existing dark crack features, and learn new dark crack patterns that may emerge. This makes the system in this embodiment no longer a static system, but a dynamic system capable of self-iteration and self-improvement. Its detection performance will improve with the accumulation of data, ensuring the long-term effectiveness and advanced nature of this solution.
[0062] The working principle of the wafer dark crack identification system in wafer testing in this embodiment will be further illustrated below through a specific product example: The core server of this system is a high-performance industrial control computer, whose hardware configuration can include a multi-core high-performance processor, large-capacity memory, high-speed solid-state storage devices, and a graphics processing unit (GPU). The server has a server operating system installed and back-end control software deployed.
[0063] The control software integrates several key components: it implements the multimodal fusion model using a deep learning framework; it builds an efficient web service interface using a web service framework for real-time communication with the test machine and probe tester via TCP / IP protocol, receiving data and issuing JSON-formatted instructions; and it uses a relational database as the backend of the storage module to store historical sample data and detection logs, with the test machine and probe tester connected to the server via an internal Ethernet connection.
[0064] The server also provides a web-based graphical user interface (GUI) accessible through a browser. This GUI includes a parameter configuration page, allowing users to select the n value (optional 3, 5, 7) from preset failure rules via drop-down menus based on the current wafer type. Users can also adjust the failure rate threshold (range 50%-95%) within the cross-shaped area using a slider. The GUI further includes a real-time monitoring dashboard that dynamically displays the wafer map of the wafer currently being tested, highlights failed chips, and issues audible and visual alarms and pops up detailed information windows when a dark crack trigger rule is triggered or a dark crack is ultimately determined. Additionally, there is a historical data query page where engineers can retrieve past inspection records by batch, time, and other criteria, viewing detailed data for each marked case, including the wafer map, acquired images, and thickness distribution maps, providing data support for process analysis and yield improvement.
[0065] In a preferred embodiment, see Figure 3 Assuming the scenario is the final testing of a batch of 12-inch logic chip wafers, the system is pre-configured as follows: the dark crack triggering rule is set to the continuous failure of n=3 chips in the center and surrounding area of the cross shape, and the failure rate in the area is less than 85%. The recognition module is equipped with a fully trained multimodal fusion model.
[0066] The process begins with the first wafer being transferred to the stage of the probe tester. The tester then begins to perform electrical tests on each chip on the wafer using probe cards. The tester sends the test results (Pass / Fail and their coordinates) of each chip to the server's acquisition module in real time. In the testing of the first 2,000 chips, the failed chips are randomly and scattered. The server's control module continuously monitors the situation and does not trigger any rules. When the test reaches the center region of the wafer, the server's control module parses the wafer map in real time. (See also...) Figure 5Suddenly, a cross-shaped distribution 101 consisting of 27 failed chips was identified. The algorithm immediately verified the dark crack triggering rule: First, based on a pre-set (n=3) configuration, it was confirmed that the center point of the cross-shaped distribution 101 and the three chips above, below, to the left, and to the right (a total of 13 chips) were all in a failed state. Second, the center point of the cross-shaped distribution 101 was taken as the center point of the cross-shaped region 102. It should be noted that the cross-shaped region 102 can be a region set with n as a parameter, such as... Figures 5-7 The cross-shaped region can be square, circular, or a proportionally expanded cross shape, etc. The cross-shaped region can be set according to the potential failure range caused by regional failure. In some embodiments, the failure rate of all types of cross-shaped regions can be calculated iteratively. If any failure rate is below a threshold, the dark crack triggering rule is satisfied, and the calculation... Figure 5 The failure rate within the cross-shaped region 102 is relatively low, significantly lower than the preset 85% threshold of approximately 26.53%. Based on comprehensive judgment, the condition of failure rate being lower than the threshold is met, thus avoiding misjudgment of the entire low-yield wafer. At this point, the dark crack triggering rule is satisfied. The control module immediately executes a coordinated operation: it sends a pause test command to the testing machine via the network and simultaneously sends a physical measurement command to the probe prober, which includes the precise coordinates of the trigger area. Upon receiving the command, the probe prober first uses its vision system to perform high-precision wafer alignment. After alignment, its integrated non-contact thickness sensor sequentially moves to five preset points on the wafer (top, middle, bottom, left, and right) to measure the thickness, obtaining readings {top: 775.2µm, middle: 776.1µm, bottom: 775.3µm, left: 775.1µm, right: 775.0µm}. Simultaneously, the probe prober's high-resolution camera moves to the coordinate area specified in the command and captures a 2048x2048 pixel surface image. The probe tester packages the five thickness values and image files and sends them back to the server via TCP / IP. After receiving the data, the server's recognition module immediately starts the multimodal fusion model for analysis. The image data is sent to the CNN branch, and the model extracts an extremely weak linear texture feature that is consistent with the direction of the cross-shaped failure area. The thickness data is sent to another branch, and the model analyzes that the thickness of the central region (776.1µm) has a small but significant bulge compared to the other four points. The feature fusion layer combines these two seemingly weak but spatially highly correlated features.
[0067] Ultimately, the model's classifier outputs the judgment result: {Dark crack exists: True, confidence level: 0.985}. Upon receiving this high-confidence result, the control module immediately displays a bright red alert on the central monitoring console interface: "Warning: High-confidence dark crack detected in wafer [batch number-wafer number]", and automatically marks the wafer's status as "abnormal, pending review" in the MES system. Simultaneously, it instructs the testing machine to terminate all tests on the wafer. The entire closed-loop process, from triggering to final judgment and issuing the alert, takes less than 500 milliseconds.
[0068] It is understood that this embodiment combines the breadth of electrical testing, the depth of specific failure modes, the accuracy of multi-point physical measurements, and the intelligence of multimodal AI analysis to achieve rapid, accurate, and automated identification of early and hidden dark cracks that are difficult to detect by traditional methods. This significantly improves the overall performance of the system and achieves the technical goals of high efficiency, accuracy, and low cost.
[0069] It should be noted that the wafer dark crack identification system provided in this embodiment has a wide range of applications. For example, it can be used by wafer manufacturers for final quality inspection before product shipment, ensuring that wafers delivered to customers are free of this significant hidden danger. It can also be used by chip packaging and testing plants for incoming material inspection, rejecting defective wafers before packaging to avoid wasting subsequent packaging and testing costs. Furthermore, this system can be used as an online process control tool, directly integrated into the testing process of chip manufacturing, monitoring anomalies in the production process in real time, and providing immediate data support for process engineers to quickly locate the root cause of problems and adjust process parameters. In addition, for new products or processes in the R&D stage, this system can be used for small-batch, high-precision defect analysis, accelerating the R&D process.
[0070] Example 3 In a preferred embodiment, this application also provides an electronic device, the electronic device comprising: The computer device includes a memory and a processor. The memory stores computer-readable instructions that, when executed by the processor, implement the method for identifying wafer dark cracks during wafer testing. This computer device can be broadly categorized as a server, terminal, or any other electronic device with the necessary computing and / or processing capabilities. In one embodiment, the computer device may include a processor, memory, network interface, communication interface, etc., connected via a system bus. The processor of the computer device can be used to provide the necessary computing, processing, and / or control capabilities. The memory of the computer device may include a non-volatile storage medium and internal memory. The non-volatile storage medium may store an operating system, computer programs, etc. The internal memory can provide an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The network interface and communication interface of the computer device can be used to connect and communicate with external devices via a network. When the computer program is executed by the processor, it performs the steps of the method of the present invention.
[0071] This invention can be implemented as a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, causes the steps of the methods of embodiments of the invention to be performed. In one embodiment, the computer program is distributed across multiple network-coupled computer devices or processors, such that the computer program is stored, accessed, and executed in a distributed manner by one or more computer devices or processors. A single method step / operation, or two or more method steps / operations, may be executed by a single computer device or processor or by two or more computer devices or processors. One or more method steps / operations may be executed by one or more computer devices or processors, and one or more other method steps / operations may be executed by one or more other computer devices or processors. One or more computer devices or processors may execute a single method step / operation, or execute two or more method steps / operations.
[0072] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0073] The technical features described above can be combined arbitrarily. Although not all possible combinations of these technical features are described, any combination of these technical features should be considered to be covered by this specification, provided that such combination does not contain contradictions.
[0074] The specific embodiments of the present invention described above do not constitute a limitation on the scope of protection of the present invention. Any other corresponding changes and modifications made in accordance with the technical concept of the present invention should be included within the scope of protection of the claims of the present invention.
Claims
1. A method for identifying dark cracks in wafers during wafer testing, characterized in that, include: S100: Acquire electrical test data uploaded in real time by the tester during wafer testing; S200. Determine whether the electrical test data meets the dark crack triggering rule according to the preset check conditions. If it does, control the probe tester to perform physical measurement on the current wafer. The physical measurement includes thickness measurement and image acquisition. S300. Obtain the results of the physical measurement, and identify and determine the hidden cracks based on the results of the physical measurement using a preset analysis model.
2. The method for identifying wafer dark cracks in wafer testing according to claim 1, characterized in that, The method for determining whether the electrical test data meets the dark crack triggering rule based on preset checkpoint conditions includes: Analyzing the distribution of failed chips in the wafer test pattern generated from the electrical test data, when the failed chips are distributed in a cross shape, and the number of failed chips in the cross-shaped area meets the preset failure rules, and the failure rate in the cross-shaped area is lower than the preset threshold, it is determined that the dark crack triggering rule is met.
3. The method for identifying wafer dark cracks in wafer testing according to claim 2, characterized in that, The preset failure rules specifically include: Taking the center of the cross-shaped region as a reference, n chips above, below, left, and right of the center of the cross-shaped region are all failed chips, where n is an adjustable positive integer.
4. The method for identifying wafer dark cracks in wafer testing according to claim 1, characterized in that, The method for controlling the probe probe to perform physical measurements on the current wafer also includes: Before performing thickness measurement and image acquisition, the probe prober is controlled to perform wafer alignment.
5. The method for identifying wafer dark cracks in wafer testing according to claim 1, characterized in that, The thickness measurement specifically includes: Thickness measurements were performed on five designated areas of the wafer: the top, middle, bottom, left, and right sides, resulting in five sets of thickness data.
6. The method for identifying wafer dark cracks in wafer testing according to claim 1, characterized in that, The preset analysis model is a multimodal fusion model, including: The image feature extraction branch is used to extract texture features related to dark cracks from the acquired images; The thickness feature extraction branch is used to extract thickness distribution features from thickness data; The feature fusion layer is used to fuse image features with thickness features; A classifier is used to output the crack identification result and confidence level based on the fused features.
7. The method for identifying wafer dark cracks in wafer testing according to claim 1, characterized in that, The method further includes: The server establishes a communication connection with the probe tester and the testing machine via the TCP / IP protocol. The server acts as the control terminal, sending instructions to the probe tester and the testing machine, and receiving electrical test data uploaded by the testing machine and physical measurement results uploaded by the probe tester.
8. The method for identifying wafer dark cracks in wafer testing according to claim 7, characterized in that, The method for identifying and determining hidden cracks based on the results of the physical measurements using a preset analysis model includes: When the preset analysis model determines that a dark crack exists, the server issues an abnormal warning message and stops subsequent testing of the current wafer; When the preset analysis model determines that there are no hidden cracks, the server sends a continue testing instruction to the testing machine.
9. A system for identifying wafer dark cracks during wafer testing, comprising a testing machine and a probe tester, characterized in that, It also includes a server, which is communicatively connected to both the testing machine and the probe testing machine, and the server includes: Acquisition module: Used to acquire electrical test data uploaded in real time by the tester during wafer testing; Control module: Used to determine whether the electrical test data meets the dark crack triggering rules according to the preset check conditions. If it does, the probe tester is controlled to perform physical measurements on the current wafer. The physical measurements include thickness measurement and image acquisition. Identification module: used to acquire the results of the physical measurements and to identify and determine the hidden cracks based on the results of the physical measurements using a preset analysis model.
10. The wafer dark crack identification system in wafer testing according to claim 9, characterized in that, The server also includes: Storage module: Used to store thickness data and image data of historical dark-cracked wafers as training samples; Model training module: used to train the multimodal fusion model in the recognition module using the training samples.