A semiconductor structure and a method of forming the same

Abstract

This application provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein a connection hole extending into the substrate is formed on the top surface of the substrate; forming a first conductor at the bottom of the connection hole, the first conductor being a porous structure; and forming a second conductor on the top surface of the first conductor within the connection hole, the second conductor completely filling the connection hole. This application also provides a semiconductor structure. The semiconductor structure and its formation method provided by this application can avoid the impact of incomplete stress release on device reliability in TSVs due to copper.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] After electroplating copper filler, the copper filler in a through-silicon via (TSV) needs to be annealed.

[0003] During annealing, the copper near the top of the TSV (Transformer Substrate) is able to expand freely, resulting in complete stress release, elimination of internal defects, and a reduction in voids. However, the copper in the middle and bottom of the TSV is constrained by the silicon substrate, leading to incomplete stress release. On one hand, this can cause internal defects to aggregate into voids, affecting the copper's conductivity. On the other hand, the residual stress from incomplete stress release can cause the copper at the bottom of the TSV to expand again after the back-side copper exposure process, potentially even affecting the reliability of the packaged device.

[0004] Therefore, it is necessary to develop a semiconductor structure and its formation method to avoid affecting device reliability due to incomplete stress relief of the copper at the bottom of the TSV. Summary of the Invention

[0005] The purpose of this application is to provide a semiconductor structure and its formation method to avoid the impact of incomplete stress relief on device reliability caused by copper in TSV.

[0006] In a first aspect, this application provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein a connection hole extending into the substrate is formed on the top surface of the substrate; forming a first conductor at the bottom of the connection hole, the first conductor being a porous structure; and forming a second conductor on the top surface of the first conductor within the connection hole, the second conductor completely filling the connection hole.

[0007] In some embodiments, the pores of the first conductor are uniformly distributed.

[0008] In some embodiments, the porosity of the end of the first conductor near the bottom of the connection hole is greater than the porosity of the end of the first conductor away from the bottom of the connection hole.

[0009] In some embodiments, the porosity of the first conductor decreases in a stepwise manner away from the bottom of the connection hole.

[0010] In some embodiments, the porosity of the first conductor decreases gradually in a direction away from the bottom of the connection hole.

[0011] In some embodiments, the method of forming the first conductor includes electroplating.

[0012] In some embodiments, the electroplating process for forming the first conductor includes: depositing the first conductor using a fluctuating current.

[0013] In some embodiments, the oscillation amplitude of the fluctuating current remains constant.

[0014] In some embodiments, the oscillation amplitude of the fluctuating current is reduced in a stepwise manner.

[0015] In some embodiments, the oscillation amplitude of the fluctuating current gradually decreases.

[0016] In some embodiments, the ratio of the deposition thickness of the first conductor to the depth of the connection hole is (0.01 to 0.5):1.

[0017] Secondly, this application also provides a semiconductor structure, comprising: a substrate, wherein a connection hole extending into the substrate is formed on the top surface of the substrate; a first conductor, wherein the first conductor is located at the bottom of the connection hole and the first conductor has a porous structure; and a second conductor, located on the top surface of the first conductor within the connection hole, wherein the second conductor completely fills the connection hole.

[0018] In some embodiments, the pores of the first conductor are uniformly distributed.

[0019] In some embodiments, the porosity of the end of the first conductor closer to the second conductor is less than the porosity of the end of the first conductor farther from the second conductor.

[0020] The beneficial effects of the semiconductor structure and its formation method provided in this application include, but are not limited to, the following:

[0021] The semiconductor structure provided in this application has a first conductor with a porous structure formed on the side of the second conductor facing the bottom of the connection hole in the substrate connection hole. In the subsequent annealing process, the first conductor, due to its porous structure, can reduce its volume when subjected to external force, creating space for the bottom of the second conductor to expand, so that the stress of the second conductor can be completely released, reducing or eliminating internal defects of the second conductor, and at the same time preventing the second conductor from bulging out of the through silicon via due to residual stress at the exposed bottom, which would affect product performance. Attached Figure Description

[0022] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale.

[0023] in:

[0024] Figures 1-7 This is a schematic diagram of the formation process of a semiconductor structure according to some embodiments of this application. Detailed Implementation

[0025] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0026] This application provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein a connection hole extending into the substrate is formed on the top surface of the substrate; forming a first conductor at the bottom of the connection hole, the first conductor being a porous structure; and forming a second conductor on the top surface of the first conductor within the connection hole, the second conductor completely filling the connection hole.

[0027] The semiconductor structure formation method provided in this application first forms a first conductor with a porous structure in a connection hole of the substrate, such as a through-silicon via (TSV), and then forms a second conductor that acts as a wire. In the subsequent annealing process, the first conductor, due to its porous structure, can reduce its volume when subjected to external force, creating space for the bottom expansion of the second conductor. This allows the stress of the second conductor to be completely released, reducing or eliminating internal defects in the second conductor. At the same time, it prevents the second conductor from bulging out of the TSV after the stress remains at the exposed bottom, thus affecting product performance.

[0028] The method for forming the semiconductor structure provided in this application will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0029] refer to Figure 1 A substrate 100 is provided, and a connection hole 200 extending into the interior of the substrate 100 is provided on the top surface of the substrate 100.

[0030] In some embodiments, the substrate 100 is a semiconductor substrate or a packaging substrate, and the material of the substrate 100 includes at least one of silicon oxide, silicon nitride, aluminum oxide, zirconium oxide, and zirconia.

[0031] In some embodiments, reference Figure 2 A barrier layer 300 is further formed on the top surface of the substrate 100 and the bottom and sidewalls of the connection hole 200. The material of the barrier layer 300 includes oxide (OX). The methods for forming the barrier layer 300 include, but are not limited to, chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

[0032] In some embodiments, the connection hole 200 is used to form a through silicon via (TSV).

[0033] Continue to refer to Figure 3 A first conductor 400 is formed at the bottom of the connection hole 200, and the first conductor 400 has a porous structure.

[0034] In some embodiments, the pores of the first conductor 400 are uniformly distributed, that is, the porosity of the first conductor 400 is approximately uniform from one end near the bottom of the connection hole 200 to the other end away from the bottom of the connection hole 200.

[0035] In other embodiments, the porosity of the end of the first conductor 400 near the bottom of the connecting hole 200 is greater than the porosity of the end of the first conductor away from the bottom of the connecting hole 200. A larger porosity makes the first conductor 400 easier to compress under external force, providing more expansion space for the subsequently formed second conductor 500. However, excessive porosity may affect the morphology of the subsequent second conductor 500. For example, if the second conductor 500 is formed by deposition, the end of the second conductor 500 near the first conductor 400 tends to have a larger porosity, which is simultaneously compressed during expansion, affecting the effective length of the second conductor 500. Therefore, designing the first conductor 400 such that the porosity of the end near the second conductor 500 is smaller than the porosity of the end of the first conductor 400 away from the second conductor 500 satisfies the requirement of easy compression of the first conductor 400 while avoiding the influence of the morphology of the second conductor 500.

[0036] In some embodiments, the porosity of the first conductor 400 decreases in a stepwise manner away from the bottom of the connection hole 200.

[0037] In other embodiments, the porosity of the first conductor 400 gradually decreases in a direction away from the bottom of the connection hole 200.

[0038] In some embodiments, the method of forming the first conductor 400 includes electroplating.

[0039] In some embodiments, the electroplating process includes: forming a seed layer (not shown) covering the top surface of the barrier layer 300; depositing the first conductor 400 using a fluctuating current, wherein the fluctuating current refers to a periodic oscillation of current magnitude, that is, the current alternates between a first current and a second current, and the difference between the magnitudes of the first current and the second current is the oscillation amplitude of the fluctuating current; the total duration for which the first current and the second current are applied continuously once is the oscillation period of the fluctuating current. In some embodiments, the current density of the fluctuating current is in the range of 0.01 A / dm³. 2 ~10A / dm 2 For example, 0.01A / dm 2 0.05A / dm 2 0.1A / dm 2 0.2A / dm 2 0.5A / dm 2 1A / dm 2 3A / dm 2 5A / dm 2 6A / dm 2 8A / dm 2 or 10A / dm 2 The oscillation amplitude of the fluctuating current is 0.01 A / dm. 2 ~5A / dm 2 For example, 0.01A / dm 2 0.05A / dm 2 0.1A / dm 2 0.2A / dm 2 0.5A / dm 2 1A / dm 2 2A / dm 2 3A / dm 2 Or 5A / dm 2 The period of the fluctuating current is 0.01s to 5s, for example, 0.01s, 0.05s, 0.1s, 0.2s, 0.5s, 1s, 2s, 3s or 5s.

[0040] In some embodiments, the oscillation amplitude of the fluctuating current remains constant. For example, using a constant 2A / dm 2 The amplitude of the oscillation. A constant oscillation amplitude can keep the porosity of the first conductor 400 uniform.

[0041] In other embodiments, the oscillation amplitude of the fluctuating current decreases in a stepwise manner. This stepwise decrease means that the oscillation amplitude decreases at intervals that are integer multiples of the oscillation period, while the oscillation amplitude within a single oscillation period remains constant. For example, the oscillation amplitude decreases from 2 A / dm². 2 It decreases by 0.2A / dm every three oscillation cycles. 2 The rate of decrease decreased to 0.2A / dm. 2 Specifically, with an oscillation amplitude of 2A / dm 2 The fluctuating current with an oscillation period of 3 seconds is deposited for 3 cycles; then, with an oscillation amplitude of 1.8 A / dm... 2 The fluctuating current with an oscillation period of 3 seconds is deposited for 3 cycles; then, with an oscillation amplitude of 1.6 A / dm... 2 The fluctuating current with an oscillation period of 3 seconds is deposited for 3 cycles; ...; with an oscillation amplitude of 0.2A / dm 2 The oscillation current is deposited for 3 cycles with an oscillation period of 3 seconds. The stepwise reduction in oscillation amplitude causes the porosity of the first conductor 400 to decrease stepwise from the end near the bottom of the connection hole 200 to the end away from the bottom of the connection hole 200.

[0042] In other embodiments, the oscillation amplitude of the fluctuating current decreases gradually. This gradual decrease means that the oscillation amplitude decreases steadily over a period less than a single cycle. For example, while keeping the second current constant, the first current decreases gradually during application. Specifically, in some embodiments, the second current of the fluctuating current is 0.2 A / dm². 2 The current remains constant, with the first current being 2A / dm. 2 And at 0.01A / dm 2 ·s gradually decreased to 0.4A / dm 2 The fluctuating current oscillates repeatedly between the first and second currents with a 3-second oscillation period until the first current decreases to 0.4 A / dm. 2 The gradually decreasing oscillation amplitude can cause the porosity of the first conductor 400 formed to gradually decrease from one end near the bottom of the connection hole 200 to the end away from the bottom of the connection hole 200.

[0043] In some embodiments, the electroplating process further includes depositing the first conductor 400 using a constant current to make the end of the first conductor 400 away from the bottom of the connection hole 200 have a dense structure, which facilitates the deposition of the second conductor 500.

[0044] It should be noted that the electroplating details omitted in the electroplating process can be reasonably set and implemented by those skilled in the art based on technical manuals or literature (e.g., Zhang Jianru. Research on the Influence of Different Current Densities on DC Electroplating for Filling Blind Holes [J]. Printed Circuit Information, 2013, 38-41). In order to make the description concise, the specification only provides detailed descriptions of the key steps of the electroplating process.

[0045] In some embodiments, the ratio of the thickness of the first conductor 400 to the depth of the connection hole 200 is (0.01 to 0.5):1, for example, 0.01:1, 0.05:1, 0.1:1, 0.2:1 or 0.5:1.

[0046] refer to Figures 4-6 A second conductor 500 is formed on the top surface of the first conductor 400 within the connection hole 200, and the second conductor 500 completely fills the connection hole 200.

[0047] In some embodiments, the method of forming the second conductor 500 includes, but is not limited to, electroplating, physical vapor deposition, chemical vapor deposition, and atomic layer deposition.

[0048] In some embodiments, the method for forming the second conductor 500 is electroplating, and the electroplating process for forming the second conductor 500 includes: referencing Figure 4 The second conductor 500 is deposited using a first constant current until the distance between the second conductor 500 and the top surface of the connection hole 200 is 1 / 5 to 1 / 3 of the depth of the connection hole 200. For example, the distance between the second conductor 500 and the top surface of the connection hole 200 is 1 / 5, 1 / 4, or 1 / 3 of the depth of the connection hole 200. (Reference) Figure 5 The second conductor 500 is deposited using a second constant current, so that the second conductor 500 completely fills the connection hole 200 and covers the top surface of the substrate 100. The second constant current is greater than the first constant current.

[0049] The material of the first conductor 400 is the same as the material of the second conductor 500; or the materials of the first conductor 400 and the second conductor 500 are different. In some embodiments, the materials of the first conductor 400 and the second conductor 500 include at least one of copper, aluminum, silver, gold, and graphene.

[0050] In some embodiments, reference Figure 6 After forming the second conductor 500, the substrate 100 is further subjected to chemical mechanical polishing so that the top surface of the second conductor 500 is flush with the top surface of the barrier layer 300 or the seed layer.

[0051] refer to Figure 7 Annealing is performed on the substrate 100; planarization is performed on the top and bottom surfaces of the substrate 100; a portion of the bottom surface of the substrate 100 and the first conductor 400 are removed to expose the second conductor 500.

[0052] During the annealing process, the second conductor 500 expands under thermal stress. Since the first conductor 400 has a porous structure, during the expansion of the second conductor 500, the first conductor 400 contracts under pressure, providing expansion space for the second conductor 500 located at the bottom of the connecting hole 200. This allows the second conductor 500 located at the bottom of the connecting hole 200 and the second conductor 500 located at the top of the connecting hole 200 to expand simultaneously, completely releasing the internal stress of the second conductor 500 and eliminating internal defects in the second conductor 500.

[0053] In some embodiments, the method for planarizing the top and bottom surfaces of the substrate 100 includes chemical mechanical polishing.

[0054] This application also provides a semiconductor structure, referenced... Figure 6 The device includes: a substrate 100, the top surface of which has a connection hole 200 extending into the interior of the substrate 100; a first conductor 400, the first conductor 400 being located at the bottom of the connection hole 200, the first conductor 400 having a porous structure; and a second conductor 500, located inside the connection hole 200 on the top surface of the first conductor 400, the second conductor 500 completely filling the connection hole 200.

[0055] In some embodiments, the porosity of the end of the first conductor 400 near the bottom of the connection hole 200 is greater than the porosity of the end of the first conductor 400 away from the bottom of the connection hole 200.

[0056] The semiconductor structure and embodiments of this application provide Figures 1-6 The semiconductor structures shown are the same or similar, and will not be described in detail here for the sake of brevity in the specification.

[0057] The semiconductor structure provided in this application has a first conductor with a porous structure formed on the side of the second conductor facing the bottom of the connection hole in the substrate connection hole. In the subsequent annealing process, the first conductor, due to its porous structure, can reduce its volume when subjected to external force, creating space for the bottom of the second conductor to expand, so that the stress of the second conductor can be completely released, reducing or eliminating internal defects of the second conductor, and at the same time preventing the second conductor from bulging out of the through silicon via due to residual stress at the exposed bottom, which would affect product performance.

[0058] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0059] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0060] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0061] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0062] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Therefore, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For example, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, wherein a connection hole extending into the interior of the substrate is formed on the top surface of the substrate; A first conductor is formed at the bottom of the connection hole, and the first conductor has a porous structure. A second conductor is formed on the top surface of the first conductor within the connection hole, and the second conductor completely fills the connection hole.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The pores of the first conductor are uniformly distributed.

3. The method for forming a semiconductor structure according to claim 1, characterized in that, The porosity of the end of the first conductor near the bottom of the connection hole is greater than the porosity of the end of the first conductor away from the bottom of the connection hole.

4. The method for forming a semiconductor structure according to claim 3, characterized in that, The porosity of the first conductor decreases in a stepwise manner away from the bottom of the connection hole.

5. The method for forming a semiconductor structure according to claim 3, characterized in that, The porosity of the first conductor decreases gradually in a direction away from the bottom of the connection hole.

6. The method for forming a semiconductor structure according to claim 1, characterized in that, The method of forming the first conductor includes electroplating.

7. The method for forming a semiconductor structure according to claim 6, characterized in that, The electroplating process for forming the first conductor includes: The first conductor is deposited using a fluctuating current.

8. The method for forming a semiconductor structure according to claim 7, characterized in that, The oscillation amplitude of the fluctuating current remains constant.

9. The method for forming a semiconductor structure according to claim 7, characterized in that, The oscillation amplitude of the fluctuating current decreases in a stepwise manner.

10. The method for forming a semiconductor structure according to claim 7, characterized in that, The oscillation amplitude of the fluctuating current gradually decreases.

11. The method for forming a semiconductor structure according to claim 1, characterized in that, The ratio of the deposition thickness of the first conductor to the depth of the connecting hole is (0.01 to 0.5):

1.

12. A semiconductor structure, characterized in that, include: A substrate, wherein a connection hole extending into the interior of the substrate is provided on the top surface of the substrate; A first conductor is located at the bottom of the connection hole, and the first conductor has a porous structure. as well as The second conductor is located on the top surface of the first conductor inside the connection hole, and the second conductor completely fills the connection hole.

13. The semiconductor structure according to claim 12, characterized in that, The pores of the first conductor are uniformly distributed.

14. The semiconductor structure according to claim 12, characterized in that, The porosity of the end of the first conductor closer to the second conductor is less than the porosity of the end of the first conductor farther from the second conductor.

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