Semiconductor device and manufacturing method thereof, electronic device
By setting an isolation sublayer between the connecting electrodes and optimizing the arrangement of signal lines and connecting electrodes, the problems of device integration and parasitic capacitance are solved, resulting in more efficient device manufacturing and reduced costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING SUPERSTRING ACAD OF MEMORY TECH
- Filing Date
- 2025-01-06
- Publication Date
- 2026-07-10
AI Technical Summary
With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the impact of minute differences on device performance is increasing. How to manufacture more devices on a limited substrate and reduce parasitic capacitance has become a challenge.
By setting an isolation sublayer between the connecting electrodes, the size of the connecting electrodes is reduced. The arrangement of the horizontal and vertical parts is designed to reduce parasitic capacitance. The staircase structure in the three-dimensional architecture is adopted to simplify the process and reduce costs.
This effectively reduces parasitic capacitance between the horizontal and vertical sections, improves device integration, and lowers manufacturing costs.
Smart Images
Figure CN122373794A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to, but is not limited to, device design and manufacturing in the field of semiconductor technology, and particularly to a semiconductor device and its manufacturing method, and electronic equipment. Background Technology
[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.
[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention
[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.
[0005] This application provides a semiconductor device and its manufacturing method, as well as an electronic device, which can reduce the parasitic capacitance of the semiconductor device.
[0006] This application provides a semiconductor device, comprising: multiple signal lines stacked on a substrate in a direction perpendicular to the substrate and distributed in multiple layers, and multiple connection electrodes disposed on the same side of the multiple signal lines, wherein the multiple connection electrodes and the signal lines are distributed in a second direction; the signal lines extend in a direction parallel to the substrate; each connection electrode includes a horizontal portion extending in a direction parallel to the substrate and a vertical portion extending in a direction perpendicular to the substrate connected to the horizontal portion, wherein the horizontal portion of each connection electrode is distributed in different layers and connected to a signal line in the same layer; the multiple vertical portions of the multiple connection electrodes are spaced apart in a first direction, or arranged in an array along the first direction and the second direction; a first sub-trench extending in the second direction and penetrating multiple layers and spaced apart from adjacent connection electrodes along the first direction is provided between them, and a first isolation sub-layer filling the first sub-trench, wherein the first direction and the second direction intersect.
[0007] In some embodiments, the horizontal portion extends along the second direction, and the vertical portions of the plurality of the plurality of the connecting electrodes form two rows. The horizontal portion of the connecting electrodes in the first row distributed along the first direction near the signal line is disposed between the signal line connected to the connecting electrodes and the vertical portion of the connecting electrodes adjacent along the second direction.
[0008] In some embodiments, the semiconductor device further includes a second isolation sublayer that extends through multiple layers in a direction perpendicular to the substrate and extends along the first direction. The second isolation sublayer is disposed on the side of the first isolation sublayer away from the signal line and is connected to the first isolation sublayer. A plurality of the connection electrodes are disposed between the second isolation sublayer and the signal line.
[0009] In some embodiments, the horizontal portion of the connecting electrodes in the second row distributed along the first direction away from the signal line is connected at one end to the signal line and at the other end to the second isolation sublayer.
[0010] In some embodiments, the semiconductor device further includes a third insulating layer that surrounds the sidewall of the vertical portion and is connected to the first isolation sublayer.
[0011] In some embodiments, the orthographic projection of the third insulating layer on the substrate overlaps with the orthographic projection of at least one of the two adjacent first isolation sublayers on the substrate, or the orthographic projection of the third insulating layer on the substrate is located outside the orthographic projection of the two adjacent first isolation sublayers on the substrate, and the orthographic projection of the third insulating layer on the side facing the first isolation sublayer falls on the boundary of the orthographic projection of the first isolation sublayer on the substrate.
[0012] This disclosure provides a method for manufacturing a semiconductor device, including:
[0013] A stacked structure comprising multiple alternating first insulating layers and sacrificial layers is formed on a substrate. The stacked structure is patterned to form multiple signal lines, and the multiple signal lines are respectively disposed on different sacrificial layers.
[0014] A plurality of first sub-trenches are formed on the same side of the signal lines, extending along a second direction and spaced apart along a first direction through the stacked structure, with the first sub-trenches exposing the sidewall of each signal line; and a first isolation sub-layer is formed to fill the first sub-trenches.
[0015] Contact holes extending perpendicular to the substrate are formed between adjacent first isolation sublayers, and the bottom wall of each contact hole exposes a sacrificial layer containing a signal line; a third insulating layer is formed covering the sidewalls of the contact holes; based on the contact holes, the sacrificial layer is etched in a direction parallel to the substrate to expose the signal line to form a second lateral groove;
[0016] A connecting electrode is formed that fills the contact hole and the second transverse groove.
[0017] In some embodiments, the method further includes: forming a second sub-trench extending along a first direction through the stacked structure, the second sub-trench being disposed on the side of the first sub-trench away from the signal line, and the second sub-trench communicating with a plurality of first sub-trenches;
[0018] When forming the first isolation sublayer that fills the first sub-groove, a second isolation sublayer that fills the second sub-groove is also formed.
[0019] In some embodiments, the sidewalls of the contact hole expose two first isolation sublayers adjacent to the contact hole.
[0020] In some embodiments, the orthographic projection of the contact hole onto the substrate is located outside the orthographic projection of the first isolation sublayer onto the substrate, or the orthographic projection of the contact hole onto the substrate overlaps with the orthographic projection of the first isolation sublayer onto the substrate.
[0021] This disclosure provides an electronic device, including any of the semiconductor devices described above, or a semiconductor device formed according to the manufacturing method of any of the semiconductor devices described above.
[0022] This application includes a semiconductor device and a method for manufacturing the same, and an electronic device. The semiconductor device includes: multiple signal lines stacked on a substrate in a direction perpendicular to the substrate and distributed in multiple layers, and multiple connection electrodes disposed on the same side of the multiple signal lines. The multiple connection electrodes and the signal lines are distributed in a second direction. The signal lines extend in a direction parallel to the substrate. Each connection electrode includes a horizontal portion extending in a direction parallel to the substrate and a vertical portion extending in a direction perpendicular to the substrate connected to the horizontal portion. The horizontal portions of each connection electrode are distributed in different layers and connected to a signal line in the same layer. The multiple vertical portions of the multiple connection electrodes are spaced apart in a first direction, or arranged in an array along the first direction and the second direction. A first sub-trench extending in the second direction and penetrating multiple layers is provided between adjacent connection electrodes along the first direction, and a first isolation sub-layer is filled with the first sub-trench. The solution provided in this disclosure reduces the size of the connecting electrodes along the first direction by providing a first isolation sublayer between the connecting electrodes, thereby reducing the area of the horizontal portion and ensuring that there is no overlap between the orthographic projections of adjacent horizontal portions along the first direction, reducing the parasitic capacitance between horizontal portions of different layers, and reducing the parasitic capacitance between the vertical portion and the horizontal portions of other connecting electrodes.
[0023] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the embodiments described in the description and the accompanying drawings.
[0024] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description
[0025] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.
[0026] Figure 1A A three-dimensional schematic diagram of a semiconductor device provided for some embodiments. Figure 1B A top view schematic diagram of a semiconductor device provided for some embodiments. Figure 1C For along Figure 1B Cross-sectional view of the substrate in the direction perpendicular to BB'. Figure 1D For along Figure 1B A cross-sectional view of the substrate in the CC' direction perpendicular to the substrate;
[0027] Figure 1E A top view schematic diagram of a semiconductor device provided for other embodiments;
[0028] Figure 2 A cross-sectional view along the AA' direction perpendicular to the substrate after the formation of the stacked structure and the first hole is provided in some embodiments;
[0029] Figure 3 A cross-sectional view along the AA' direction perpendicular to the substrate after forming a signal line, provided for some embodiments;
[0030] Figure 4A A cross-sectional view along the AA' direction perpendicular to the substrate after the formation of the isolation layer, provided for some embodiments. Figure 4B A cross-sectional view along the BB' direction perpendicular to the substrate after the formation of the isolation layer, provided for some embodiments;
[0031] Figure 5A A cross-sectional view along the BB' direction perpendicular to the substrate after forming multiple contact holes, provided for some embodiments. Figure 5B A cross-sectional view along the CC' direction perpendicular to the substrate after forming multiple contact holes, provided for some embodiments;
[0032] Figure 6A A cross-sectional view along the BB' direction perpendicular to the substrate after exposing multiple contact holes, as provided in some embodiments. Figure 6B A cross-sectional view along the CC' direction perpendicular to the substrate after exposing multiple contact holes, as provided in some embodiments;
[0033] Figure 7A A cross-sectional view along the BB' direction perpendicular to the substrate after exposing the sacrificial layer, provided for some embodiments. Figure 7B A cross-sectional view along the CC' direction perpendicular to the substrate after exposing the sacrificial layer, provided for some embodiments. Detailed Implementation
[0034] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.
[0035] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.
[0036] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values shown in the drawings.
[0037] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.
[0038] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the disclosure is not limited to the terms used herein and may be appropriately replaced as appropriate.
[0039] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to physical or signal connections, contact or integral connections; direct connections, indirect connections via intermediate components, or internal communication between two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure according to the specific circumstances.
[0040] In this disclosure, "connection" includes the situation where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.
[0041] In this disclosure, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.
[0042] In this embodiment of the disclosure, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected membrane layers on a single membrane layer. For example, A and B may be formed using the same material as a single membrane layer and simultaneously created through the same patterning process, resulting in a structure with interconnected relationships.
[0043] In this embodiment of the disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.
[0044] With the continuous improvement of chip integration, three-dimensional architecture has become the dominant trend in the development of various technologies. In three-dimensional architecture, the staircase (SC) is an indispensable component for connecting metal lines. Parasitic capacitance is easily introduced into the staircase, therefore it is necessary to reduce its parasitic capacitance.
[0045] Figure 1A A three-dimensional schematic diagram of a semiconductor device provided for some embodiments. Figure 1B A top view schematic diagram of a semiconductor device provided for some embodiments. Figure 1C For along Figure 1B A cross-sectional view of the substrate 1 in the direction perpendicular to BB'. Figure 1D For along Figure 1B A cross-sectional view of the middle section perpendicular to the CC' direction of substrate 1. The BB' direction is perpendicular to the CC' direction. Figure 1A The diagram shows 10 connecting electrodes 32. Figures 1B to 1D For simplicity, only 8 connecting electrodes 32 are shown in the diagram. Figures 1A to 1DAs shown, this disclosure provides a semiconductor device including multiple signal lines 31 stacked on a substrate 1 in a direction perpendicular to the substrate 1 and multiple connection electrodes 32 disposed on the same side of the multiple signal lines 31. The multiple connection electrodes 32 and the signal lines 31 are distributed along a second direction Y. The signal lines 31 extend in a direction parallel to the substrate 1. The connection electrodes 32 may include a horizontal portion 321 extending in a direction parallel to the substrate 1 and a vertical portion 322 extending in a direction perpendicular to the substrate 1 connected to the horizontal portion 321. The horizontal portion 321 of each connection electrode 32 is distributed in different layers and connected to a signal line 31 in the same layer. The multiple vertical portions 322 of the multiple connection electrodes 32 may be distributed at intervals along a first direction X, or arranged in an array along the first direction X and the second direction Y. A first sub-trench extending through multiple layers and extending along the second direction Y is provided between adjacent connection electrodes 32 along the first direction X, and a first isolation sub-layer 611 filling the first sub-trench. Figure 1B Only the vertical portion 322 is shown; the horizontal portion 321 is not shown. The first direction X and the second direction Y are parallel to the substrate 1 and intersect. In some embodiments, the first direction X and the second direction Y are perpendicular.
[0046] The solution provided in this embodiment reduces the size of the connecting electrodes 32 along the first direction by providing a first isolation sublayer 611 between the connecting electrodes 32, thereby reducing the area of the horizontal portion 321 and ensuring that the orthographic projections of adjacent horizontal portions 321 along the first direction X do not overlap, reducing the parasitic capacitance between horizontal portions 321 of different layers, and reducing the parasitic capacitance between the vertical portion 322 and the horizontal portions 321 of other connecting electrodes 32.
[0047] In some embodiments, the horizontal portion 321 may extend along the second direction Y, and the multiple vertical portions 322 of the plurality of connecting electrodes 32 may form two rows, the first direction X being called the row direction and the second direction Y being called the column direction. The horizontal portion 321 of the first row of connecting electrodes 32 distributed along the first direction X near the signal line 31 is disposed between the signal line 31 connected to the connecting electrodes 32 and the vertical portion 322 of the connecting electrodes 32 adjacent along the second direction Y. For example, refer to Figure 1CTaking the first connecting electrode 32 in the first row as an example, the horizontal portion 321 of the first connecting electrode 32 in the first row is located between the vertical portion 322 of the first connecting electrode 32 in the second row and the signal line 31. In the solution provided by this embodiment, the length of the connecting electrode 32 in the first row along the second direction Y is limited by the adjacent connecting electrode 32, which can further reduce the area of the connecting electrode and reduce parasitic capacitance. However, this embodiment is not limited to this; the horizontal portion 321 of the connecting electrode 32 in the first row can extend to the side of the vertical portion 322 of the adjacent connecting electrode 32 along the second direction Y that faces away from the signal line 31.
[0048] In some embodiments, the semiconductor device may include N layers of signal lines 31 (starting from the signal line 31 closest to the substrate 1, representing the first layer of signal lines 31 to the Nth layer of signal lines 31) and N connection electrodes. A first row includes N / 2 connection electrodes, and a second row includes N / 2 connection electrodes. The first to N / 2 connection electrodes of the first row are respectively connected to the signal lines 31 of the Nth to N / 2+1th layers, and the first to N / 2 connection electrodes of the second row are respectively connected to the signal lines 31 of the N / 2th to the first layer. Figure 1A As shown, the first to fifth connection electrodes in the first row are connected to signal lines 31 in layers 10 to 6; the first to fifth connection electrodes in the second row are connected to signal lines 31 in layers 5 to 1. With this arrangement, the horizontal portions 321 of multiple connection electrodes in the same column that have parasitic capacitance are spaced further apart, which reduces parasitic capacitance.
[0049] In some embodiments, the semiconductor device may further include a second isolation sublayer 612 extending through multiple layers perpendicular to the substrate 1 and extending along the first direction X. The second isolation sublayer 612 is disposed on the side of the first isolation sublayer 611 opposite to the signal line 31. The second isolation sublayer 612 can be connected to the first isolation sublayer 611, and a plurality of connection electrodes 32 are disposed between the second isolation sublayer 612 and the signal line 31. The solution provided in this embodiment can define the size of the connection electrodes 32 along the second direction Y by means of the second isolation sublayer 612.
[0050] In some embodiments, the horizontal portion 321 of the second row of connecting electrodes 32 distributed along the first direction X, away from the signal line 31, is connected at one end to the signal line 31 and at the other end to the second isolation sublayer 612.
[0051] In some embodiments, the semiconductor device may further include a third insulating layer 13 that surrounds the sidewall of the vertical portion 322 and is connected to the first isolation sublayer 611. The third insulating layer 13 may space the vertical portion 322 of the electrode 32 and the horizontal portion 321 of the adjacent connecting electrode 32 along the second direction Y. One end of the horizontal portion 321 of the first row of connecting electrodes 32 is connected to a signal line 31, and the other end is connected to the third insulating layer 13 that surrounds the vertical portion 322 of the adjacent connecting electrode 32 along the second direction Y.
[0052] In some embodiments, the orthographic projection of the third insulating layer 13 onto the substrate 1 overlaps with the orthographic projection of the first isolation sublayer 611 onto the substrate 1; or, the orthographic projection of the third insulating layer 13 onto the substrate 1 is located outside the orthographic projection of the first isolation sublayer 611 onto the substrate 1, and the orthographic projection of the third insulating layer on the substrate towards the first isolation sublayer falls on the boundary of the orthographic projection of the first isolation sublayer onto the substrate 1. (Reference) Figure 1B The orthographic projection of the third insulating layer 13 onto the substrate 1 is located outside the orthographic projection of the first isolation sublayer 611 onto the substrate 1, and the boundary of the orthographic projection of the third insulating layer 13 falls on the boundary of the orthographic projection of the first isolation sublayer 611 onto the substrate 1. That is, the contact hole where the connecting electrode 32 and the third insulating layer 13 are located falls exactly between two adjacent first isolation sublayers 611. Figure 1E A top view schematic diagram of a semiconductor device provided for some embodiments. For example... Figure 1E As shown, the orthographic projection of the third insulating layer 13 onto the substrate 1 overlaps with the orthographic projection of the first isolation sublayer 611 onto the substrate 1. At this time, the orthographic projection of the contact hole where the connecting electrode 32 and the third insulating layer 13 are located onto the substrate 1 overlaps with the orthographic projections of the two adjacent first isolation sublayers 611 onto the substrate. The solution provided in this embodiment, where the third insulating layer 13 is close to or overlaps with the adjacent first isolation sublayer 611, allows the horizontal portion of the connecting electrode near the signal line 31 to be confined between the contact hole and the signal line away from the signal line 31, reducing the size of the horizontal portion of the connecting electrode near the signal line 31 along the second direction.
[0053] In some embodiments, the horizontal portion 321 and the vertical portion 322 of the same connecting electrode 32 can be connected to form an integral structure. The solution provided by the embodiments of this disclosure can form the horizontal portion 321 and the vertical portion 322 of the same connecting electrode 32 in one step, simplifying the process and reducing costs.
[0054] In some embodiments, the semiconductor device may include a multilayer memory cell array stacked along a direction perpendicular to the substrate 1. Each layer of the memory cell array may include a plurality of memory cells distributed in the array. The memory cells may be connected to bit lines or word lines. The signal line 31 may be a common bit line connected to a plurality of bit lines or a common word line connected to a plurality of word lines, etc.
[0055] In some embodiments, the signal line 31 can be a ring structure, such as a square ring. The long side of the signal line 31 can extend along a first direction X, and the short side can extend along a second direction Y. The ring structure can be filled with a second insulating layer 12. The second insulating layer 12 can penetrate multiple layers, filling the ring structure of multiple layers of signal lines 31.
[0056] This disclosure provides a method for manufacturing a semiconductor device, which may include:
[0057] A stacked structure comprising multiple alternating first insulating layers 11 and sacrificial layers 10 is formed on a substrate, and the stacked structure is patterned to form multiple signal lines 31, wherein the multiple signal lines 31 are respectively disposed on different sacrificial layers 10;
[0058] A plurality of first sub-trenches are formed on the same side of the signal line 31, extending along the second direction Y and spaced apart along the first direction X, penetrating the stacked structure. The first sub-trenches expose the sidewall of each signal line 31. A first isolation sub-layer 611 is formed to fill the first sub-trenches.
[0059] Contact holes extending in a direction perpendicular to the substrate 1 are formed between adjacent first isolation sublayers 511, and the bottom wall of each contact hole exposes a sacrificial layer 10 where a signal line 31 is located; a third insulating layer 13 is formed covering the sidewalls of the contact holes; the sacrificial layer 10 is etched in a direction parallel to the substrate 1 based on the contact holes until the signal line 31 is exposed, forming a second lateral groove A2;
[0060] A connecting electrode 32 is formed to fill the contact hole and the second transverse groove A2.
[0061] In some embodiments, the method may further include: forming a second sub-trench extending along a first direction X through the stacked structure, the second sub-trench being disposed on the side of the first sub-trench away from the signal line 31, and the second sub-trench communicating with a plurality of first sub-trenches;
[0062] When forming the first isolation sublayer 611 that fills the first sub-groove, a second isolation sublayer 612 that fills the second sub-groove is also formed.
[0063] In some embodiments, the sidewalls of the contact hole expose two first isolation sublayers 611 adjacent to the contact hole.
[0064] In some embodiments, the orthographic projection of the contact hole on the substrate 1 is located outside the orthographic projection of the first isolation sublayer 611 on the substrate 1, or the orthographic projection of the contact hole on the substrate 1 overlaps with the orthographic projection of the first isolation sublayer 611 on the substrate 1.
[0065] The technical solution of this embodiment is further illustrated below through the manufacturing process of the semiconductor device in this embodiment. In this embodiment, a film pattern is formed through a patterning process or a photolithography process. The "patterning process" mentioned in this embodiment includes film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this embodiment includes film coating, mask exposure, and development, which are mature manufacturing processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film of a certain material manufactured on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or photolithography process during the entire manufacturing process, it can also be called a "layer." If the "thin film" requires a patterning process or photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning or photolithography process contains at least one "pattern".
[0066] In an exemplary embodiment, signal line 31 may be a common bit line, and the manufacturing process of the semiconductor device may include:
[0067] 1) Forming a stacked structure and the first hole T1;
[0068] A stacked structure is formed by sequentially and alternately depositing a first insulating film and a sacrificial layer film on a substrate 1; the stacked structure may include a stack of multiple alternating first insulating layers 11 and multiple sacrificial layers 10.
[0069] The stacked structure is etched along a direction perpendicular to the substrate 1 to form a first hole T1 penetrating the stacked structure; the first hole T1 may extend along a first direction X. Figure 2 As shown, Figure 2 This is a cross-sectional view along the AA' direction perpendicular to the substrate 1 after the formation of the stacked structure and the first hole T1 is provided in some embodiments.
[0070] In some embodiments, substrate 1 may be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. The substrate may be a conventional silicon substrate or other bulk substrate including a layer of semiconductor material.
[0071] In some embodiments, the first insulating film may be a low-K dielectric layer, i.e., a dielectric layer with a dielectric constant not greater than 3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO2). The materials of the multiple first insulating layers 11 may be the same or different.
[0072] In some embodiments, the sacrificial layer film includes a film layer with a greater etching selectivity than the first insulating film, including but not limited to SiN (silicon nitride).
[0073] In some embodiments, the first insulating film and the sacrificial layer film can be deposited using a chemical vapor deposition method.
[0074] Figure 2 The number of stacked layers shown in the diagram is merely an example. In other embodiments, the stacked structure may include more or fewer alternating layers of a first insulating layer 11 and a sacrificial layer 10.
[0075] 2) Form signal line 31;
[0076] Based on the first hole T1, the sacrificial layer 10 is etched laterally (i.e., etched along a direction parallel to the substrate 1) to form the first lateral groove A1;
[0077] A first conductive film is deposited, which fills the first hole T1 and the first lateral groove A1. The first conductive film in the first hole T1 is removed by etching, while the first conductive film in the first lateral groove A1 is retained to form a signal line 31. The signal line 31 is filled in the first lateral groove A1 to form a square ring structure.
[0078] A second insulating film is deposited, which fills the first hole T1 to form a second insulating layer 12; as shown. Figure 3 As shown, Figure 3 A cross-sectional view along the AA' direction perpendicular to the substrate 1 after forming the signal line 31, as provided in some embodiments.
[0079] In some embodiments, the first conductive film may be one or more of the following different types of materials:
[0080] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can be a metal alloy containing these metals.
[0081] Alternatively, it can be conductive metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), and indium oxide (InO); or conductive metal nitride materials like titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).
[0082] Alternatively, it could be polycrystalline silicon, silicon, germanium, silicon-germanium, etc., which become conductive after doping.
[0083] The materials used for the second conductive thin film are similar and will not be described in detail here.
[0084] In some embodiments, the second insulating film may be polycrystalline silicon or the like.
[0085] 3) Forming an isolation layer 61;
[0086] The aforementioned structure is patterned to form a second trench T2. The second trench T2 may include a second sub-trench T22 extending along the first direction X and a plurality of first sub-trench T21 extending along the second direction Y and spaced apart along the first direction X. The first sub-trench T21 and the second sub-trench T22 penetrate the stacked structure, and the second sub-trench T22 and the plurality of first sub-trench T21 are connected. The first sub-trench T21 is disposed between the second sub-trench T22 and the first hole T1, and the first sub-trench T21 exposes the multiple layers of signal lines 31.
[0087] A thin insulating film is deposited to form an insulating layer 61 that fills the first sub-trench T21 and the second sub-trench T22, such as... Figure 4A and Figure 4B As shown, Figure 4A This is a cross-sectional view along the AA' direction perpendicular to the substrate 1 after the formation of the isolation layer 61, as provided in some embodiments. Figure 4B The image shows a cross-sectional view along the BB' direction perpendicular to the substrate 1 after the formation of the isolation layer 61, as provided in some embodiments. The isolation layer 61 may include a first isolation sub-layer 611 filling a first sub-trench T21 and a second isolation sub-layer 612 filling a second sub-trench T22.
[0088] In some embodiments, the isolation layer film may be an insulating film layer that has an etching selectivity ratio with the sacrificial layer film, such as SiO2.
[0089] 4) Multiple contact holes are formed;
[0090] The stacked structure is patterned to form multiple contact holes, which are disposed between adjacent first sub-trenches T21. The contact holes extend in a direction perpendicular to the substrate 1. The bottom wall of each contact hole exposes a sacrificial layer 10, and the sacrificial layer 10 exposed on the bottom wall of different contact holes is different. The sidewalls of the contact holes expose the sidewalls of two adjacent first isolation sub-layers 611. The number of contact holes is related to the number of signal lines 31, and the bottom wall of each contact hole exposes a sacrificial layer 10 on the same layer as one signal line 31. The multiple contact holes can be formed in one or more rows distributed along the first direction X, for example, two rows.
[0091] Taking an 8-layer signal line 31 as an example, there are a total of 8 contact holes C1 to C8, forming two rows of 4 contact holes each. The 4 contact holes in the first row (i.e., the row of contact holes closest to the signal line 31, contact holes C1 to C4) expose the 4 sacrificial layers 10 starting from the topmost sacrificial layer 10. The 4 contact holes in the second row (contact holes C5 to C8) expose the 4th sacrificial layer 10 to the 1st sacrificial layer 10 (the sacrificial layer 10 closest to the substrate 1 is called the first sacrificial layer 10). Figure 5A and Figure 5B As shown, Figure 5A A cross-sectional view along the BB' direction perpendicular to the substrate 1 after forming multiple contact holes, as provided in some embodiments. Figure 5B A cross-sectional view along the CC' direction perpendicular to the substrate 1 after forming a plurality of contact holes, provided for some embodiments. Figure 5A and Figure 5B In the arrangement shown, the subsequent formation of connection electrodes 32 in the contact holes allows the overlapping connection electrodes 32 projected onto the substrate 1 to be spaced as far apart as possible along the direction perpendicular to the substrate 1, thereby reducing parasitic capacitance. However, the embodiments disclosed herein are not limited to this. Figure 5A and Figure 5B The arrangement of contact holes exposing different sacrificial layers 10 is only an example and can be other arrangements.
[0092] In some embodiments, the formation process of contact holes Ci,i, where i is 1 to 8, is as follows:
[0093] The first insulating layer 11 is etched along a direction perpendicular to the substrate 1, or the first insulating layer 11 and the sacrificial layer 10 are etched until the sacrificial layer 10 corresponding to the contact hole Ci is exposed; the first isolation sub-layer 611 may or may not be etched; when the orthographic projection of the contact hole Ci on the substrate 1 overlaps with the orthographic projection of the first isolation sub-layer 611 on the substrate 1, a portion of the first isolation sub-layer 611 is etched when the contact hole Ci is formed; when the orthographic projection of the contact hole Ci on the substrate 1 does not overlap with the orthographic projection of the first isolation sub-layer 611 on the substrate 1, the first insulating layer 11 and the sacrificial layer 10 are etched until the sidewall of the adjacent first isolation sub-layer 611 is exposed.
[0094] After sequentially depositing a third insulating film and a barrier film, the layers are smoothed to form a third insulating layer 13 covering the bottom and sidewalls of the contact hole Ci and a barrier layer 62 filling the contact hole Ci. The above steps are repeated to form contact holes C1 to C8. The method for forming contact holes C1 to C8 described above is merely an example; multiple contact holes can be formed in other ways. The order in which contact holes C1 to C8 are formed is not limited.
[0095] In some embodiments, the third insulating film may be an insulating film layer that has an etching selectivity ratio with the sacrificial layer film, such as SiO2.
[0096] In some embodiments, the barrier layer film may be a material such as silicon carbide (SOC) that is easy to fill deep holes.
[0097] 5) Multiple contact holes are exposed;
[0098] Etching removes the barrier layer 62 in each contact hole, exposing the third insulating layer 13 in each contact hole, such as... Figure 6A and Figure 6B As shown, Figure 6A A cross-sectional view along the BB' direction perpendicular to the substrate 1 after exposing multiple contact holes, as provided in some embodiments. Figure 6B A cross-sectional view along the CC' direction perpendicular to the substrate 1 after exposing multiple contact holes, as provided in some embodiments.
[0099] In some embodiments, when the barrier layer film is SOC, the barrier layer 62 can be removed by introducing high-temperature oxygen to cause the SOC to volatilize.
[0100] 6) Expose sacrificial layer 10;
[0101] The third insulating layer 13 on the bottom wall of each contact hole is etched away to expose the sacrificial layer 10, while the third insulating layer 13 on the sidewall of each contact hole is retained. Figure 7A and Figure 7B As shown, Figure 7A A cross-sectional view along the BB' direction perpendicular to the substrate 1 after exposing the sacrificial layer 10, as provided in some embodiments. Figure 7B A cross-sectional view along the CC' direction perpendicular to the substrate 1 after exposing the sacrificial layer 10, provided for some embodiments. In some embodiments, the third insulating layer 13 on the bottom wall of the contact hole can be removed by dry etching.
[0102] 7) Form connecting electrode 32;
[0103] Based on the contact holes, the sacrificial layer 10 is etched laterally to expose the signal line 31, forming a channel A2. Each contact hole corresponds to one channel A2. The channel A2 is located between adjacent first sub-trench T21 and second sub-trench T22 and the signal line 31. Specifically, for the contact holes in the first row, the channel A2 is located between the contact holes in the adjacent second row and the signal line 31; for the contact holes in the second row, the channel A2 is located between the second sub-trench T22 and the signal line 31.
[0104] A second conductive film is deposited to form a connection electrode 32 that fills the contact hole and the channel A2, such as... Figure 1C and Figure 1D As shown.
[0105] In some embodiments, the connecting electrode 32 may include a first sub-layer and a second sub-layer. The first sub-layer covers the sidewalls and bottom wall of the contact hole and the channel A2, and the second sub-layer fills the contact hole and the channel A2. The first sub-layer may be a film layer with good adhesion, such as titanium nitride, and the second sub-layer may be a film layer with low resistivity, such as tungsten. That is, the first sub-conductive film and the second sub-conductive film can be deposited sequentially to form the first sub-layer and the second sub-layer.
[0106] This disclosure also provides an electronic device, including the semiconductor device described in any of the foregoing embodiments, or a semiconductor device formed by the manufacturing method of the semiconductor device described in any of the foregoing embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.
[0107] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.
Claims
1. A semiconductor device, characterized in that, include: Multiple signal lines stacked on a substrate in a direction perpendicular to the substrate and distributed in multiple layers, and multiple connection electrodes disposed on the same side of the multiple signal lines, the multiple connection electrodes and the signal lines are distributed in a second direction; the signal lines extend in a direction parallel to the substrate; each connection electrode includes a horizontal portion extending in a direction parallel to the substrate and a vertical portion extending in a direction perpendicular to the substrate connected to the horizontal portion, the horizontal portion of each connection electrode is distributed in different layers and connected to a signal line in the same layer; the multiple vertical portions of the multiple connection electrodes are spaced apart in a first direction, or arranged in an array along the first direction and the second direction; a first sub-trench extending in the second direction and penetrating multiple layers, spaced apart from adjacent connection electrodes along the first direction, and a first isolation sub-layer filling the first sub-trench, the first direction and the second direction intersect.
2. The semiconductor device according to claim 1, characterized in that, The horizontal portion extends along the second direction, and the vertical portions of the plurality of the connecting electrodes form two rows. The horizontal portion of the connecting electrodes in the first row, which is close to the signal line and distributed along the first direction, is disposed between the signal line connected to the connecting electrodes and the vertical portion of the connecting electrodes adjacent to each other along the second direction.
3. The semiconductor device according to claim 2, characterized in that, The semiconductor device further includes a second isolation sublayer that extends through multiple layers in a direction perpendicular to the substrate and extends along the first direction. The second isolation sublayer is disposed on the side of the first isolation sublayer away from the signal line and is connected to the first isolation sublayer. A plurality of the connection electrodes are disposed between the second isolation sublayer and the signal line.
4. The semiconductor device according to claim 3, characterized in that, The horizontal portion of the second row of connecting electrodes, distributed along the first direction away from the signal line, is connected at one end to the signal line and at the other end to the second isolation sublayer.
5. The semiconductor device according to any one of claims 1 to 4, characterized in that, The semiconductor device further includes a third insulating layer that wraps around the sidewall of the vertical portion and is connected to the first isolation sublayer.
6. The semiconductor device according to claim 5, characterized in that, The orthographic projection of the third insulating layer on the substrate overlaps with the orthographic projection of at least one of the two adjacent first isolation sublayers on the substrate, or the orthographic projection of the third insulating layer on the substrate is located outside the orthographic projection of the two adjacent first isolation sublayers on the substrate, and the orthographic projection of the third insulating layer on the side facing the first isolation sublayer falls on the boundary of the orthographic projection of the first isolation sublayer on the substrate.
7. A method for manufacturing a semiconductor device, characterized in that, include: A stacked structure comprising multiple alternating first insulating layers and sacrificial layers is formed on a substrate. The stacked structure is patterned to form multiple signal lines, and the multiple signal lines are respectively disposed on different sacrificial layers. A plurality of first sub-trenches are formed on the same side of the signal lines, extending along a second direction and spaced apart along a first direction through the stacked structure, with the first sub-trenches exposing the sidewall of each signal line; and a first isolation sub-layer is formed to fill the first sub-trenches. Contact holes extending perpendicular to the substrate direction are formed between adjacent first isolation sublayers, and the bottom wall of each contact hole exposes a sacrificial layer containing a signal line; A third insulating layer is formed to cover the sidewalls of the contact hole; Based on the contact hole, the sacrificial layer is etched along a direction parallel to the substrate to expose the signal line, forming a second lateral groove; A connecting electrode is formed that fills the contact hole and the second transverse groove.
8. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The method further includes: forming a second sub-trench extending along a first direction through the stacked structure, the second sub-trench being disposed on the side of the first sub-trench away from the signal line, and the second sub-trench being connected to a plurality of first sub-trenches; When forming the first isolation sublayer that fills the first sub-groove, a second isolation sublayer that fills the second sub-groove is also formed.
9. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The sidewall of the contact hole exposes two first isolation sublayers adjacent to the contact hole.
10. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The orthographic projection of the contact hole onto the substrate is located outside the orthographic projection of the first isolation sublayer onto the substrate, or the orthographic projection of the contact hole onto the substrate overlaps with the orthographic projection of the first isolation sublayer onto the substrate.
11. An electronic device, characterized in that, It includes the semiconductor device as described in any one of claims 1 to 6, or the semiconductor device formed by the manufacturing method of the semiconductor device as described in any one of claims 7 to 10.