Interconnects for enhancing reliability and performance of semiconductor packages
By designing cavities on the top surface of the lead pads to accommodate solder bumps, the problem of solder bump propagation and peeling during temperature cycling is solved, thereby improving the reliability and performance of semiconductor packaging.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- TEXAS INSTRUMENTS INC
- Filing Date
- 2025-12-19
- Publication Date
- 2026-07-10
AI Technical Summary
In semiconductor packaging, solder bumps are prone to propagation and peeling during temperature cycling, leading to connection errors and stress failures, which are difficult to solve effectively with existing technologies.
A cavity is formed on the top surface of the lead pad to accommodate a portion of the solder bump, reducing solder spread and flow, and lowering the stress on the bottom side of the solder bump. The cavity is designed on the top surface of the lead to improve the fixation of the solder bump.
It effectively reduces solder spread and flow, lowers the risk of solder bumps peeling off during temperature cycling, and improves connection reliability and stability.
Smart Images
Figure CN122373850A_ABST
Abstract
Description
Technical Field
[0001] This specification relates to semiconductor packages and interconnects that enhance performance and reliability. Background Technology
[0002] Many semiconductor packages include interconnects for providing inputs and outputs to semiconductor dies on the package. In various packages, the semiconductor die is attached directly or via a molded interconnect substrate (MIS) to the individual leads of the interconnect, which are coupled to the individual leads of the interconnect. Each lead of the interconnect is coupled to the MIS / semiconductor die via lead pads and solder bumps or solder paste between the lead and the MIS / semiconductor die. Summary of the Invention
[0003] The first example relates to a semiconductor package. The semiconductor package includes interconnects, each interconnect including leads. Each lead has a cavity on its top surface. The semiconductor package also includes a semiconductor die electrically coupled to the leads. Each cavity in the leads accommodates a portion of a solder bump.
[0004] The second example relates to an interconnect for a semiconductor package. The interconnect includes leads. Each lead has a top surface with a cavity for receiving solder. The interconnect also includes a baffle mechanically coupled to each of the leads to reduce relative movement of the leads.
[0005] A third example relates to a method of forming a semiconductor package. The method includes applying solder to cavities on leads of an interconnect. The cavities are on the top surface of the respective leads. The method further includes mounting a molded interconnect substrate (MIS) on the interconnect. The method additionally includes mounting a semiconductor die electrically coupled to the MIS. The method further includes encapsulating the MIS, the semiconductor die, and a portion of the interconnect in a molding compound. Attached Figure Description
[0006] Figure 1A A portion of an example semiconductor package with interconnect leads is shown, the leads having corresponding cavities on their respective top surfaces for receiving portions of corresponding solder bumps.
[0007] Figure 1B It shows Figure 1A A close-up view of the dashed area shows a cavity in the lead that houses a portion of the solder bump that couples the lead to the molded interconnect substrate (MIS).
[0008] Figure 2AAn example semiconductor package including leads is shown, the leads having cavities on their top surfaces to accommodate corresponding portions of solder bumps for coupling the leads to a MIS for coupling the leads to a semiconductor die.
[0009] Figure 2B It shows Figure 2A The example semiconductor package shows a MIS (Mechanical Interconnect) that couples a semiconductor die to the leads of an interconnect.
[0010] Figure 2C It shows Figure 2A A perspective view of an example interconnect in an example semiconductor package.
[0011] Figure 2D It shows Figure 2C The close-up side view of the dashed area shows two leads with corresponding cavities formed in the top surface to accommodate solder bumps.
[0012] Figure 2E It shows Figure 2D The dashed area is a close-up side view showing a lead pad with a cavity that accommodates a portion of a solder bump.
[0013] Figure 3 An example interconnect and MIS perspective view of a semiconductor package are shown.
[0014] Figure 4 An example interconnect is shown, wherein a cavity is present on the top surface of the lead pad of the interconnect lead.
[0015] Figure 5 An example interconnect is shown, in which solder bumps are partially housed in cavities on the top surface of the lead pads of the interconnect leads.
[0016] Figure 6 An example MIS is shown that couples a semiconductor die to an interconnect having a cavity on the top surface of the lead for accommodating portions of solder bumps.
[0017] Figure 7 An example interconnect is shown coupled to an example MIS via solder bumps, which are partially housed within cavities formed on the top surface of the interconnect leads.
[0018] Figure 8 An example interconnect is shown coupled to a semiconductor die via an example MIS, which is coupled to the interconnect via solder bumps partially housed within cavities formed on the top surface of the leads of the interconnect.
[0019] Figure 9An example semiconductor package including leads is shown, the leads having cavities on their top surfaces to accommodate corresponding portions of solder bumps for coupling the leads to a MIS for coupling the leads to a semiconductor die.
[0020] Figure 10 A table showing an example interconnect with leads and a cavity on the top surface of the leads for receiving solder bumps is provided for comparison with an interconnect with flat leads.
[0021] Figure 11 An example method for forming a semiconductor package is shown, the semiconductor package comprising interconnects with leads having cavities on respective top surfaces for receiving portions of respective solder bumps. Detailed Implementation
[0022] This specification relates to an interconnect comprising leads having cavities on the top surface of lead pads, and also to a semiconductor package comprising such an interconnect. The cavities on the top surface are shaped to receive and accommodate a portion of solder bumps that electrically couple the leads to a semiconductor die, for example, directly or via a molded interconnect substrate (MIS).
[0023] In interconnects where the leads do not have cavities in the lead pads, solder paste may spread and / or flow along the lead sidewalls during reflow soldering and / or after solder is applied to the lead pads. Spread of solder paste from the application site on the lead pads or flow along the lead sidewalls can lead to connection errors between the lead and the MIS. Additionally, at the location of solder bumps, several components share multiple interfaces; mismatched coefficients of thermal expansion (CTE) of these components result in external shear stress, which can cause solder bumps to peel off during temperature cycling.
[0024] Various examples include interconnects with leads having cavities on the top surface of the lead pads for receiving solder. The cavities accommodate a portion of the solder bump, thereby reducing solder spread and flow along the lead sidewalls. The contact area between the solder and the lead pads is increased by accommodating a portion of the solder bump within the cavity. Additionally, the examples reduce stress near the cavity on the underside of the solder bump, thus lowering the risk of solder bump peeling during temperature cycling.
[0025] Figure 1AA portion of an example semiconductor package 100 (e.g., a small shrink outline package (SSOP) or another semiconductor package that may be larger or smaller than an SSOP) is shown, wherein the leads 101 and 102 of the interconnects (e.g., having a pitch of 0.7 mm or less in one example, but in other examples, the size of leads 101 and 102 may be larger or smaller, and / or may vary based on the size and type of the semiconductor package 100, etc.) have respective cavities 103 and 104 (e.g., having a circular profile, etc.) on their respective top surfaces to receive portions of respective solder bumps 105 and 106. For ease of illustration, solder bumps (e.g., solder bumps 105 and 106, etc.) are discussed herein in conjunction with examples. However, in various examples, solder paste may be used instead of solder bumps. The example semiconductor package 100 also includes a molded interconnect substrate (MIS) 107, which is coupled to a semiconductor die 108, for example via solder attachment to a set of pillars, such as copper pillars 109. Molding compound 110 encapsulates semiconductor die 108, MIS 107, solder bumps 105 and 106, and portions of interconnects (e.g., portions of leads 101 and 102 containing cavities 103 and 104).
[0026] In the example semiconductor package 100, leads 101 and 102 are leads for interconnects (e.g., in some examples, lead frames, etc.). In one example, leads 101 and 102 are coated with nickel, palladium, and gold, but in various examples, the materials of leads 101 and 102 can be varied, including variations based on the selection of other materials in the semiconductor package. Cavities 103 and 104 of leads 101 and 102 receive corresponding solder bumps 105 and 106 (or solder paste, etc.) such that solder propagation of solder bumps 105 and 106 is reduced, and the sidewalls of leads 101 and 102 are free of solder. Cavities 103 and 104 are configured to receive corresponding portions of solder bumps 105 and 106 and resist deformation of solder bumps 105 and 106 during temperature cycling (e.g., throughout the operating temperature range, during temperature ramps and ramps, etc.). Additionally, cavities 103 and 104 are configured to reduce stress on the respective bottom portions of solder bumps 105 and 106. In the example semiconductor package 100, the depths of cavities 103 and 104 are approximately equal to half the heights of solder bumps 105 and 106. In one example, cavities 103 and 104 have a depth of approximately 30 micrometers and a diameter of approximately 250 micrometers. In various examples, cavities 103 and 104 are formed via etching. The size and shape of cavities 103 and 104 (e.g., relative to lead pads and / or solder bumps 105 and 106, etc.) have advantages over alternative cavities. For example, smaller cavities increase the likelihood of solder spreading out of the cavity, including downward spreading along the outer sidewalls of the leads. Alternatively, larger cavities reduce the thickness of the lead sidewalls, increasing the likelihood of lead breakage.
[0027] Figure 1B It shows Figure 1A A close-up view of the dashed area shows a cavity 103 in lead 101 for receiving and accommodating a portion of solder bump 105 that couples lead 101 to MIS 107. In the example semiconductor package 100, cavity 103 has an inclined inner surface 111 that extends upward from a flat bottom surface 112 (e.g., parallel to the top surface of lead 101 in the example semiconductor package 100, etc.) to (e.g., to the top surface of lead 101, to a vertical inner surface extending to the top surface of lead 101, etc.).
[0028] Figure 2A An example semiconductor package 200 (e.g., as an example of semiconductor package 100, etc.) is shown, which is a 16-pin semiconductor package containing leads 201-216 (e.g., leads of interconnects such as lead frames), wherein a cavity is provided on the top surface of the inner portion of the leads 201-216 for receiving and accommodating corresponding portions of solder bumps for coupling the leads 201-216 to MIS 217, which couples the leads 201-216 to semiconductor dies 218 and 219. MIS 217, semiconductor dies 218 and 219, and portions of leads 201-216 are encapsulated in molding compound 220.
[0029] Figure 2B A sample semiconductor package 200 illustrates a MIS 217 that couples semiconductor dies 218 and 219 to leads 201-216 of interconnects. In various examples, the specific design of the MIS (e.g., MIS 217, etc.) depends on the number and design of the semiconductor dies (e.g., semiconductor dies 218 and 219, etc.) and interconnects (e.g., interconnects containing leads 201-216, etc.) that the MIS is designed to couple together.
[0030] Figure 2C A perspective view of an example interconnect 221 of an example semiconductor package 200 is shown. The example interconnect 221 includes leads 201-216, wherein solder bumps 222-237 are partially accommodated in corresponding cavities of the lead pads of leads 201-216. Figure 2D It shows Figure 2CA close-up side view of the dashed area shows leads 201 and 202 with corresponding cavities 238 and 239 formed in the top surface to accommodate solder bumps 222 and 223, respectively. In the example interconnect 221, the lead pads 240 and 241 of leads 201 and 202 have dimensions of approximately 440 micrometers by 440 micrometers, but various examples may have larger, smaller, and / or different shaped lead pads. Cavities 238 and 239 have a diameter of approximately 250 micrometers at the top surface of the leads and a depth of approximately 30 micrometers, accommodating a portion of the corresponding solder bumps 222 and 223, the portion being approximately equal to half the height of the solder bumps 222 and 223. The dimensions of cavities 238 and 239 (e.g., relative to the lead pads and / or solder bumps 222 and 223, etc.) have advantages over alternative geometries. Smaller cavities increase the likelihood of solder flowing across the lead sidewalls or otherwise spreading out of the cavities. Larger cavities reduce the thickness of the leads around the cavity, increasing the likelihood of lead breakage. As an additional example, hemispherical cavities (rather than flat-bottomed cavities) increase stress on the underside of solder bumps (or solder paste, etc.), increasing the likelihood of solder peeling off the lead pads during temperature cycling.
[0031] Figure 2E It shows Figure 2D The dashed-lined area shows a close-up side view of the lead pad 240 of lead 201, where cavity 238 receives and accommodates a portion of solder bump 222. In example interconnect 221, cavity 238 has a beveled edge 242 that extends upward from flat bottom surface 243 to the top side of lead pad 240 of lead 201.
[0032] Cavity 238 significantly reduces the stress on the underside of solder bump 222 in example interconnect 221. Mechanical stress modeling of one example shows that the stress on the underside of solder bump 222 is reduced by approximately 58% (e.g., where the stress in example interconnect 221 is 63.4 MPa, compared to 150 MPa for solder bumps deposited on flat lead pads, etc.). The underside of solder bumps (e.g., solder bump 222, etc.) is a common point of failure. Cavity 238 reduces the stress on the underside of solder bump 222, thereby reducing the risk of failure (e.g., due to temperature cycling, etc.).
[0033] refer to Figure 3 The image shows a perspective view of an example interconnect 300 coupled to a semiconductor die 310 of a semiconductor package. Figure 3An example of an interconnect 300 directly coupled to a semiconductor die 310 via flip-chip technology is shown. The leads of the interconnect 300 include cavities on their top surfaces (e.g., facing the semiconductor die 310) for receiving portions of corresponding solder bumps used to couple the interconnect 300 and the semiconductor die 310. Because the portions of the solder bumps are received in cavities, solder propagation and flow along the lead sidewalls are reduced, increasing the contact area between the solder bumps and the leads of the interconnect 300. Additionally, the reduced stress on the bottom side of the solder bumps also reduces external shear stresses that could cause solder bump failure during temperature cycling.
[0034] Figure 4-9 The various stages of forming a semiconductor package are illustrated, the semiconductor package including interconnects (e.g., interconnect 221, interconnect 300, etc.), wherein a cavity for receiving solder is provided on the top surface of the lead pads of the interconnect leads.
[0035] Figure 4 An example interconnect 400 is shown, wherein a cavity for receiving solder is provided on the top surface of the lead pads of the interconnect 400 leads. The example interconnect 400 (e.g., a lead frame) may include leads coupled to one of two baffles 410 and 420, which reduce relative movement of the leads and facilitate alignment of the interconnect 400 with a MIS (e.g., MIS 107, MIS 217, etc.) after solder bumps are applied to the interconnect 400. Figure 5 An example interconnect 500 is shown, wherein solder bumps are partially accommodated in cavities on the top surface of the lead pads of the interconnect 500's leads. The example interconnect 500 includes leads coupled to one of two baffles 510 and 520, which reduce relative movement of the leads and facilitate alignment of the interconnect 400 with MIS (e.g., MIS 107, MIS 217, etc.), for example, via solder bump reflow and curing. Figure 6 An example MIS 600 is shown, which couples a semiconductor die to interconnects (e.g., interconnects 221, 300, 400, 500, etc.), wherein the top surface of the lead has a cavity for receiving solder bumps. In one example, the top side of the MIS 600 is rough copper, and its back side contains nickel, palladium, and gold.
[0036] refer to Figure 7An example interconnect 700 is shown, coupled to an example MIS 710 via solder bumps, the solder bumps being partially housed within cavities formed on the top surface of the leads of the interconnect 700 to receive portions of the solder bumps (e.g., by reflowing and curing the solder bumps applied to the interconnect 700). The leads of the interconnect 700 are coupled in two sets via baffles 720 and 730, reducing relative movement of the leads and facilitating alignment of the MIS 710 on the interconnect 700 prior to the removal of baffles 720 and 730.
[0037] Figure 8 An example interconnect 800 is shown coupled to semiconductor dies 810 and 820 via an example MIS 830, which is coupled to the interconnect 800 via solder bumps that partially receive and are housed within cavities formed on the top surface of the leads of the interconnect 800. The leads of the interconnect 800 are coupled in two sets by baffles 840 and 850, reducing relative movement of the leads and facilitating alignment of the MIS 830 on the interconnect 800 before the baffles 840 and 850 are removed. In one example, semiconductor dies 810 and 820 are attached via flip-chip die technology, for example by flipping semiconductor dies 810 and 820, immersing solder bumps of semiconductor dies 810 and 820 in flux, attaching semiconductor dies 810 and 820 to MIS 830, reflowing solder bumps on semiconductor dies 810 and 820, and curing solder bumps to couple semiconductor dies 810 and 820 to MIS 830.
[0038] Figure 9 An example semiconductor package 900 (e.g., as an example of semiconductor package 100, etc.) including leads 901-916 (e.g., leads of interconnects such as interconnect 700, interconnect 800, etc.) is shown, wherein a cavity is provided on the top surface of the leads 901-916 to receive corresponding portions of solder bumps for coupling the leads 901-916 to MIS 917, which couples the leads 901-916 to semiconductor dies 918 and 919. Figure 7 and 8 The baffles shown have been removed, and portions of MIS 917, semiconductor dies 918 and 919, and leads 901-916 have been encapsulated in molding compound 920, which has been trimmed (e.g., removing baffles 720 and 730 or baffles 840 and 850 and separating leads, etc.) and formed leads, thereby forming semiconductor package 900.
[0039] Figure 10This table compares an example interconnect with a cavity containing leads and a portion on the top surface of the leads that accommodates solder bumps, to an interconnect with flat leads. For the lead dimensions of the example interconnect (e.g., lead pads approximately 440 μm by approximately 440 μm, etc.), a cavity with a diameter of approximately 250 μm and a depth of approximately 30 μm generates a stress of 63.4 MPa on the underside of the solder bump, approximately 42% of the 150 MPa stress on the underside of a solder bump deposited on the top surface of a lead with a flat top surface. While the stress on the top side of the solder bump of the example interconnect (158 MPa) is slightly higher than that of the flat lead (138 MPa), the top side of the solder bump is not a common failure point, unlike the bottom side of the solder bump, which involves several components sharing multiple interfaces and has a mismatch in coefficients of thermal expansion, resulting in shear stress during temperature cycling.
[0040] Figure 11 A method 1100 for forming a semiconductor package including interconnects, the interconnects having leads having cavities on respective top surfaces to receive respective solder bumps, for example... Figure 2A Semiconductor package 200 or Figure 9 900 semiconductor packaging.
[0041] At 1110, method 1100 includes a cavity (e.g., formed in the top surface of the interconnect lead, for example, via etching, stamping, etc.) Figure 1B Cavity 103 in the top surface of lead 101 Figure 2D Solder is applied to cavities 238 and 239, etc., of the leads 201 and 202. In some examples, the interconnect is a lead frame, but in other examples, solder is applied to cavities in different interconnects.
[0042] At 1120, method 1100 includes adding a MIS (e.g., Figure 1A-1B MIS 107 Figure 2A-2B MIS 217, Figure 6 MIS 600 Figure 7 MIS 710, Figure 8 MIS 830 Figure 9 The MIS (such as MIS 917) is mounted onto the interconnect. In various examples, the MIS is mounted onto the interconnect by attaching the MIS to the interconnect and resoldering the solder applied at 1110, which cures to couple the MIS to the interconnect.
[0043] At 1130, method 1100 includes placing at least one semiconductor die (e.g., Figure 1A Semiconductor bare die 108, Figure 2A Semiconductor dies 218 and / or 219, Figure 8 Semiconductor dies 810 and / or 820, Figure 9 Semiconductor dies 918 and / or 919, etc., are mounted onto the MIS. Alternatively, in examples without an MIS, the semiconductor dies are directly mounted onto the interconnects. In various examples, the semiconductor dies are attached via flip-chip die technology, such as by flipping the semiconductor die, immersing solder bumps on the semiconductor die in flux, and attaching the semiconductor die to the interconnects. The attachment of the semiconductor die to the interconnects is performed directly or via attaching the semiconductor die to the MIS, reflowing the solder bumps on the semiconductor die, and curing the solder bumps to couple the semiconductor die to the MIS.
[0044] At 1140, method 1100 includes molding compound (e.g., Figure 1A-1B Molding compound 110, Figure 2A Molding compound 220, Figure 9 The molding compound 920, etc., encapsulates portions of the MIS (containing the MIS in the example), semiconductor die, and interconnects. In various examples, any of the various molding compounds is used to encapsulate portions of the MIS, semiconductor die, and interconnects. Because the portion accommodating the solder bump in the cavity on the top surface of the interconnect lead reduces the stress on the underside of the solder bump, the various examples have greater tolerance to variations in the coefficient of thermal expansion (CTE) of the molding compound compared to interconnects where solder is applied to the flat top surface of the lead.
[0045] At 1150, method 1100 includes trimming the interconnects (e.g., removing any baffles, such as...). Figure 4 The baffles 410 and 420, Figure 5 The baffles 510 and 520 Figure 7 The baffles 720 and 730, Figure 8 baffles 840 and 850, etc., are used to form individual leads and form semiconductor packages (e.g., Figure 2A Semiconductor packaging 200 Figure 9 Semiconductor packaging 900, etc.
[0046] In this specification, unless otherwise stated, "about," "approximately," or "substantially" before a parameter means a difference of no more than + / - 10% from the parameter. Within the scope of the claims, modifications are possible in the described embodiments, and other embodiments are also possible.
[0047] In this specification, the term "coupled" may encompass a connection, communication, or signaling path that enables the functional relationship to be consistent with this description. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first example, device A is coupled to device B via a direct connection; or (b) in a second example, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.
[0048] The phrase “based on” means “at least partially based on”. Therefore, if X is based on Y, then X can be a function of Y and any number of other factors.
[0049] Within the scope of the claims, modifications are possible in the described embodiments, and other embodiments are also possible.
Claims
1. A semiconductor package comprising: Interconnectors, including leads, each lead having a top surface with a cavity; as well as A semiconductor die electrically coupled to the leads; Each cavity in the lead contains a portion of a solder bump.
2. The semiconductor package according to claim 1, further comprising: A molded interconnect substrate (MIS) is mounted on the interconnect, wherein the semiconductor die is mounted on the MIS and electrically coupled to the leads through the MIS and through solder bumps of the leads.
3. The semiconductor package of claim 2, further comprising a molding compound encapsulating a portion of the semiconductor die, the MIS, and the interconnect.
4. The semiconductor package of claim 1, wherein each cavity includes a sloping edge extending from the bottom surface of the respective cavity to the top surface of the respective lead.
5. The semiconductor package of claim 4, wherein the bottom surface of each cavity is flat.
6. The semiconductor package of claim 1, wherein the sidewalls of the leads are free of solder.
7. The semiconductor package of claim 1, wherein the semiconductor package is a Small Shrink Profile Package (SSOP).
8. The semiconductor package of claim 3, wherein the leads have a spacing of 0.7 mm or less.
9. The semiconductor package of claim 1, wherein the cavity is configured to resist deformation of the solder bumps on each lead during temperature ramping and descent.
10. The semiconductor package of claim 1, wherein the depth of the cavity is approximately half the thickness of the corresponding solder bump.
11. The semiconductor package of claim 1, wherein the cavity has a depth of approximately 30 micrometers.
12. The semiconductor package of claim 1, wherein the cavity has a diameter of approximately 250 micrometers.
13. An interconnect for a semiconductor package, the interconnect comprising: Each lead has a top surface with a cavity for receiving solder. as well as A baffle bar, which is mechanically coupled to each of the leads, to reduce relative movement of the leads.
14. The interconnect of claim 13, wherein each cavity includes an inclined edge extending from the bottom surface of the respective cavity to the top surface of the respective lead.
15. The interconnect according to claim 13, wherein the leads have a spacing of 0.7 mm or less.
16. The interconnect of claim 13, wherein the cavity has a diameter of approximately 250 micrometers.
17. The interconnect according to claim 13, wherein the leads are coated with nickel, palladium and gold.
18. A method of forming a semiconductor package, the method comprising: Solder is applied to cavities on the leads of the interconnect, wherein the cavities are on the top surface of the respective leads; The molded interconnect substrate (MIS) is mounted on the interconnect; Install a semiconductor die electrically coupled to the MIS; as well as Encapsulate the MIS, the semiconductor die, and a portion of the interconnect in a molding compound.
19. The method of claim 18, further comprising trimming and forming the leads of the interconnect.
20. The method of claim 18, wherein the sidewalls of the lead are free of solder.