Electronic device

Abstract

An electronic device is provided. The electronic device includes a redistribution layer, a component disposed on the redistribution layer, and an underfill disposed between the redistribution layer and the component. The electronic device also includes an encapsulation material covering the component. The encapsulation material or the underfill defines a sidewall adjacent to the component and a surface of the component that is substantially perpendicular to the sidewall.

Description

Technical Field

[0001] This disclosure relates to an electronic device. Background Technology

[0002] Fan-out multi-chip modules (FO-MCMs) integrate multiple chips within a single package material and utilize a redistribution layer (RDL) to achieve fan-out input and output. However, traditional FO-MCMs often result in higher costs and lower yields because once packaged, damaged components cannot be removed or replaced. Summary of the Invention

[0003] In some configurations, the electronic device includes a redistribution layer, components disposed on the redistribution layer, and an underfill disposed between the redistribution layer and the components. The electronic device also includes an encapsulation material covering the components. The encapsulation material or the underfill defines sidewalls adjacent to the components and is generally perpendicular to the surface of the components.

[0004] In some configurations, the electronic device includes a redistribution layer, a chip disposed on the redistribution layer, and a memory package disposed on the redistribution layer and adjacent to the chip. The memory package includes a first encapsulation material. The electronic device also includes a second encapsulation material covering the memory package. A first interface exists between the first encapsulation material and the second encapsulation material.

[0005] In some configurations, the electronic device includes a redistribution layer, an interposer layer disposed on the redistribution layer, and an underfiller disposed between the redistribution layer and the interposer layer. The electronic device also includes a first encapsulation material covering the underfiller. The first encapsulation material or the underfiller defines an opening in the interposer layer for receiving a memory package. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that the structures are not drawn to scale, and the dimensions of the structures may be arbitrarily enlarged or reduced for ease of explanation.

[0007] Figure 1A A cross-sectional view of an electronic device configured according to this disclosure.

[0008] Figure 1B This is a partial enlarged view of an electronic device configured according to this disclosure.

[0009] Figure 1CThis is a partial enlarged view of an electronic device configured according to this disclosure.

[0010] Figure 1D This is a partial enlarged view of an electronic device configured according to this disclosure.

[0011] Figure 2A A cross-sectional view of an electronic device configured according to this disclosure.

[0012] Figure 2B This is a partial enlarged view of an electronic device configured according to this disclosure.

[0013] Figure 2C This is a partial enlarged view of an electronic device configured according to this disclosure.

[0014] Figure 2D This is a partial enlarged view of an electronic device configured according to this disclosure.

[0015] Figure 2E A cross-sectional view of an electronic device configured according to this disclosure.

[0016] Figure 2F A cross-sectional view of an electronic device configured according to this disclosure.

[0017] Figure 2G A cross-sectional view of an electronic device configured according to this disclosure.

[0018] Figures 3A-3J A cross-sectional view of one or more stages of a method for manufacturing an electronic device according to some configurations of this disclosure.

[0019] Figure 4A , 4B 4C, 4D and 4E are cross-sectional views of one or more stages of a method for manufacturing an electronic device according to some configurations of the present disclosure. Detailed Implementation

[0020] Figure 1A This is a cross-sectional view of an electronic device 1a according to some configurations of the present disclosure. The electronic device 1a may include a package, such as a semiconductor device package. In some configurations, the electronic device 1a may include a carrier 10, electronic components 11, components 12, underfill 13, and encapsulation material 14.

[0021] The carrier 10 can be configured to provide structural support for electronic components 11, 12, underfill 13, and encapsulation material 14. In some configurations, the carrier 10 can be configured to rewire or redistribute the input / output (I / O) connections of electronic components 11 and 12 for a layout more suitable for packaging or interconnection with other components. For example, the carrier 10 can be configured to rewire or redistribute the input / output connections of electronic components 11 and 12 to a circuit board (not shown in the figures) via electrical contacts 10e.

[0022] In some configurations, the line spacing of the input / output connections of electronic component 11 may be smaller or finer than the line spacing of carrier 10. For example, the line / space (L / S) ratio of the input / output connections of electronic component 11 may have a smaller range than that of carrier 10. In some configurations, the line spacing of the input / output connections of component 12 may be smaller or finer than the line spacing of carrier 10. For example, the line / space ratio of the input / output connections of component 12 may have a smaller range than that of carrier 10. In some configurations, the line spacing of the input / output connections of electronic component 11 may differ from that of component 12.

[0023] The carrier 10 may include one or more redistribution layers. For example, the carrier 10 may include one or more conductive layers and one or more dielectric layers. A portion of the conductive layer may be covered or encapsulated by the dielectric layer, while another portion of the conductive layer may be exposed outside the dielectric layer to provide electrical contacts. The conductive layer may contain a conductive material, such as a metal or metal alloy. Examples of conductive materials include gold (Au), silver (Ag), copper (Cu), platinum (Pt), palladium (Pd), other metals or alloys, or combinations of two or more of the above. The dielectric layer may contain a dielectric material, such as an epoxy-based material (e.g., an epoxy resin containing silica / alumina filler), an encapsulation (e.g., an epoxy resin encapsulation or other types of encapsulation), an Ajinomoto build-up film (ABF), polyimide (PI), benzocyclobutene (BCB), silicon oxide, silicon nitride, etc. In some configurations, the dielectric layer may contain other suitable non-conductive or insulating materials. For example, the dielectric layer may comprise a composite material consisting of a dielectric material and nanofillers dispersed therein. The transparency of the composite material may be in the range of about 50% to about 90%, and the nanofillers may be in the form of sheets, rods, core-shells, or tubes.

[0024] Electronic component 11 may be mounted on carrier 10. Electronic component 11 may be electrically connected to carrier 10, and electrical contacts may be achieved through solder bonding, Cu-Cu bonding, wire bonding, or a combination of these methods. For example, electronic component 11 may be electrically connected to the conductive layer of carrier 10 via electrical contacts 11e. In some configurations, electronic component 11 may be electrically connected to carrier 10 via metal-to-metal bonding without the need for separate bonding material.

[0025] Electronic component 11 may include a surface 111 facing the carrier 10, a surface 112 opposite to the surface 111, and a surface 113 extending between the surfaces 111 and 112. Surface 111 may be an active surface, a front surface, or a front side. Surface 112 may be a back surface or a back side. Surface 113 may be a side surface or a sidewall.

[0026] In some configurations, electronic component 11 may be a chip or die comprising a semiconductor substrate, one or more integrated circuit (IC) devices, and one or more upper metal interconnect structures. The integrated circuit devices may include active devices such as transistors and / or passive devices such as resistors, capacitors, inductors, or combinations thereof. For example, electronic component 11 may include radio frequency integrated circuits (RFICs), application-specific integrated circuits (ASICs), central processing units (CPUs), microprocessor units (MPUs), graphics processing units (GPUs), microcontroller units (MCUs), field-programmable gate arrays (FPGAs), or other types of integrated circuits. For example, electronic component 11 may include systems on chips (SoCs), system-on-modules (SoMs), system-in-package (SiPs), or other types of integrated circuits that combine multiple components together. Furthermore, the number of electronic components can be arbitrary, depending on design requirements.

[0027] Component 12 may be mounted on carrier 10. Component 12 may be adjacent to electronic component 11. Component 12 may be located near electronic component 11. In some configurations, the distance (e.g., minimum distance) between component 12 and electronic component 11 may be less than about 300 micrometers (µm). For example, this distance may be about 200µm to 300µm.

[0028] Component 12 can be electrically connected to carrier 10, and the electrical connection can be achieved by solder bonding, copper-to-copper bonding, wire bonding, or a hybrid bonding. For example, component 12 can be electrically connected to the conductive layer of carrier 10 via electrical contact 12e. In some configurations, component 12 can be electrically connected to carrier 10 via metal-to-metal bonding without the need for separate bonding materials.

[0029] In some configurations, electrical contacts 10e, 11e, and 12e may contain solder balls or solder bumps, such as controlled collapse chip connection (C4) bumps, ball grid arrays (BGAs), or pad arrays (LGAs).

[0030] Component 12 may include a surface 121 facing the carrier 10, a surface 122 opposite to the surface 121, and a surface 123 extending between the surfaces 121 and 122. Surface 121 may be an active surface, a front surface, or a front side. Surface 122 may be a back surface or a back side. Surface 123 may be a side surface or a sidewall. Surface 123 of component 12 may face surface 113 of electronic component 11.

[0031] In some configurations, component 12 can be configured to predefine the placement of another component (e.g., Figure 2A The position of the package 20 in the package. For example, component 12 can be configured as a predetermined position or mounting point for the package 20. By specifying a redistribution layer area for die placement, this configuration helps reduce manufacturing costs and improve overall yield. Furthermore, this configuration allows the package 20 to be placed after the packaging operation is complete. By delaying this step, the process can minimize potential damage to the package 20 during packaging and improve die alignment accuracy, ultimately improving product reliability and efficiency.

[0032] In some configurations, component 12 may be configured to protect carrier 10 from damage or destruction during the process of forming an opening 14h above component 12. For example, as Figure 3IIn the operation described, the opening 14h can be formed by methods such as laser cutting or chemical etching, and component 12 can act as a protective barrier, shielding the carrier 10 from the harmful effects that can be caused by the laser beam or chemical etchant. This protective function helps maintain the structural integrity of the carrier 10, ensuring that it remains intact and usable throughout the manufacturing process.

[0033] In some configurations, component 12 may contain logic dies or active components. In some configurations, component 12 may contain control logic for managing memory operations. For example, component 12 is configured to communicate with a controller (such as electronic component 11), receive instructions, addresses, and data, and forward these instructions, addresses, and data to another component (such as...). Figure 2A The encapsulation body 20 in the middle.

[0034] For example, component 12 can actively control or process electrical signals. For instance, component 12 can perform functions such as amplification, modulation, filtering, rectification, switching, and / or conversion of electrical signals transmitted to or from package 20. Specifically, data transmitted to or from package 20 can first be pre-processed by component 12. Subsequently, the processed data can be further processed or analyzed by electronic component 11. Electronic component 11 can act as a slave in a master-slave configuration, with component 12 providing control signals to electronic component 11 via carrier 10.

[0035] Alternatively, the data can be initially processed by electronic component 11 and then by component 12. This hierarchical signal processing approach improves overall system performance by ensuring that the signal is optimized before reaching its final destination within the electronic architecture.

[0036] In some configurations, component 12 may include an interposer, bridge, electrical interface, or passive component. For example, component 12 may be a silicon interposer, glass interposer, ceramic interposer, or other suitable interposer. For example, component 12 may focus on providing robust and reliable location-based functionality or protection without introducing the complexity of active circuitry. For example, component 12 may not include active components such as transistors, diodes, integrated circuits, operational amplifiers (op-amps), and similar devices.

[0037] Component 12 may include bridging metal for coupling package 20 to carrier 10. Component 12 may include one or more conductive pads 12p disposed on surface 122. The conductive pads 12p may be exposed on surface 122. The conductive pads 12p are configured to serve as another component (e.g., Figure 2A The package 20 in the package provides electrical contacts.

[0038] Component 12 may include one or more conductive vias 12v that penetrate component 12 and are electrically connected to conductive pad 12p. The conductive vias 12v may be configured to connect the carrier 10 to another component (e.g., Figure 2A Vertical electrical contacts are provided between the package 20. The conductive vias 12V may be through-silicon vias (TSVs). In some configurations, the component 12 may include one or more shielding lines disposed between adjacent conductive vias 12V. The shielding lines are configured to provide electrostatic discharge (ESD) protection and reduce electrical noise and interference.

[0039] In some configurations, circuit layer 12c may be disposed on surface 121 of component 12 and electrically connected to conductive via 12v and conductive pad 12p. In some configurations, circuit layer 12c may contain the aforementioned active devices. In some configurations, component 12 and circuit layer 12c may form a circuit with desired circuit functionality and complement another component (e.g., Figure 2A The reconfigurable interposer layer 12c is the package 20 in the package. In some other configurations, the circuit layer 12c may be omitted. For example, there may be no active device between the carrier 10 and the component 12.

[0040] In some configurations including circuit layer 12c, the line spacing of the input / output connections of circuit layer 12c may be smaller or finer than the line spacing of component 12. For example, the line spacing of the input / output connections of circuit layer 12c may be the smallest or finest in electronic device 1a.

[0041] Underfill 13 may be disposed between carrier 10 and electronic component 11. Underfill 13 may surround or cover electrical contact 11e. Underfill 13 may rise to surface 113 of electronic component 11. The rise height (or vertical coverage height, or extension length) of underfill 13 may vary. For example, the rise height of underfill 13 on the left side of electronic component 11 may be less than its rise height on the right side.

[0042] In some configurations, the underfill 13 may climb to a greater height on the surface 113 of the electronic component 11 relative to the carrier 10 than the surface 122 of the component 12. For example, the height to which the underfill 13 climbs along the surface 113 of the electronic component 11 may exceed the height of the surface 122 of the component 12 relative to the carrier 10. This arrangement can improve the reliability of the component 12 under thermal and mechanical loads.

[0043] Underfill 13 may be disposed between carrier 10 and component 12. Underfill 13 may surround or cover electrical contact 12e. Underfill 13 may rise to surface 123 of component 12. The rise height (or vertical coverage height, or extension length) of underfill 13 may vary. For example, the rise height of underfill 13 on the left side of component 12 may be greater than its rise height on the right side. In some configurations, surface 123 of component 12 may be completely covered by underfill 13. For example, both the left and right sides of component 12 may be completely covered by underfill 13.

[0044] The underfill 13 may be disposed between the surface 123 of the component 12 and the surface 113 of the electronic component 11. The underfill 13 may overlap the surface 123 of the component 12 and the surface 113 of the electronic component 11 in a direction generally perpendicular to the surface 123 and / or the surface 113.

[0045] In some configurations, the underfill 13 located between the surface 123 of component 12 and the surface 113 of electronic component 11 may have a non-planar top surface or topography. For example, the surface of the underfill 13 located between the surface 123 of component 12 and the surface 113 of electronic component 11 may not be flat or horizontal, but may have different heights, profiles or other complex geometric features.

[0046] In some configurations, the underfill 13 located between surface 123 of component 12 and surface 113 of electronic component 11 may have a local roughness greater than 1, for example, approximately 2, 3, 4, 5, 6, 7, 8, 9, 10, etc. The local roughness can be calculated by dividing the arithmetic mean roughness (Ra) by the mean spacing (Sm). The average roughness is the arithmetic mean of the absolute values ​​of the roughness amplitudes, and the mean spacing is the average spacing between the roughness peaks. In some configurations, the underfill 13 located between surface 123 of component 12 and surface 113 of electronic component 11 may have a stepped structure.

[0047] The underfiller 13 may be liquid at room temperature and may have a relatively low viscosity to facilitate flow and fill spaces or voids. In some configurations, the underfiller 13 may comprise an epoxy-based underfiller, a silicone-based underfiller, or a polyimide-based underfiller. The underfiller 13 may be selected based on functions such as reducing mechanical stress, improving thermal cycling performance, and protecting solder joints. For example, the underfiller 13 may be designed to have a low modulus, a low coefficient of thermal expansion (CTE), and generate lower stress during temperature cycling.

[0048] In some configurations, an underfill flow prevention structure may be disposed around the underfill 13. The underfill flow prevention structure may include multiple raised structures disposed around the mounting areas of the electronic components 11 and 12.

[0049] Encapsulation material 14 may be disposed on carrier 10. Encapsulation material 14 may cover electronic component 11, component 12, and underfill 13. Encapsulation material 14 may have a surface (e.g., top surface) 142. Encapsulation material 14 and underfill 13 may contact surface 122 of component 12. Surface 112 of electronic component 11 may be at least partially exposed from encapsulation material 14. Surface 112 of electronic component 11 and surface 142 of encapsulation material 14 may be substantially coplanar or aligned.

[0050] The encapsulation material 14 may define or have an opening 14h. The surface 122 of component 12 may be partially exposed to the opening 14h and partially covered by the encapsulation material 14. For example, the width 14hw of the opening 14h may be smaller than the width 12w of component 12. For example, the peripheral portion of the surface 122 of component 12 may be covered by the encapsulation material 14. The central portion of the surface 122 of component 12 may be exposed to the opening 14h. The conductive pad 12p of component 12 may be exposed to the opening 14h.

[0051] In some configurations, the opening 14h may include a sidewall 14hs. The sidewall 14hs may be located inside the edge or boundary of the component 12. The sidewall 14hs may be an inclined structure. The sidewall 14hs may be at an angle or orientation relative to the surface 122 of the component 12. For example, the taper angle of the opening 14h may be greater than 90 degrees. In some configurations, the sidewall 14hs may be a vertical surface, or a surface that is generally perpendicular to the surface 122 of the component 12. In some configurations, the surface 113 of the electronic component 11 and the sidewall 14hs generally tend to be perpendicular to the carrier 10.

[0052] In some configurations, the opening 14h can be formed using a laser-based process, and the laser technology can generate a thermal effect on the adjacent sidewalls, thereby affecting the material properties of these areas. For example, the sidewalls 14hs can become charred or burned due to laser exposure. The bottom filler 13 may not be exposed from the sidewalls 14hs.

[0053] In some configurations, the encapsulating material 14 may comprise an epoxy resin with a filler, an encapsulation (e.g., an epoxy encapsulation or other type of encapsulation), a polyimide, a phenolic compound or material, a material dispersed with silicone, or a combination thereof. In some configurations, the encapsulating material 14 may comprise a material different from the underfiller 13.

[0054] For example, the encapsulation material 14 may contain a first Young's modulus, and the underfill 13 may contain a second Young's modulus. The Young's modulus ratio (i.e., the ratio of the second Young's modulus to the first Young's modulus) may be greater than 1. For example, the flowability of the encapsulation material 14 may be less than that of the underfill 13.

[0055] Figure 1B This is a partial enlarged view of an electronic device according to some configurations of the present disclosure. For example, electronic device 1a may have, for example, Figure 1B The structure shown. In some configurations, Figure 1B The structure and Figure 1A The structure within the dashed box X is similar, except that the underfill 13 is exposed from the opening 14h. The underfill 13 is exposed from the sidewall 14hs of the opening 14h. For example, the underfill 13 and the encapsulation material 14 can together define the sidewall 14hs of the opening 14h.

[0056] In some configurations, the underfill 13 may rise onto the surface 122 of the component 12, and during the formation of the opening 14h, the underfill 13 on the surface 122 may be partially removed, thereby creating a cut or exposed surface of the underfill 13. In some configurations, the cut surface of the underfill 13 and the cut surface of the encapsulation material 14 may be substantially coplanar or aligned. In some configurations, the cut surfaces of the underfill 13 and the encapsulation material 14 may become charred or burned due to laser irradiation. In some configurations, the encapsulation material 14 may be spaced apart from the surface 122 of the component 12 by the underfill 13. For example, the encapsulation material 14 may not contact the surface 122 of the component 12. In some configurations, the encapsulation material 14 and the underfill 13 may overlap the surface 122 of the component 12 in a direction substantially perpendicular to the surface 122 of the component 12. In some configurations, the interface between the encapsulation material 14 and the underfill 13 may be higher than the component 12 relative to the carrier 10.

[0057] Figure 1C This is a partial enlarged view of an electronic device according to some configurations of the present disclosure. For example, electronic device 1a may have, for example, Figure 1C The structure shown. In some configurations, Figure 1C The structure and Figure 1A The structure within the dashed box X is similar, except that the width of the opening 14h is approximately equal to the width 12w of component 12. The sidewall 14hs of the opening 14h is approximately aligned with the surface 123 of component 12.

[0058] Figure 1D This is a partial enlarged view of an electronic device according to some configurations of the present disclosure. For example, electronic device 1a may have, for example, Figure 1D The structure shown. In some configurations, Figure 1DThe structure and Figure 1A The structure within the dashed box X is similar, except that the width 14hw of the opening 14h can be greater than the width 12w of the component 12. The surface 123 of the component 12 can be partially exposed to the opening 14h. For example, the upper part of the surface 123 of the component 12 can be exposed to the opening 14h.

[0059] In some configurations, the underfill 13 may have a recess 13h adjacent to the surface 123 of the component 12. The recess 13h may be a cavity, gap, or recessed region. The surface 123 of the component 12 may be partially exposed from the recess 13h. In some configurations, the lowest point of the recess 13h may be spaced apart from the surface 123 of the component 12. In some configurations, the lowest point of the recess 13h may be located between surfaces 121 and 122 of the component 12. In some configurations, the interface between the encapsulation material 14 and the underfill 13 may be lower than the surface 122 of the component 12 relative to the carrier 10.

[0060] In some configurations, the surface of the recessed portion 13h (e.g., the bottom surface or sidewall) may be uneven. In some configurations, the underfill 13 and component 12 can work together to protect the carrier 10, preventing damage or destruction during the formation of the opening 14h above component 12. For example, the parameters of the laser beam or the concentration and application method of the etchant can be precisely adjusted so that the area of ​​the carrier 10 covered only by the underfill 13 is adequately protected. For example, component 12 can protect the carrier 10 through its synergistic operation with the underfill 13.

[0061] Figure 2A This is a cross-sectional view of an electronic device 2a according to some configurations of the present disclosure. Electronic device 2a and... Figure 1A The electronic device 2a is similar to the electronic device 1a, except that the electronic device 2a further includes a package 20 and a package material 21.

[0062] The encapsulation 20 may be placed on top of the component 12. The encapsulation 20 may be placed within the opening 14h. The encapsulation 20 may be surrounded by the encapsulation material 14. The encapsulation 20 and the component 12 may substantially overlap in a direction substantially perpendicular to the surface 122 of the component 12.

[0063] Package 20 can be electrically connected to component 12, and the electrical connection can be achieved by solder joint, copper-to-copper joint, wire joint, or hybrid joint. For example, package 20 can be electrically connected to component 12 via electrical contact 20e.

[0064] Package 20 may include a memory package, such as a Dynamic Random Access Memory (DRAM) package, a Static Random Access Memory (SRAM) package, a Read-Only Memory ROM package, a Flash memory package, a Magnetoresistive RAM (MRAM) package, etc. However, the innovative concept is not limited to this. For example, package 20 may also be other types of packages or include other types of packages, such as a transceiver package, a processing package, a network package, a voltage-regulated package (providing stable voltage), etc.

[0065] In some configurations, package 20 may include carrier 20c, component 20a, and encapsulation material 20m. Carrier 20c may be configured to provide structural support for component 20a and encapsulation material 20m. Component 20a may include one or more memory dies. For example, Figure 2A Only the outermost memory die may be drawn, providing a focused view of its structure and layout, without depicting the underlying or adjacent dies. In some configurations, component 20a may include other types of dies. Encapsulation material 20m may be placed on the carrier 20c and cover component 20a.

[0066] The encapsulation material 20m may contain the material described above for encapsulation material 14. In some configurations, the encapsulation material 20m may contain a different material than encapsulation material 14. In some configurations, the encapsulation material 20m and encapsulation material 14 may contain the same material, and there is a distinguishable interface between them.

[0067] Encapsulation material 21 can fill the gaps or spaces within the opening 14h after the package 20 is placed within it. Encapsulation material 21 can form a sealed space between the package 20 and encapsulation material 14. Encapsulation material 21 can cover the package 20. The central portion of the surface 122 of component 12 can be covered by encapsulation material 21. The peripheral portion of the surface 122 of component 12 can be covered by underfill 13 and / or encapsulation material 14. This filling process helps ensure a tight fit, providing structural support and protection for the package 20 while preventing the ingress of contaminants such as dust or moisture.

[0068] Encapsulation material 21 may comprise the materials listed above for encapsulation material 14. In some configurations, encapsulation material 21 may comprise a different material than encapsulation material 14. In some configurations, encapsulation material 21 and encapsulation material 14 may comprise the same material, with a distinguishable interface between them.

[0069] Encapsulation material 21 may cover, surround, or encapsulate encapsulation material 20m. In some configurations, encapsulation material 21 and encapsulation material 20m may define or include an interface or boundary i1. For example, interface i1 may exist at the junction of encapsulation material 21 and encapsulation material 20m. For example, interface i1 may be a gapless interface.

[0070] Encapsulation material 14 may cover, surround, or encapsulate encapsulation material 21. In some configurations, encapsulation materials 14 and 21 may define or include an interface or boundary i2. For example, interface i2 may exist at the junction of encapsulation material 14 and encapsulation material 21. For example, interface i2 may be a gapless interface.

[0071] The encapsulation material 21 may have a surface (e.g., a top surface) 212. The surface 112 of the electronic component 11, the surface 142 of the encapsulation material 14, and the surface 212 of the encapsulation material 21 may be substantially coplanar or aligned.

[0072] Figure 2B This is a partial enlarged view of an electronic device according to some configurations of the present disclosure. For example, electronic device 2a may have, for example, Figure 2B The structure shown. In some configurations, Figure 2B The structure and Figure 2A The structure within the dashed box 2X is similar, except that the underfill 13 contacts the encapsulation material 21. For example, the underfill 13 and the encapsulation material 14 may define a coplanar surface that contacts the encapsulation material 21. In some configurations, the interface between the encapsulation material 21 and the underfill 13 may be located within the boundary of component 12.

[0073] like Figure 2C The image shown is a partially enlarged view of an electronic device according to some configurations of the present disclosure. For example, electronic device 2a may have, as shown in the image... Figure 2C The structure shown. In some configurations, Figure 2C The structure and Figure 2A The structure within the dashed box 2X is similar, except that the width of the opening 14h can be approximately equal to the width 12w of the component 12. For example, the underfill 13 and the encapsulation material 14 can define a coplanar surface that is substantially aligned with the surface 123 of the component 12.

[0074] Figure 2D This is a partial enlarged view of an electronic device according to some configurations of the present disclosure. For example, electronic device 2a may have, for example, Figure 2D The structure shown. In some configurations, Figure 2D The structure and Figure 2A The structures within the dashed box 2X are similar, except that the width 14hw of the opening 14h can be greater than the width 12w of component 12.

[0075] The surface 123 of component 12 may be partially covered by encapsulating material 21 and partially covered by underfill 13. For example, the upper surface of surface 123 of component 12 may be covered by encapsulating material 21, while the lower surface of surface 123 may be covered by underfill 13. In some configurations, the interface between encapsulating material 21 and underfill 13 may be located outside the boundary of component 12.

[0076] Figure 2E A cross-sectional view of an electronic device 2e according to some configurations of this disclosure. Electronic device 2e and... Figure 2A Similar to electronic device 2a, except that in electronic device 2e, encapsulation material 20m may have a surface (e.g., top surface) 20m2. The surface 20m2 of encapsulation material 20m may be at least partially exposed from encapsulation material 21. The surface 112 of electronic component 11, the surface 142 of encapsulation material 14, the surface 212 of encapsulation material 21, and the surface 20m2 of encapsulation material 20m may be substantially coplanar or aligned.

[0077] Figure 2F This is a cross-sectional view of an electronic device 2f according to some configurations of this disclosure. Electronic device 2f and... Figure 2A Similar to electronic device 2a, the difference is that electronic device 2f is also connected to heat dissipation component 22 via an adhesive layer 22g (e.g., thermal gel). Heat dissipation component 22 may contain heat conduction units and may have high thermal conductivity. For example, heat dissipation component 22 may contain copper (Cu), aluminum (Al), graphite, ceramic, etc. Heat dissipation component 22 may include a block, pipe, heat sink, fin, or other shape.

[0078] In some configurations, the width 22w of the heat dissipation component 22 may be smaller than the width 14w of the encapsulation material 14. For example, a portion of the adhesive layer 22g may not be covered by the heat dissipation component 22.

[0079] Figure 2G This is a cross-sectional view of an electronic device 2g according to some configurations of this disclosure. The electronic device 2g and... Figure 2A The electronic device 2a is similar to that in the other device, except that the electronic device 2g further includes a shielding layer 23.

[0080] The shielding layer 23 may comprise a generally conformal layer or conformal shield. For example, the shielding layer 23 may be conformal to the encapsulation material 14. The shielding layer 23 may be formed in the appropriate locations by an electroplating process. The shielding layer 23 may be disposed on the surface 112 of the electronic component 11, the surface 142 of the encapsulation material 14, the surface 212 of the encapsulation material 21, and the side surface of the carrier 10.

[0081] The shielding layer 23 can be electrically connected to the grounding component of the carrier 10. In some configurations, the shielding layer 23 may comprise a conductive film made of materials such as copper, aluminum, or conductive polymers to achieve effective conductivity. In addition, the shielding layer 23 may also be designed to provide electrostatic discharge protection, thereby protecting sensitive components inside the electronic device 2g from damage that may be caused by sudden power surges or static electricity.

[0082] Figure 3A , 3B Figures 1A, 3C, 3D, 3E, 3F, 3G, 3H, 3I, and 3J are drawn in cross-section at one or more stages of a method of manufacturing an electronic device according to some configurations of the present disclosure. For a better understanding of the various aspects of the present disclosure, at least some of these figures have been simplified. In some configurations, electronic device 1a can be... Figure 3A , 3B The manufacturing process is illustrated by steps 3C, 3D, 3E, 3F, 3G, 3H, 3I, and 3J.

[0083] refer to Figure 3A A temporary carrier 30 may be provided (e.g., manufactured or obtained). The temporary carrier 30 may be a glass carrier, a metal carrier, a ceramic carrier, or other suitable carrier. The temporary carrier 30 may include a panel with a size generally 300 square millimeters, 500 square millimeters, 600 square millimeters, or larger. For example, electronic device 1a may be implemented using a panel-level packaging (PLP) process. In panel-level packaging, multiple semiconductor packages are manufactured simultaneously using a panel. Compared to conventional wafer-level packaging (WLP), using a panel allows for higher throughput and better material utilization due to the increased substrate size. The rectangular substrate is typically formed from organic multilayer materials or a glass-based substrate and may have pre-defined kerfs (saw marks) in the row and column directions for monomerization after packaging and other back-end processes.

[0084] The carrier 10 may be formed on the temporary carrier 30. The carrier 10 may be attached to the temporary carrier 30 by an adhesive layer 10g. The adhesive layer 10g may include a die attach film (DAF), adhesive, bonding layer, underfill, or other suitable material.

[0085] In some configurations, due to the rectangular geometry of the panel, the electroplating process during redistribution layer formation can cause charge accumulation at the corners, resulting in unique microstructural effects on the wiring near the panel edges that are not present on circular chips. To compensate for the non-uniformity of electroplating at the panel corners, dummy structures may be densely distributed in these areas. Furthermore, the panel's cut streets are typically aligned parallel or perpendicular to the panel edges, which is structurally distinct from the cut paths on the chip.

[0086] refer to Figure 3B Electronic components 11 and 12 can be placed on temporary carrier 30.

[0087] In some configurations, more than two electronic devices can be batched on a temporary carrier 30 and undergo similar or identical processes in the manufacturing method. For example, electronic components 11 can be arranged in an N×M array. For example, components 12 can be arranged in an N×M array. For example, the sidewalls of electronic components 11 can be aligned with the sidewalls of components 12 to form a symmetrical array. For example, the relative displacement between the sidewalls of electronic components 11 and the sidewalls of components 12 can be substantially equal.

[0088] In some configurations, compared to wafer-level packaging (WLP), panel-level packaging (PLP) is based on a rectangular panel substrate on which multiple components are arranged in an N×M array, with each row and column containing the same number of components. This uniform grid arrangement is a characteristic of PLP, unlike wafer-level packaging, where die density is typically higher in the chip center and lower in the peripheral areas. For example, a wafer-level package includes a central area with a relatively high density of dies and a peripheral area with a relatively low density of dies. In PLP, the outermost rows and columns can share a single component located at the panel corner, a layout not commonly seen on circular chips.

[0089] Underfill 13 can be placed on temporary carrier 30. Underfill 13 can connect electronic components 11 and 12 to temporary carrier 30. For example, during the application of underfill material 13, electronic components 11 and 12 can be positioned at specific locations on a support structure within the dispensing system. In some configurations, images of the underfill 13 can be captured in situ, i.e., directly during the dispensing process. This real-time imaging allows for precise monitoring of underfill application. Using the captured images, the chamfer width of the underfill can be accurately measured. Based on these measurements, multiple threshold levels for chamfer width can be established to ensure quality control and consistency in the dispensing process.

[0090] In some configurations, the underfill 13 can be formed on the surface using anisotropic deposition techniques. Unlike isotropic deposition, which deposits material uniformly in all directions, anisotropic deposition selectively enhances deposition in target areas to form non-uniform films or structures.

[0091] refer to Figure 3C The encapsulation material 14 can be placed on the carrier 10 to cover the electronic components 11, 12, and the underfill 13. In some configurations, the encapsulation material 14 can be formed by molding techniques, such as transfer molding, injection molding, or compression molding.

[0092] refer to Figure 3D The temporary carrier 30 and the adhesive layer 10g can be removed, and the carrier 10 is exposed.

[0093] refer to Figure 3E Electrical contacts 10e can be formed on the carrier 10.

[0094] refer to Figure 3F ,Depend on Figure 3E The structure obtained through the operation can be placed on a temporary carrier 31. Planarization or grinding operations can be performed to remove a portion of the encapsulation material 14, thereby exposing the surface 112 of the electronic component 11. Planarization or grinding operations may include grinding processes using grinding wheels or grinders, chemical mechanical planarization (CMP) processes, etching processes, or laser direct ablation (LDA) processes.

[0095] refer to Figure 3G ,Depend on Figure 3F The resulting structure can be mounted on cutting tape 32. Individual unitization can be performed. Electronic components can be individualized or separated into multiple independent units or segments during the individual unitization process. In some configurations, individual unitization can be performed using a saw blade or laser cutting tool.

[0096] refer to Figure 3H ,pass Figure 3H The units obtained through the operation can be placed or sorted on plate 33. For example, plate 33 may include multiple holes or openings, and each unit can be placed in a corresponding opening.

[0097] refer to Figure 3I The opening 14h can be formed by laser ablation, laser drilling, laser cutting, or etching. Component 12 can be configured to protect the carrier 10 from damage or destruction during the formation of the opening 14h on component 12.

[0098] refer to Figure 3JBefore product packaging and shipping, a cover 34 can be placed over the plate 33 to facilitate a thorough cleaning process. This cleaning process may include multiple steps, such as washing the plate with water to remove any contaminants or residues, followed by baking in an oven to ensure complete drying and eliminate any residual moisture. In some configurations, the product may be transported to different production lines for placement of the package 20. Compared to embodiments without component 12, the presence of component 12 enhances the overall structural strength and durability of the product.

[0099] Figure 4A , 4B Figures 4C, 4D, and 4E are cross-sections of one or more stages of a method for manufacturing an electronic device according to some configurations of this disclosure. For the purpose of better understanding various aspects of this disclosure, at least some figures have been simplified. In some configurations, electronic device 2a can be manufactured by... Figure 4A , 4B Manufactured according to the steps shown in 4C, 4D and 4E.

[0100] refer to Figure 4A ,exist Figure 3E After the operation, by Figure 3E The structure obtained through the operation can be placed on the temporary carrier 41. The opening 14h can be formed by laser direct ablation, laser drilling, laser cutting, or etching. The component 12 is configured to protect the carrier 10 from damage or destruction during the formation of the opening 14h above the component 12.

[0101] refer to Figure 4B The package 20 can be placed on top of the component 12 and located within the opening 14h. In some configurations, the carrier 10 can be electrically tested before the package 20 is installed.

[0102] Traditionally, packages (such as memory packages) are molded together with the integrated circuit die in the package material. The package is at risk of being damaged in subsequent process steps. This traditional approach presents a significant challenge because any damage after the molding process cannot be repaired by removing or replacing the package. Therefore, this traditional approach typically leads to higher manufacturing costs and lower production yields, as defective packages result in increased scrap and rework.

[0103] According to one arrangement of this disclosure, the present invention employs placing component 12 on a designated redistribution layer area for die placement, followed by encapsulation and forming openings to expose the pads of component 12. This allows for electrical testing of the redistribution layer prior to die mounting, thereby facilitating early defect detection, reducing costs, and improving yield.

[0104] In some configurations, electrical testing may be performed after the package 20 is placed within the opening for 14 hours. If a defect is found in the package 20 or the carrier 10 during this testing, methods include separating and removing the package 20 from the opening for replacement or further inspection.

[0105] In some configurations, the package 20 or carrier 10 is controlled to operate in a repair mode, where test signals are redirected to avoid damaged pathways and transmitted via alternative paths.

[0106] refer to Figure 4C After the package 20 is placed within the opening 14h, the encapsulation material 21 can fill the gaps or spaces within the opening 14h. In some configurations, the encapsulation material 21 can be formed by a molding process, such as transfer molding, injection molding, or compression molding.

[0107] refer to Figure 4D Planarization or grinding operations can be performed to remove portions of the encapsulation materials 14 and 21, exposing the surface 112 of the electronic component 11.

[0108] refer to Figure 4E ,Depend on Figure 4D The resulting structure can be mounted on cutting tape 42. Individualization operations can be performed. In individualization operations, electronic device components can be individualized or separated into multiple independent units. In some configurations, individualization operations can be performed using a saw blade or laser cutting tool.

[0109] Spatial descriptions, such as "above," "below," "upper," "left," "right," "lower," "top," "bottom," "vertical," "horizontal," "side," "higher," "lower," "upper part," "above," "below," etc., unless otherwise specified, refer to the directions shown in the accompanying drawings. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and the described structures can be arranged spatially in any direction or manner in actual implementation, as long as such arrangement does not depart from the advantages of the embodiments disclosed herein.

[0110] In this document, the terms "approximately," "substantially," "essentially," and "about" are used to describe and explain minor variations. When used in conjunction with an event or situation, these terms can refer to either the event or situation occurring completely or approximately. For example, when used with a numerical value, these terms can refer to a range of variation less than or equal to ±10% of that value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For instance, if the first value is within the range of variation of the second value of less than or equal to ±10%, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%, then the first value can be considered "substantially" the same as or equal to the second value. For example, "generally" vertical can refer to an angle variation of less than or equal to ±10° relative to 90°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

[0111] Two surfaces can be considered coplanar or substantially coplanar if the displacement between them is no greater than 5µm, 2µm, 1µm, or 0.5µm. If the displacement between the highest and lowest points on a surface is no greater than 5µm, 2µm, 1µm, or 0.5µm, then the surface can be considered substantially flat.

[0112] In this document, the singular terms “a” and “the” may contain plural references unless the context clearly specifies otherwise.

[0113] In this article, the terms "conductive," "electrical conductivity," and "conductivity" refer to the ability to conduct electric current. Conductive materials generally indicate materials that offer little or no obstruction to the flow of electric current. One unit of measurement for electrical conductivity is Siemens per meter (S / m). Typically, conductive materials are defined as having a conductivity greater than approximately 10. 4 Materials with a S / m ratio, for example, at least 10 5 S / m or at least 10 6 S / m. The electrical conductivity of a material can vary with temperature. Unless otherwise stated, the electrical conductivity of a material is measured at room temperature.

[0114] In addition, quantities, ratios, and other values ​​are sometimes presented in range form. It should be understood that this range form is for convenience and simplicity only, and should be interpreted flexibly to include not only the values ​​explicitly defined as range limits, but also all individual values ​​or subranges falling within that range, as if each value and subrange were explicitly specified.

[0115] Although this disclosure has been described and illustrated with reference to specific embodiments, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various modifications and alternative equivalents can be made without departing from the true spirit and scope of this disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to manufacturing processes and tolerances, artistic drawings in this disclosure may differ from actual devices. Other embodiments not specifically illustrated may also exist in this disclosure. The specification and drawings should be considered illustrative rather than limiting. Modifications may be made to specific situations, materials, compositions, methods, or processes to suit the objectives, spirit, and scope of this disclosure. All such modifications are intended to be included within the scope of the appended claims. While the methods disclosed herein have been described in conjunction with specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of this disclosure.

Claims

1. An electronic device comprising: Rewire layer; Components, which are disposed on the redistribution layer; An underfill material is disposed between the redistribution layer and the component; as well as An encapsulation material that covers the component, wherein the encapsulation material or the underfill defines a sidewall adjacent to the component and is substantially perpendicular to the surface of the component.

2. The electronic device of claim 1, wherein the encapsulation material or the underfill defines an opening in a conductive pad having the surface and exposing the component.

3. The electronic device of claim 2, wherein the opening is configured to receive a memory package.

4. The electronic device of claim 2, wherein the bottom filler is exposed from the opening.

5. The electronic device according to claim 1, wherein, The bottom filler defines a recessed portion of the sidewall adjacent to the component.

6. An electronic device comprising: Rewire layer; The chip is disposed on the redistribution layer; A memory package disposed on the redistribution layer and adjacent to the chip, wherein the memory package includes a first encapsulation material; as well as A second encapsulation material covers the memory package, wherein the first encapsulation material and the second encapsulation material have a first interface.

7. The electronic device according to claim 6, further comprising: A third packaging material covers the chip and the second packaging material, wherein the third packaging material and the second packaging material have a second interface.

8. The electronic device of claim 7, wherein the top surface of the third encapsulation material is substantially aligned with the top surface of the first encapsulation material.

9. The electronic device according to claim 6, further comprising: An intermediary layer connects the memory package and the redistribution layer.

10. The electronic device of claim 9, wherein the central portion of the intermediate layer is covered by the second encapsulation material.

11. The electronic device of claim 10, further comprising: The bottom filler connects the intermediary layer to the redistribution layer.

12. The electronic device of claim 11, wherein the peripheral portion of the intermediate layer is covered by the underfiller.

13. An electronic device comprising: Rewire layer; An intermediary layer is placed on the redistribution layer; A bottom filler is disposed between the redistribution layer and the interposer layer; as well as A first encapsulation material covers the underfill, wherein the first encapsulation material or the underfill defines an opening on the interlayer to accommodate the memory package.

14. The electronic device of claim 13, wherein the interposer is configured to protect the redistribution layer from damage during the formation of the opening.

15. The electronic device of claim 13, wherein the interface between the first encapsulation material and the underfill is higher than the interposer relative to the redistribution layer.

16. The electronic device according to claim 13, wherein, Relative to the redistribution layer, the interface between the first encapsulation material and the underfiller is below the surface of the interposer layer that is away from the redistribution layer.

17. The electronic device of claim 13, wherein the interposer layer comprises a circuit layer disposed on a surface of the interposer layer toward the redistribution layer.

18. The electronic device of claim 17, wherein the line spacing of the circuit layer is smaller than the line spacing of the interposer layer.

19. The electronic device of claim 18, wherein the line spacing of the intermediate layer is smaller than the line spacing of the redistribution layer.

20. The electronic device of claim 13, further comprising: A second encapsulating material is placed in the opening and in contact with the bottom filler.

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