Apparatus and method for deterministic interleaving of data from multiple hosts connected to a single port

Abstract

An apparatus and related method are disclosed. The apparatus includes: a port; a memory circuitry; and a processing circuitry coupled to the port and the memory circuitry. The processing circuitry receives a plurality of commands through the port, said plurality of commands coming from at least two hosts using an inserter, and said plurality of commands include a corresponding memory address and a corresponding port identifier (ID). The processing circuitry divides each of the received commands into a plurality of segments, each segment having a predetermined transfer size. The processing circuitry also transfers each segment of each command to a corresponding data structure instance corresponding to the port ID of the corresponding received command, and performs the data transfer of each of the plurality of segments by accessing the memory circuitry at each corresponding memory address associated with each segment.

Description

Technical Field

[0001] This disclosure relates to apparatus and methods for managing commands from multiple hosts via a single port of the apparatus. Summary of the Invention

[0002] According to this disclosure, apparatus and methods are provided for interleaving and processing commands for accessing a memory circuitry from multiple hosts via a single port of a device (e.g., a storage device). The device (e.g., a solid-state drive (SSD) device) includes a memory circuitry that may include memory blocks having pages or superpages of memory. The apparatus and methods disclosed herein may use the device's firmware and processing circuitry to perform the interleaving and processing of commands received from multiple hosts. The interleaving of received commands provides command workload balancing, which improves the link efficiency of the bus coupling the host to a single port of the device. An interposer may be used between the port of the device and the host to provide support from at least two ports located on the host side of the interposer to a single port located on the device side of the interposer. Additionally, the interleaving and processing of commands performed by the device disclosed herein reduces the memory and processing overhead of the interposer, minimizing command data path and associated latency within the interposer. The apparatus and methods disclosed herein balance access to the device's memory circuitry by each host. Commands may include any one or more data transfer requests (e.g., read or write requests), such as direct memory access (DMA) data transfers.

[0003] A device (e.g., an SSD device) may include a processing circuitry that receives multiple commands through a single port of the device. In some embodiments, each of the multiple commands originates from one of at least two hosts using an inserter. The inserter is used to communicatively couple multiple hosts to a single port of the device. In some embodiments, each of the multiple commands includes a corresponding memory address and a corresponding port identifier (ID). The port ID included within each corresponding command corresponds to one of the at least two hosts from which the corresponding command originated. Once the processing circuitry receives the multiple commands, it then segments each of the received commands into corresponding segments, each segment having a predetermined transmission size. In some embodiments, the predetermined transmission size of each segment is not less than the maximum packet size (MPS) or minimum transmission size supported by the device. The processing circuitry then transmits each of its multiple segments to a corresponding data structure instance corresponding to the port ID of the corresponding received command. In some embodiments, a corresponding data structure instance exists for each corresponding host communicatively coupled to the device. Each data structure instance is configured to temporarily store a data transfer request (e.g., a direct memory access (DMA) request), and each data transfer request corresponds to one of a plurality of segments. The processing circuitry also performs the data transfer for each of the plurality of segments via memory access devices with corresponding memory addresses associated with each corresponding segment. The processing circuitry will perform the data transfer for the segment corresponding to the data transfer request in a given data structure instance at a given time.

[0004] In some embodiments, the apparatus (e.g., a storage device) is provided with a memory circuitry and a processing circuitry communicatively coupled to each other. In some embodiments, the processing circuitry includes: (a) a processor for executing instructions to provide the apparatus with general processing capabilities; and (b) a memory controller for processing processor-independent commands for accessing the memory circuitry. In some embodiments, the processing circuitry receives commands from a plurality of hosts to be processed by the memory controller, each command including a destination memory address corresponding to a memory address within the memory circuitry. In some embodiments, the command is a write command that includes host data to be stored at the destination memory address within the memory circuitry. Attached Figure Description

[0005] The following description includes a discussion of the accompanying drawings, which illustrate implementations of embodiments of the present disclosure given as examples. The drawings should be understood as examples, not as limitations. As used herein, references to one or more “embodiments” should be understood as describing specific features, structures, and / or characteristics included in at least one implementation. Therefore, phrases such as “in one embodiment” or “in an alternative embodiment” appearing herein describe various embodiments and implementations and do not necessarily all refer to the same embodiment. However, they are not necessarily mutually exclusive.

[0006] Figure 1 An illustrative diagram of a system comprising two hosts and a device according to some embodiments of the present disclosure is shown, the device having a processing circuitry system, an I / O circuitry system, and a memory circuitry system; Figure 2 This illustrates exemplary commands processed from a host according to some embodiments of the present disclosure. Figure 1 An illustrative diagram of the processing circuit system; Figure 3 A flowchart illustrating illustrative steps of a process for performing data transfer on an apparatus according to some embodiments of the present disclosure; Figure 4A and 4B Flowcharts illustrating illustrative steps of sub-processes for executing read and write commands received from a respective host, according to some embodiments of this disclosure; and Figure 5 A flowchart illustrating the illustrative steps of a sub-process for performing data transfer on an apparatus by interleaving data transfers of commands from each of the respective hosts, according to some embodiments of the present disclosure. Detailed Implementation

[0007] According to this disclosure, apparatus and methods are provided for interleaving and processing commands from multiple hosts via a single port of a device (e.g., a storage device). The device (e.g., an SSD device) may include a processing circuitry that receives multiple commands via a single port of the device. In some embodiments, each of the multiple commands originates from one of at least two hosts using an inserter. The inserter is used to communicatively couple the multiple hosts to a single port of the device. In some embodiments, the inserter includes multiple submission queues, each corresponding to a respective host. In some embodiments, each of the multiple commands includes a corresponding memory address and a corresponding port identifier (ID). The memory address included in each corresponding command corresponds to the memory address of the device's memory circuitry accessed (e.g., read from and written to) by the processing circuitry. The port ID included within each corresponding command corresponds to one of the at least two hosts from which the corresponding command originates.

[0008] Once the processing circuitry receives the plurality of commands, it then segments each of the received commands into a plurality of corresponding segments, each segment having a predetermined transfer size. In some embodiments, the predetermined transfer size of each segment is not less than the maximum packet size (MPS) or minimum transfer size supported by the device. In some embodiments, the MPS and minimum transfer size are defined by a bus or interface used to connect the device to the plurality of hosts. The processing circuitry then transfers each of the respective plurality of segments to a corresponding data structure instance corresponding to the port ID of the corresponding received command. In some embodiments, each corresponding data structure instance is a mailbox (e.g., a direct memory access (DMA) mailbox). In some embodiments, a corresponding data structure instance exists for each corresponding host coupled to the device in a communicative manner. Each data structure instance is configured to temporarily store a data transfer request (e.g., a DMA request), each data transfer request corresponding to one of the plurality of segments. In some embodiments, each data transfer request stored in the corresponding data structure instance originates from a corresponding host among the plurality of hosts coupled to the single port. The processing circuitry also performs the data transfer of each of the plurality of segments by accessing the device's memory by each corresponding memory address associated with each corresponding segment.

[0009] The processing circuitry will execute data transfer of a segment corresponding to a data transfer request in a corresponding data structure instance at a given time. In some embodiments, the processing circuitry executes data transfer of a first subset of segments of a first command by accessing the memory circuitry at each corresponding memory address associated with each corresponding segment of a first subset of segments of a first command, and subsequently executes data transfer of a second subset of segments of a second command by accessing the memory circuitry at each corresponding memory address associated with each corresponding segment of a second subset of segments of a second command. In some embodiments, each subset of the first and second subsets of segments includes at least one segment from its corresponding command. Additionally, each of the first and second commands may include a different port ID, indicating that the first and second commands originate from different hosts. This process enables interleaving of data transfer of segments of commands from different hosts, thus improving fairness for each host when accessing the device's memory and improving the link efficiency of the bus that couples the inserter to a single port of the device.

[0010] For the purposes of brevity and clarity, the features of the disclosure described herein are situated within the context of a device having a processing circuitry and a memory circuitry (e.g., an SSD device). However, the principles of this disclosure can be applied to any other suitable context in which commands for accessing the memory circuitry from multiple hosts via a single port of the device are interleaved and processed. The device may include a processing circuitry and a memory circuitry, which are communicatively coupled to each other via a network bus or interface. In some embodiments, the processing circuitry receives commands from multiple hosts via an inserter. In some embodiments, the inserter allows multiple hosts to be communicatively coupled to a single port of the device. In some embodiments, commands are sent to the device from any of the hosts via a network bus or interface.

[0011] In particular, this disclosure provides apparatus and methods that provide improved network link efficiency between the device and the plurality of hosts by interleaving and processing commands for accessing the device's memory circuitry. This improves the overall performance and bandwidth of the device while the processing circuitry executes instructions and processes commands for accessing the memory circuitry.

[0012] In some embodiments, the processing circuitry includes a processor and a memory controller. The memory controller may include a data transfer engine and corresponding data structure instances corresponding to the respective host from which the command originates, each data structure instance (e.g., a DMA mailbox) configured to temporarily store the data transfer request until the data transfer engine transmits the data transfer request to the memory circuitry. In some embodiments, the processor of the processing circuitry may be a highly parallelized processor capable of rapidly processing high-bandwidth incoming instructions (e.g., by starting simultaneous instruction processing before previously received instructions complete). For the memory controller to process commands from the host, the processor will execute instructions concurrently and independently.

[0013] The memory circuitry of the device may be referred to hereinafter as the memory of the device. In some embodiments, the memory of the device disclosed herein may comprise any of the following memory densities: single-level primitive (SLC), multi-level primitive (MLC), three-level primitive (TLC), four-level primitive (QLC), five-level primitive (PLC), and any suitable memory density greater than five bits per memory primitive.

[0014] In some embodiments, the apparatus and methods disclosed herein may refer to a storage device (e.g., an SSD device) having a single port, which is communicatively coupled to multiple hosts (e.g., host devices) via a network bus or interface. In some embodiments, a host is coupled to the single port of the device via an inserter, which may include: multiple host-side ports for receiving data from and transmitting data to each host; and a single device-side port for transmitting data to and receiving data from the device.

[0015] SSDs are data storage devices that use integrated circuit components as memory to permanently store data. SSDs have no moving mechanical parts, and this characteristic distinguishes them from traditional electromechanical disks (such as hard disk drives (HDDs) or floppy disks), which contain spinning platters and removable read / write heads. Compared to HDDs, SSDs are generally more resistant to physical shocks, operate quietly, and have lower access times and less latency.

[0016] Many types of SSDs use NAND-based flash memory that retains data without power and include a type of non-volatile storage technology. The Quality of Service (QoS) of an SSD is related to predictable low latency and consistent high input / output operations per second (IOPS) while serving read / write input / output (I / O) workloads. This means that latency or I / O command completion times need to be within specified ranges without unexpected outliers. Throughput or I / O rates may also need to be tightly tuned without causing sudden drops in performance levels.

[0017] By reference Figure 1-5 The subject matter of this disclosure can be better understood.

[0018] Figure 1The illustrated diagram shows a system 100 according to some embodiments of the present disclosure. The system 100 includes two hosts (e.g., a first host 108 and a second host 112) and a device 102 having a processing circuitry system 104, an I / O circuitry system 105, and a memory circuitry system 106. In some embodiments, the device 102 may be a storage device, such as a solid-state storage device (e.g., an SSD device). In some embodiments, the processing circuitry system 104 may include a processor or any suitable processing unit. In some embodiments, the memory circuitry system 106 may include non-volatile memory. It will be understood that embodiments of the present disclosure are not limited to SSDs. For example, in some embodiments, in addition to an SSD, the device 102 may also include a hard disk drive (HDD) device, or instead of an SSD, the device 102 may include a hard disk drive (HDD) device. In some embodiments, the I / O circuitry system 105 includes temporary memory (e.g., a cache or any suitable volatile memory) to store commands received via port 107 (e.g., a first command 110 from the first host 108 and a second command 113 from the second host 112).

[0019] Processing circuitry 104 is configured to receive commands (e.g., first command 110 and second command 113) via port 107 of device 102. In some embodiments, each of the plurality of commands (e.g., first command 110 and second command 113) originates from one of at least two hosts (e.g., first host 108 and second host 112) using inserter 109. Inserter 109 communicatively couples the plurality of hosts (e.g., first host 108 and second host 112) to port 107 of device 102. In some embodiments, each command (e.g., first command 110 and second command 113) includes a corresponding memory address and a corresponding port ID. The memory address included in each corresponding command corresponds to the memory address of the memory circuitry 106 of device 102 accessed (e.g., read and write) by processing circuitry 104. The port ID included in each corresponding command corresponds to one of the at least two hosts (e.g., first host 108 and second host 112) from which the corresponding command (e.g., first command 110 and second command 113) originates. Once the processing circuitry 104 receives the plurality of commands (e.g., first command 110 and second command 113), the processing circuitry 104 then divides each of the received commands into a plurality of corresponding segments, each segment having a predetermined transmission size. In some embodiments, the predetermined transmission size of each segment is not less than the maximum packet size (MPS) or minimum transmission size supported by the device 102. In some embodiments, the MPS and minimum transmission size are defined by a bus 111 for connecting the device 102 to the plurality of hosts (e.g., first host 108 and second host 112). The processing circuitry 104 then transmits each of the respective plurality of segments to a corresponding data structure instance corresponding to the port ID of the corresponding received command (e.g., first command 110 and second command 113). In some embodiments, each corresponding data structure instance is a mailbox (e.g., a direct memory access (DMA) mailbox). In some embodiments, a corresponding data structure instance exists for each corresponding host (e.g., first host 108 and second host 112) communicatively coupled to the device 102. Each data structure instance is configured to temporarily store a data transfer request (e.g., a DMA request), and each data transfer request corresponds to one of a plurality of segments. In some embodiments, each data transfer request stored in a respective data structure instance originates from a respective host among the plurality of hosts coupled to port 107. The processing circuitry 104 also performs data transfer for each of the plurality of segments via memory (e.g., memory circuitry 106) of each respective memory address access device 102 associated with each respective segment.

[0020] Processing circuitry 104 will execute data transfer of a segment corresponding to a data transfer request in a corresponding data structure instance at a given time. In some embodiments, processing circuitry 104 executes data transfer of a first subset of segments of the first command 110 by accessing memory circuitry 106 at each corresponding memory address associated with each corresponding segment of a first subset of segments of the first command 110, and subsequently executes data transfer of a second subset of segments of the second command 113 by accessing memory circuitry 106 at each corresponding memory address associated with each corresponding segment of a second subset of segments of the second command 113. In some embodiments, each subset of the first and second subsets of segments includes at least one segment from its corresponding command. Additionally, each command in the first command 110 and the second command 113 may include a different port ID indicating that the first command 110 and the second command 113 originate from different hosts (e.g., first host 108 and second host 112). This process enables the interleaving of data transfer segments of commands (e.g., first command 110 and second command 113) from different hosts (e.g., first host 108 and second host 112), thus improving fairness for each host when accessing the circuit system memory 106 of device 102 and improving the link efficiency of bus 111 that couples inserter 109 to port 107 of device 102.

[0021] For the purposes of brevity and clarity, the features of the disclosure described herein are situated within the context of a device having a processing circuitry and a memory circuitry (e.g., an SSD device). However, the principles of this disclosure can be applied to any other suitable context in which commands for accessing the memory circuitry from multiple hosts via a single port of the device are interleaved and processed. The device may include a processing circuitry and a memory circuitry, which are communicatively coupled to each other via a network bus or interface. In some embodiments, the processing circuitry receives commands from multiple hosts via an inserter. In some embodiments, the inserter allows multiple hosts to be communicatively coupled to a single port of the device. In some embodiments, commands are sent to the device from any of the hosts via a network bus or interface.

[0022] In some embodiments, inserter 109 includes a plurality of submission queues, each corresponding to a corresponding host. Each corresponding submission queue of inserter 109 will store commands from the corresponding host. In some embodiments, processing circuitry 104 retrieves commands from the submission queues of inserter 109 for processing each command. In some embodiments, processing circuitry 104 retrieves commands from the submission queues in a round-robin manner, wherein one command is retrieved from each submission queue sequentially at a time. This is at least one feature that ensures that each host (e.g., first host 108 and second host 112) has fair access to processing circuitry 104 when accessing memory circuitry 106. In some embodiments, hosts (e.g., first host 108 and second host 112) may be executing two different applications.

[0023] Port 107 is an input / output port configured to receive commands (e.g., first command 110 and second command 113) from multiple hosts (e.g., first host 108 and second host 112) on bus 111 and to transmit data from device 102 to bus 111. In some embodiments, port 107 is communicatively coupled to I / O circuitry 105. Bus 111 can transport commands and data between port 107 and inserter 109. Bus 111 can use Non-Volatile Memory High Speed ​​(NVMe), Peripheral Component Interconnect High Speed ​​(PCIe), or any other suitable network protocol to transport commands and data.

[0024] Additionally, device 102 includes a memory circuit system 106. The memory circuit system 106 may also be referred to hereinafter as the memory of device 102. In some embodiments, the memory circuit system 106 includes any one or more non-volatile memories, such as phase-change memory (PCM), PCM and switch (PCMS), ferroelectric random access memory (FeRAM) or ferroelectric transistor random access memory (FeTRAM), memristors, spin-transfer torque random access memory (STT-RAM) and magnetoresistive random access memory (MRAM), any other suitable memory, or any combination thereof. In some embodiments, the memory circuit system 106 includes a memory with a certain memory density, which is any of the following memory densities: (a) single-level primitive (SLC) memory density, (b) multi-level primitive (MLC) memory density, (c) three-level primitive (TLC) memory density, (d) four-level primitive (QLC) memory density, (e) five-level primitive (PLC) memory density, or (f) a memory density greater than 5 bits per memory cell. Processing circuitry 104 is communicatively coupled to memory circuitry 106 to store and access data in memory blocks or pages of memory circuitry 106. In some embodiments, a data bus interface is used to transport data transfer requests or data. In some embodiments, the data bus interface includes a data transfer request bus and a data interface. In some embodiments, memory circuitry 106 includes a plurality of memory dies. In some embodiments, memory circuitry 106 includes a plurality of memory strips, each memory strip spanning each memory die. In some embodiments, memory circuitry 106 may be accessed (e.g., read or write) by processing circuitry using direct memory access (DMA). In this embodiment, processing circuitry includes: a processor for executing instructions; and a memory controller (e.g., a DMA controller) for processing and performing DMA transfers independently of the processor's execution of instructions.

[0025] In some embodiments, device 102 further includes volatile memory, which may include any one or more volatile memories, such as static random access memory (SRAM). In some embodiments, the volatile memory is configured to temporarily store data (e.g., first command 110 and second command 113) while processing circuitry 104 processes commands from a host (e.g., first host 108 and second host 112). In some embodiments, each of processing circuitry 104 and I / O circuitry 105 is communicatively coupled to the volatile memory to store and access commands (first command 110 and second command 113) received from the host (e.g., first host 108 and second host 112) via inserter 109. In some embodiments, a data bus interface is used to transport commands (e.g., first command 110 and second command 113) or command data from the volatile memory to processing circuitry 104. In some embodiments, the volatile memory is communicatively coupled to memory circuitry 106, which is configured to serve as a cache or temporary memory storage device for memory circuitry 106. In some embodiments, the data bus interface between the memory circuit system 106 and the volatile memory provides a network bus for accessing data to the memory circuit system 106 or writing data to the memory circuit system 106.

[0026] In some embodiments, the processor or processing unit of the processing circuitry system 104 may include a hardware processor, a software processor (e.g., a processor emulated using a virtual machine), or any combination thereof. The processor may include any suitable software, hardware, or both for controlling the memory circuitry system 106 and the processing circuitry system 104 while executing instructions. In some embodiments, the apparatus 102 may also include a multi-core processor. In some embodiments, the processing circuitry system 104 includes a memory controller (e.g., a direct memory access (DMA) controller) that may include any suitable software, hardware, or both for accessing the memory circuitry system 106 independently of the processor executing instructions. The memory circuitry system 106 may also include hardware elements for non-transitory storage of instructions, commands, or requests.

[0027] In some embodiments, device 102 may be a storage device (e.g., an SSD device) that may include one or more packages of memory dies (e.g., memory circuitry 106), wherein each die includes a storage cell. In some embodiments, the storage cells are organized into pages or superpages such that pages and superpages are organized into blocks. In some embodiments, each storage cell is capable of storing one or more bits of information.

[0028] For clarity and brevity, and not as a limitation, this disclosure is provided in the context of interleaving and processing commands (e.g., first command 110 and second command 113) for accessing memory circuitry 106 from multiple hosts (e.g., first host 108 and second host 112) via a single port (e.g., port 107) of device 102. The process of interleaving and processing commands (e.g., first command 110 and second command 113) from multiple hosts (e.g., first host 108 and second host 112) via a single port can be configured by any suitable software, hardware, or both for implementing this feature and functionality. The interleaving and processing of commands from multiple hosts via a single port of the device can be implemented at least partially in, for example, device 102 (e.g., as part of processing circuitry 104 or any other suitable device). For example, for a solid-state storage device (e.g., device 102), the interleaving and processing of commands from multiple hosts via a single port can be implemented in processing circuitry 104. Interleaving and processing commands from multiple hosts via a single port provides improved link efficiency on the bus 111 between the inserter 109 at port 107 and device 102. This improved link efficiency will also result in increased execution speed of device 102 for processing commands for accessing memory circuitry 106 while the processing circuitry concurrently executes instructions independent of the multiple hosts. Furthermore, the interleaving and processing of commands by device 102 reduces the cost, memory overhead, and processing overhead of inserters or protection locks (e.g., inserter 109) used to communicatively couple hosts (e.g., first host 108 and second host 112) to port 107 of device 102.

[0029] Figure 2 This illustrates an exemplary read command 203 from a second host 112, according to some embodiments of the present disclosure. Figure 1 An illustrative diagram of the processing circuitry system 104 is provided. The processing circuitry system 104 may include a processor 202 and a memory controller 204. While the processor 202 can execute instructions for a device (e.g., device 102), the memory controller 204 is configured to receive and process commands (e.g., a read command 203 from a second host 112). In some embodiments, while the processor 202 executes instructions, the memory controller 204 processes each command (e.g., the read command) such that while the processor 202 executes instructions for device 102, a host (e.g., a first host 108 and a second host 112) can access the memory circuitry system 106.

[0030] When processing a received command (e.g., read command 203), memory controller 204 may divide each command into corresponding segments. Memory controller 204 then stores the data transfer request (e.g., data transfer request 205) corresponding to one of the corresponding segments into data structure instances (e.g., first data structure instance 206 and second data structure instance 208). In some embodiments, each of first data structure instance 206 and second data structure instance 208 is implemented in memory controller 204; however, each of first data structure instance 206 and second data structure instance 208 may be implemented in processing circuitry system 104. In some embodiments, first data structure instance 206 and second data structure instance 208 are mailboxes (e.g., DMA mailboxes) for temporarily storing data transfer requests (e.g., data transfer request 205), such as DMA requests. Memory controller 204 stores the data transfer request for the corresponding segment of the corresponding command based on the port ID included within the corresponding command. Therefore, segments of commands originating from the same host will be stored by memory controller 204 in the same data structure instance. In some embodiments, for each host (e.g., first host 108 and second host 112) that is communicatively coupled to device 102, there is a corresponding data structure instance (e.g., first data structure instance 206 and second data structure instance 208).

[0031] For example, such as Figure 2 As shown, read command 203 is transmitted from the second host 112 and by the memory controller 204 via inserter 109 and port 107. Figure 2(Not shown in the image) to receive. The memory controller 204 then segments the read command 203 into multiple segments and determines which data transfer request corresponding to the multiple segments will be stored in which data structure instance (e.g., first data structure instance 206 and second data structure instance 208). In some embodiments, the memory controller 204 stores a subset of data transfer requests (e.g., data transfer request 205) in the data structure instance. In some embodiments, the subset of data transfer requests includes at least one data transfer request. Since the read command 203 originates from the second host 112, the memory controller 204 will store the data transfer request (e.g., data transfer request 205) in the second data structure instance 208 based on the port ID associated with the read command 203. Data transfer request 205 is one of many data transfer requests corresponding to a segment of the read command 203. In some embodiments, each data transfer request (e.g., data transfer request 205) includes a memory address of the memory circuitry 106 to be accessed. In some embodiments, if the corresponding data transfer request corresponds to a segment of a write command, the corresponding data transfer request may also include host data for storage at a memory address in the memory circuitry 106. The memory controller 204 may also include a data transfer engine 210 (e.g., a DMA engine) to execute data transfer requests (e.g., data transfer request 205). Figure 2 As shown, by transmitting read request 207 to memory circuitry 106, data transfer engine 210 executes data transfer request 205. When memory circuitry 106 receives read request 207, it reads data stored at the memory address of memory circuitry 106 included in read request 207. Memory circuitry 106 then transmits read data 209 corresponding to read request 207 to memory controller 204. Finally, memory controller 204 receives read data 209 and transmits it to second host 112 on bus 111 via inserter 109 (bus 111 and inserter 109 not shown). In some embodiments, memory controller 204 is configured to perform data transfer in a polling manner from each data structure instance (e.g., first data structure instance 206 and second data structure instance 208) such that when data transfer requests stored in each data structure instance are transmitted to data transfer engine 210, they are interleaved.

[0032] Figure 3A flowchart illustrating illustrative steps of a process 300 for performing data transfer on a device according to some embodiments of the present disclosure is shown. In some embodiments, the systems, devices, processing circuitry systems, I / O circuitry systems, memory circuitry systems (e.g., the memory of the device), ports, first hosts, inserters, first commands, buses, second hosts, second commands, processors, memory controllers, data transfer, first data structure instances, read requests, second data structure instances, read data, and data transfer engines mentioned may be implemented / represented as system 100, device 102, processing circuitry system 104, I / O circuitry system 105, memory circuitry system 106, port 107, first host 108, inserter 109, first command 110, bus 111, second host 112, second command 113, processor 202, memory controller 204, data transfer request 205, first data structure instance 206, read request 207, second data structure instance 208, read data 209, and data transfer engine 210. In some embodiments, process 300 can be modified by, for example, rearranging, changing, adding and / or removing steps.

[0033] In step 302, the processing circuitry receives multiple commands (e.g., write and read commands) via a port, wherein the multiple commands originate from at least two hosts using the inserter (e.g., a first host and a second host), and each of the multiple commands includes a corresponding memory address and a corresponding port identifier (ID). In some embodiments, each of the multiple commands originates from one of the at least two hosts using the inserter. In some embodiments, the inserter includes multiple submission queues, each corresponding to a corresponding host. In some embodiments, each of the multiple commands includes a corresponding memory address and a corresponding port identifier (ID). The memory address included in each corresponding command corresponds to the memory address of the device whose memory the processing circuitry accesses (e.g., reads and writes). Once the processing circuitry receives the multiple commands, the processing circuitry then, in step 304, segments each of the received commands into corresponding multiple segments, each segment having a predetermined transfer size.

[0034] In step 304, the processing circuitry divides each of the received commands into multiple segments, each segment having a predetermined transmission size. In some embodiments, the predetermined transmission size of each segment is not less than the maximum packet size (MPS) or minimum transmission size supported by the device. In some embodiments, the MPS and minimum transmission size are defined by a bus or interface used to connect the device to the plurality of hosts. Once the processing circuitry has divided each of the received commands into multiple segments, the processing circuitry then transmits each of the respective multiple segments to the corresponding data structure instance corresponding to the port ID of the corresponding received command in step 306.

[0035] In step 306, the processing circuitry transmits each of its plurality of segments to a corresponding data structure instance corresponding to the port ID of the corresponding received command. In some embodiments, each corresponding data structure instance is a mailbox (e.g., a direct memory access (DMA) mailbox). In some embodiments, a corresponding data structure instance exists for each corresponding host coupled to the device in a communicative manner. Each data structure instance is configured to temporarily store a data transfer request (e.g., a DMA request), and each data transfer request corresponds to one of the plurality of segments. In some embodiments, each data transfer request stored in the corresponding data structure instance originates from a corresponding host among the plurality of hosts coupled to the single port. In step 308, the processing circuitry then performs the data transfer for each of the plurality of segments by accessing the device's memory by each corresponding memory address associated with each corresponding segment.

[0036] In step 308, the processing circuitry performs data transfer for each of the plurality of segments via memory of each corresponding memory address access device associated with each corresponding segment. The processing circuitry will perform data transfer for the segment corresponding to a data transfer request in a corresponding data structure instance at a given time. In some embodiments, the processing circuitry performs data transfer for a first subset of segments of a first command via memory of each corresponding memory address access device associated with each corresponding segment of a first subset of segments of a first command, and subsequently performs data transfer for a second subset of segments of a second command via memory of each corresponding memory address access device associated with each corresponding segment of a second subset of segments of a second command. In some embodiments, each subset of the first and second subsets of segments includes at least one segment from its corresponding command. Additionally, each of the first and second commands may include a different port ID, indicating that the first and second commands originate from different hosts.

[0037] Figure 4AA flowchart illustrating illustrative steps of a sub-process 400 for executing a read command received from a corresponding host, according to some embodiments of the present disclosure. In some embodiments, the systems, devices, processing circuitry systems, I / O circuitry systems, memory circuitry systems, ports, first hosts, inserters, first commands, buses, second hosts, second commands, processors, memory controllers, data transfer, first data structure instances, read requests, second data structure instances, read data, and data transfer engines mentioned may be implemented / represented as system 100, device 102, processing circuitry system 104, I / O circuitry system 105, memory circuitry system 106, port 107, first host 108, inserter 109, first command 110, bus 111, second host 112, second command 113, processor 202, memory controller 204, data transfer request 205, first data structure instance 206, read request 207, second data structure instance 208, read data 209, and data transfer engine 210. In some embodiments, subprocess 400 can be modified by, for example, rearranging, changing, adding and / or removing steps.

[0038] In step 402, based on the port ID of the read command, the processing circuitry causes data associated with each corresponding segment of the plurality of segments of the read command to be transmitted to one of the at least two hosts via a port. Each segment of the read command includes a destination memory address corresponding to a memory address of the device's memory. When the processing circuitry executes the data transfer of the corresponding segment of the read command, the data stored at the destination memory address of the corresponding segment is read by the processing circuitry. In some embodiments, based on the port ID of the command, the data read at the corresponding destination memory address is then transmitted from a single port of the device to a host. In some embodiments, I / O circuitry is used to transmit data read for at least one segment of the command to the host that initially sent the command.

[0039] Figure 4BA flowchart illustrating illustrative steps of a sub-process 401 for executing a write command received from a corresponding host, according to some embodiments of the present disclosure. In some embodiments, the systems, devices, processing circuitry systems, I / O circuitry systems, memory circuitry systems, ports, first hosts, inserters, first commands, buses, second hosts, second commands, processors, memory controllers, data transfer, first data structure instances, read requests, second data structure instances, read data, and data transfer engines mentioned may be implemented / represented as system 100, device 102, processing circuitry system 104, I / O circuitry system 105, memory circuitry system 106, port 107, first host 108, inserter 109, first command 110, bus 111, second host 112, second command 113, processor 202, memory controller 204, data transfer request 205, first data structure instance 206, read request 207, second data structure instance 208, read data 209, and data transfer engine 210. In some embodiments, subprocess 400 can be modified by, for example, rearranging, changing, adding and / or removing steps.

[0040] In step 403, the processing circuitry causes data associated with each of the plurality of segments of the write command to be stored in the device's memory at a corresponding memory address associated with each corresponding segment. Each of the plurality of segments of the write command includes host data and a destination memory address corresponding to a memory address in the device's memory. When the processing circuitry executes a data transfer request for a corresponding segment of the write command, the host data associated with the corresponding segment of the write command is stored in the device's memory at the destination memory address. In some embodiments, the host data overwrites data previously stored at the destination memory address. In some embodiments, the destination memory address for which the data transfer request for the segment is to be executed refers to a logical block address (LBA). When the processing circuitry executes a data transfer request for the write command, the processing circuitry may determine the physical address of the memory that can be mapped to the logical destination memory address of the data transfer request for the segment. In some embodiments, this logical-to-physical (L2P) mapping may be stored and maintained by a lookup table. Therefore, if the destination memory address of a read command matches one of the L2P mappings in the lookup table, the processing circuitry accesses the data stored at the physical memory address corresponding to the matching L2P mapping.

[0041] Figure 5A flowchart illustrating the illustrative steps of a sub-process 500 for performing data transfer on an apparatus by interleaving data transfers of commands from each of the respective hosts, according to some embodiments of the present disclosure. In some embodiments, the systems, apparatuses, processing circuitry systems, I / O circuitry systems, memory circuitry systems, ports, first hosts, inserters, first commands, buses, second hosts, second commands, processors, memory controllers, data transfers, first data structure instances, read requests, second data structure instances, read data, and data transfer engines mentioned may be implemented / represented as system 100, apparatus 102, processing circuitry system 104, I / O circuitry system 105, memory circuitry system 106, port 107, first host 108, inserter 109, first command 110, bus 111, second host 112, second command 113, processor 202, memory controller 204, data transfer request 205, first data structure instance 206, read request 207, second data structure instance 208, read data 209, and data transfer engine 210. In some embodiments, subprocess 500 can be modified by, for example, rearranging, changing, adding and / or removing steps.

[0042] In step 502, the processing circuitry performs data transfer of the first subset of the segments of the first command by accessing the device's memory through each corresponding memory address associated with each corresponding segment of the first subset of the segments of the first command. In some embodiments, the first command includes a first port ID indicating that the first command originates from a first host. In some embodiments, the first subset of segments includes at least one segment of the first command. In some embodiments, before the processing circuitry performs data transfer of the first subset of segments, the data transfer request for the first subset of segments is temporarily stored in a first data structure instance (e.g., a DMA mailbox). The data transfer request for the first subset of segments may include any one of a read request, a write request, or any other suitable request for accessing the device's memory. In some embodiments, the data transfer request for the first subset of segments is the only data transfer request stored in the first data structure instance when the processing circuitry is about to perform the data transfer request. Once the processing circuitry performs data transfer of the first subset of the segments of the first command, the processing circuitry may perform data transfer of the second subset of the segments of the second command in step 504.

[0043] In step 504, the processing circuitry performs a data transfer of the second subset of the second command segment by accessing the device's memory through each corresponding memory address associated with a corresponding segment of the second subset of the second command segment. In some embodiments, the second command includes a second port ID indicating that the second command originates from a second host. In some embodiments, the second subset of the segment includes at least one segment of the second command. In some embodiments, before the processing circuitry performs the data transfer of the second subset of the segment, the data transfer request for the second subset of the segment is temporarily stored in a second data structure instance (e.g., a DMA mailbox). The data transfer request for the second subset of the segment may include any one of a read request, a write request, or any other suitable request for accessing the device's memory. In some embodiments, the data transfer request for the second subset of the segment is the only data transfer request stored in the second data structure instance when the processing circuitry is about to perform the data transfer request.

[0044] Unless otherwise expressly stated, the terms “an embodiment,” “an embodiment,” “multiple embodiments,” “the embodiment,” “the multiple embodiments,” “one or more embodiments,” “some embodiments,” and “an embodiment” mean “one or more (but not all) embodiments.”

[0045] Unless otherwise expressly stated, the terms “including,” “comprise,” “have,” and variations thereof mean “including, but not limited to”.

[0046] Unless otherwise explicitly stated, the list of items does not imply that any or all of the items are mutually exclusive.

[0047] Unless otherwise expressly stated, the terms “a,” “an,” and “the” mean “one or more.”

[0048] Unless otherwise expressly stated, devices communicating with each other do not need to communicate continuously with each other. Furthermore, devices communicating with each other may communicate directly or indirectly through one or more media.

[0049] The description of an embodiment having several components that communicate with each other does not imply that all such components are necessary. Instead, various optional components are described to illustrate various possible embodiments. Furthermore, while process steps, method steps, algorithms, etc., may be described in sequential order, such processes, methods, and algorithms may be configured to operate in an alternative order. In other words, any order or sequence of steps that may be described does not necessarily indicate that the steps must be performed in that order. The steps of the process described herein may be performed in any actual order. Additionally, some steps may be performed simultaneously.

[0050] When a single device or object is described herein, it will be readily apparent that, instead of a single device / object, more than one device / object (whether or not they cooperate) may be used. Similarly, when more than one device or object (whether or not they cooperate) is described herein, it will be readily apparent that, instead of said more than one device or object, a single device / object may be used, or, instead of the number of devices or procedures shown, a different number of devices / objects may be used. The function and / or feature of a device may alternatively be embodied by one or more other devices that are not explicitly described as having such function / feature. Therefore, other embodiments do not need to include the device itself.

[0051] The operations illustrated in the accompanying drawings may represent events occurring in a certain order. In alternative embodiments, some operations may be performed, modified, or removed in a different order. Furthermore, steps may be added to the logic described above, still conforming to the described embodiments. Additionally, the operations described herein may occur sequentially, or some operations may be processed in parallel. Furthermore, operations may be performed by a single processing unit or by distributed processing units.

[0052] For illustrative and descriptive purposes, the foregoing description of various embodiments has been presented. It is not intended to be exhaustive or limited to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings.

Claims

1. An apparatus comprising: A port, coupled to a bus, wherein at least two hosts are coupled to the bus in a communicable manner using an inserter; Memory circuitry; and A processing circuit system, coupled to the port and coupled to the memory circuit system, the processing circuit system being used for: Multiple commands are received through the port, wherein the multiple commands are from the at least two hosts using the inserter, and wherein each of the multiple commands includes a corresponding memory address and a corresponding port identifier ID; Each received command is divided into multiple segments, each segment having a predetermined transmission size; Each of its multiple segments is transmitted to the corresponding data structure instance corresponding to the port ID of the corresponding receiving command; and Data transfer of each of the plurality of segments is performed by accessing the memory circuitry at each corresponding memory address associated with each corresponding segment.

2. The apparatus of claim 1, wherein an example of the corresponding data structure is a corresponding memory mailbox.

3. The apparatus of claim 1, wherein at least one of the plurality of commands is a read command, and the processing circuitry is further configured to: Through the port, based on the port ID of the read command, data associated with each corresponding segment of the plurality of segments of the read command is transmitted to one of the at least two hosts.

4. The apparatus of claim 1, wherein at least one of the plurality of commands is a write command, and the processing circuitry is further configured to: This ensures that the data associated with each of the plurality of segments of the write command is stored in the memory circuitry at the corresponding memory address associated with each corresponding segment.

5. The apparatus of claim 1, wherein the predetermined transmission size is not less than the maximum packet size (MPS) and minimum transmission size supported by the apparatus.

6. The apparatus of claim 1, wherein the processing circuitry comprises: A processor is used to execute instructions; and Memory controller, used for: The plurality of commands are received through the port, wherein the plurality of commands are from the at least two hosts using the inserter, and wherein each of the plurality of commands includes a corresponding memory address and a corresponding port identifier ID; Each of the received commands is divided into multiple segments, each segment having the predetermined transmission size; Each of its multiple segments is transmitted to the corresponding data structure instance corresponding to the port ID of the corresponding receiving command; and Data transfer of each of the plurality of segments is performed by accessing the memory circuitry at each corresponding memory address associated with each corresponding segment.

7. The apparatus of claim 6, wherein the memory controller is a direct memory access (DMA) controller.

8. The apparatus of claim 1, wherein in order to receive the plurality of commands via the port, the processing circuitry system will retrieve each of the plurality of commands from at least one submission queue of the inserter via the bus, wherein each submission queue in the at least one submission queue temporarily stores commands received from the at least two hosts.

9. The apparatus of claim 1, wherein the corresponding port ID of each of the plurality of commands corresponds to one of the at least two hosts.

10. The apparatus of claim 1, wherein the processing circuitry further comprises: Data transfer of the first subset of the segments of the first command is performed by accessing the memory circuitry at each corresponding memory address associated with each corresponding segment of the first subset of the segments of the first command; and The data transfer of the second subset of the second command segment is performed by accessing the memory circuitry at each corresponding memory address associated with each corresponding segment of the second subset of the second command segment.

11. A method for performing data transfer on a device, the device including a port coupled to a bus, at least two hosts being communicatively coupled to the bus using an inserter, the method comprising: The processing circuitry of the device receives multiple commands through the port, wherein the multiple commands originate from the at least two hosts using the inserter, and wherein each of the multiple commands includes a corresponding memory address and a corresponding port identifier ID; The processing circuit system divides each of the received commands into multiple segments, each segment having a predetermined transmission size; The processing circuit system transmits each of its multiple segments to the corresponding data structure instance corresponding to the port ID of the corresponding received command; and The processing circuitry system performs data transfer for each of the plurality of segments by accessing the memory of the device at each corresponding memory address associated with each corresponding segment.

12. The method of claim 11, wherein the corresponding data structure instance is the corresponding memory mailbox.

13. The method of claim 11, wherein at least one of the plurality of commands is a read command, and the method further comprises: Through the port, based on the port ID of the read command, data associated with each corresponding segment of the plurality of segments of the read command is transmitted to one of the at least two hosts.

14. The method of claim 11, wherein at least one of the plurality of commands is a write command, and the method further comprises: This causes the data associated with each of the plurality of segments of the write command to be stored in the device's memory at the corresponding memory address associated with each corresponding segment.

15. The method of claim 11, wherein the predetermined transmission size is not less than the maximum packet size (MPS) and minimum transmission size supported by the device.

16. The method of claim 11, further comprising: The instructions are executed by the processor of the processing circuit system.

17. The method of claim 11, wherein: Receiving the plurality of commands through the port includes receiving the plurality of commands by the memory controller of the processing circuitry system through the port; Dividing each of the received commands into multiple segments includes the memory controller dividing each of the received commands into multiple segments. Transmitting each of the multiple segments to the corresponding data structure instance corresponding to the port ID of the corresponding receive command includes the memory controller transmitting each of the multiple segments to the corresponding data structure instance corresponding to the port ID of the corresponding receive command. and Performing data transfer of each of the plurality of segments by accessing the memory of the device by each corresponding memory address associated with each corresponding segment includes the memory controller performing data transfer of each of the plurality of segments by accessing the memory of the device by each corresponding memory address associated with each corresponding segment.

18. The method of claim 17, wherein the memory controller is a direct memory access (DMA) controller.

19. The method of claim 11, wherein receiving the plurality of commands via the port comprises the processing circuitry retrieving each of the plurality of commands from at least one submission queue of the inserter via the bus, wherein each submission queue in the at least one submission queue temporarily stores commands received from the at least two hosts.

20. The method of claim 11, wherein the corresponding port ID of each of the plurality of commands corresponds to one of the at least two hosts.

21. The method of claim 11, wherein the method further comprises: Data transfer of the first subset of the first command segment is performed by accessing the memory of the device by each corresponding memory address associated with each corresponding segment of the first subset of the first command segment; and The data transfer of the second subset of the second command segment is performed by accessing the memory of the device by each corresponding memory address associated with each corresponding segment of the second subset of the second command segment.

22. A non-transitory computer-readable medium having instructions encoded thereon, which, when executed, cause to perform a method comprising: Multiple commands are received via a port, wherein the port is coupled to a bus, at least two hosts are coupled to the bus in a communicative manner using an inserter, the multiple commands are from the at least two hosts using the inserter, and each of the multiple commands includes a corresponding memory address and a corresponding port identifier ID; Each received command is divided into multiple segments, each segment having a predetermined transmission size; Each of its multiple segments is transmitted to the corresponding data structure instance corresponding to the port ID of the corresponding receiving command; and Data transfer of each of the plurality of segments is performed by accessing the memory of the non-transitory computer-readable medium at each corresponding memory address associated with each corresponding segment.

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