Fractal analog random access memory

By simulating random access memory devices using fractals, and utilizing sampling and holding capacitors in the array geometry, combined with readout transistors and peripheral amplifiers, the problem of slow matrix-vector multiplication speed was solved, enabling efficient training of artificial intelligence neural networks.

CN122374824APending Publication Date: 2026-07-10INTERNATIONAL BUSINESS MACHINE CORPORATION
View PDF 0 Cites 0 Cited by

Patent Information

Application Number
CN202480078366.2
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Priority Date
2023-12-15
Filing Date
2024-11-03
Publication Date
2026-07-10

AI Technical Summary

Technical Problem

In existing technologies for training artificial intelligence neural networks, matrix-vector multiplication operations are slow, resulting in low training efficiency and making it difficult to meet the requirements of high parallelism and low power consumption.

Method used

Using a fractal analog random access memory device, fast random access to memory cells is achieved through sampling capacitors and holding capacitors in the array geometry, combined with readout transistors, peripheral amplifiers and analog multiplexers, supporting highly parallel matrix-matrix multiplication operations.

Benefits of technology

It enables rapid and economical extraction of voltage values ​​from large-scale capacitor arrays, improves the efficiency of matrix-matrix multiplication, and supports efficient training of artificial intelligence neural networks.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN122374824A_ABST
    Figure CN122374824A_ABST
Patent Text Reader

Abstract

A memory device includes a plurality of memory cells including a sampling capacitor and a holding capacitor in an array geometry, a sense transistor in electrical communication with the sampling capacitor and the holding capacitor, and a peripheral amplifier. The memory device also includes an analog multiplexer that controls digital and analog signals to the array of memory cells to provide random access to the memory cells. The sense transistor provides a single source follower transistor to the peripheral amplifier for each of the plurality of memory cells.
Need to check novelty before this filing date? Find Prior Art