Spi interface flash data protection method

Abstract

The application discloses an SPI interface flash memory data protection method and relates to the technical field of data protection. The method can monitor external or internal power supply fluctuation by using existing reset or other monitoring circuits. The master control chip is reset after the power supply fluctuation is monitored, so that the master control chip does not operate the flash memory when the power supply fluctuates. The original reset circuit on the board can be used to protect the flash memory data when the internal or external power supply fluctuates. The method does not need to add a circuit module, has great advantages for small embedded applications, has obvious cost advantages, and only needs to add several resistors to complete the circuit function.

Description

Technical Field

[0001] This invention relates to the field of data protection technology, and in particular to a method for protecting SPI interface flash memory data. Background Technology

[0002] Flash memory, also known as flash storage, is a type of non-volatile memory. Its storage characteristic is that it can retain data for a long time even without a current supply. This characteristic is the basis for flash memory to become the storage medium of various embedded devices.

[0003] Flash memory typically uses two types of interfaces for data exchange with external devices: parallel interfaces and serial interfaces. Parallel interfaces offer high data transfer rates but require more pins and have more complex timing, making them suitable for scenarios where miniaturization is not critical or where high transfer rates are required. Serial interfaces have fewer pins but slower transfer rates and simpler timing, making them suitable for miniaturized devices or scenarios where storage capacity or transfer rate is not critical. In embedded device applications, miniaturization and low power consumption are usually the primary goals, while performance requirements, i.e., memory transfer rate, can be appropriately reduced depending on the application scenario. Therefore, serial interface flash memory is typically chosen for embedded device applications.

[0004] Serial-interface flash memory typically uses the SPI bus interface. The SPI bus interface is a high-speed, full-duplex, synchronous communication bus that uses only four pins on the chip, saving significant pins. The SPI bus operates in master and slave modes, with one master device and one or more slave devices involved in an SPI communication. The clock signal is issued by the master device and received by the slave device, and all read and write operations are initiated by the master device. When the SPI interface flash memory interacts with external devices, the external device typically acts as the master, issuing the clock signal, and the flash memory acts as the slave, receiving the clock signal. The external device then issues read, write, and erase commands to operate on the flash memory.

[0005] Because the SPI flash memory interface has a small number of pins and simple operation instructions, if it is affected by external factors during use and incorrectly generates various operation instructions, it may damage the data stored in the flash memory. This data corruption often occurs during power fluctuations. Since SPI flash memory generally stores important data related to the product status, data corruption may lead to major failures such as the product failing to boot. Therefore, protecting the flash memory data during power fluctuations is extremely important.

[0006] To prevent power fluctuations during power outages from causing erroneous operations on the flash memory by the main controller, a solution using a backup battery and power-down timing control is currently available. This ensures that the flash memory is not erroneously operated during power outages.

[0007] Once the power failure detection system detects that the external power supply has started to drop to a certain threshold, it reports the power failure information to the power control system. The power control system then switches the power input from the external power supply to the backup battery. After completing the backup battery switch, the power control system controls the flash memory and main controller to power down according to the chip's required timing sequence, thereby ensuring that power fluctuations during a power failure do not generate erroneous operating commands that could damage the flash memory data.

[0008] However, existing methods for preventing erroneous operating commands caused by power fluctuations during power outages have the following drawbacks: 1. Adding modules such as power failure detection, power control, and backup battery complicates the hardware circuitry and reduces product reliability; 2. Adding circuit modules will increase the product size, making it unsuitable for miniaturized embedded applications. 3. Increases product costs; 4. It can only be used in power outage scenarios and cannot guarantee that it will respond to erroneous commands generated when the internal power supply fluctuates during operation. Summary of the Invention

[0009] In view of the above problems, the present invention provides an SPI interface flash memory data protection method to overcome or at least partially solve the above problems. It solves the problems of existing technologies that use methods such as adding power-down detection, power modules, and backup batteries to protect flash memory data during external power fluctuations, resulting in complex circuitry, increased hardware costs, wasted resources, and an inability to protect against erroneous instructions caused by internal power fluctuations.

[0010] This invention provides the following solution: A method for protecting SPI interface flash memory data, comprising: The on-board reset circuit is used to detect the external power supply and internal power supply. Determine whether fluctuations occur in the external power supply and / or the internal power supply; When fluctuations in the external power supply and / or the internal power supply are detected, the on-board reset circuit generates a reset signal, causing the main controller to be in a reset state. This ensures that the SPI interface of the main controller remains silent during fluctuations in the external power supply and / or the internal power supply, preventing the generation of unexpected operation commands to operate the flash memory.

[0011] Preferably, the method for determining whether the on-board reset circuit experiences fluctuations in external power supply includes: The on-board reset circuit passes through The pin receives external power after being divided by the first voltage divider resistor and the second voltage divider resistor; It is determined that the voltage divided by the first voltage divider resistor and the second voltage divider resistor decreases, and the voltage divided by the second voltage divider resistor is lower than the voltage divided by the first voltage divider resistor. After the pin threshold is reached, it is determined that the external power supply is fluctuating.

[0012] Preferably, the method by which the on-board reset circuit determines whether the internal power supply fluctuates includes: Once the voltage supplied to the on-board reset circuit drops to an internal threshold, it is determined that the internal power supply is fluctuating; the internal power supply is used to power the on-board reset circuit, the main controller, and the flash memory.

[0013] Preferably, the reset signal includes a low level output by the on-board reset circuit, which pulls down the rst pin of the main controller that has been pulled high by an external pull-up resistor.

[0014] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects: This application provides a method for protecting SPI interface flash memory data. This method utilizes existing reset or other monitoring circuits to monitor external or internal power fluctuations. Upon detecting power fluctuations, it resets the main control chip, thereby preventing the main control chip from operating on the flash memory during power fluctuations. The protection of flash memory data during internal and external power fluctuations can be achieved using the existing reset circuit on the board; no new circuit modules are required, offering significant advantages for embedded miniaturized applications; and the cost is significantly lower, requiring only a few additional resistors to complete the circuit function.

[0015] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0017] Figure 1 This is a block diagram illustrating the working principle of an SPI interface flash memory data protection method provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of the external power supply monitoring circuit provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the internal power monitoring circuit provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the SPI interface control of the main controller provided in an embodiment of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention are within the scope of protection of the present invention.

[0019] See Figure 1 This invention provides a method for protecting SPI interface flash memory data, such as... Figure 1 As shown, the method may include: The on-board reset circuit is used to detect the external power supply and internal power supply. The method for determining whether fluctuations occur in the external power supply and / or the internal power supply is performed. Specifically, embodiments of this application may provide a method for the on-board reset circuit to determine whether fluctuations occur in the external power supply, including: The on-board reset circuit passes through The pin receives external power after being divided by the first voltage divider resistor and the second voltage divider resistor; It is determined that the voltage divided by the first voltage divider resistor and the second voltage divider resistor decreases, and the voltage divided by the second voltage divider resistor is lower than the voltage divided by the first voltage divider resistor. After the pin threshold is reached, it is determined that the external power supply is fluctuating.

[0020] Furthermore, the method by which the on-board reset circuit determines whether the internal power supply has fluctuated includes: Once the voltage supplied to the on-board reset circuit drops to an internal threshold, it is determined that the internal power supply is fluctuating; the internal power supply is used to power the on-board reset circuit, the main controller, and the flash memory.

[0021] When fluctuations in the external power supply and / or the internal power supply are detected, the on-board reset circuit generates a reset signal, causing the main controller to be in a reset state. This ensures that the SPI interface of the main controller remains silent during fluctuations in the external power supply and / or the internal power supply, preventing the generation of unexpected operation commands to operate the flash memory.

[0022] In a specific implementation, the embodiments of this application may provide that the reset signal includes a low level output by the on-board reset circuit, and the low level will pull down the rst pin of the master controller that has been pulled high by an external pull-up resistor.

[0023] The SPI interface flash memory data protection method provided in this application embodiment utilizes the original reset circuit of the board to detect external power supply fluctuations; utilizes the original reset circuit of the board to detect internal power supply fluctuations; and utilizes the original reset circuit of the board to control the SPI interface of the main controller after detecting internal and external power supply fluctuations.

[0024] The working principles of each part required for the method provided in the embodiments of this application will be described in detail below.

[0025] The on-board reset circuit detects external and internal power supplies. When fluctuations in external or internal power supplies are detected, the reset circuit generates a reset signal, putting the main controller in a reset state. This ensures that the main controller's SPI interface remains silent during these power fluctuations, preventing unexpected commands from being executed on the flash memory.

[0026] 1. The reset circuit monitors the external power supply.

[0027] like Figure 2 As shown, the external power supply is divided by appropriately sized voltage divider resistors R1 and R2 and then input to the PFI pin of the reset circuit. External voltage fluctuations causing VIN to decrease will lower the voltage divider voltage between R1 and R2. Once the voltage divider voltage falls below the threshold value of the PFI pin, the reset circuit will be triggered.

[0028] 2. The reset circuit monitors the internal power supply.

[0029] like Figure 3 As shown, the internal power supply simultaneously powers the reset circuit, the main controller, and the flash memory. The reset circuit has a monitoring function, and it will trigger the reset circuit when the voltage supplied to the reset circuit drops to an internal threshold.

[0030] 3. The reset circuit controls the SPI interface of the main controller.

[0031] like Figure 4 As shown, when the reset circuit is triggered, it outputs a low level, pulling down the RST pin of the master controller, which was previously pulled high by an external pull-up resistor. The RST pin is a global reset input signal for the master controller; when this pin is pulled low, the entire master controller remains in a reset state, thus remaining silent on the SPI bus. This achieves the protection of flash memory data during power fluctuations.

[0032] In summary, the SPI interface flash memory data protection method provided in this application can monitor external or internal power fluctuations using existing reset or other monitoring circuits. By resetting the main control chip upon detecting power fluctuations, the main control chip is prevented from operating on the flash memory during power fluctuations. The protection of flash memory data during internal and external power fluctuations can be achieved using the existing reset circuit on the board; no new circuit modules are required, offering significant advantages for embedded miniaturized applications; and the cost is significantly lower, requiring only a few additional resistors to complete the circuit function.

[0033] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0034] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments or some parts of the embodiments of this application.

[0035] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. In particular, for system or system embodiments, since they are fundamentally similar to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments. The systems and system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. Components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0036] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A method for protecting SPI interface flash memory data, characterized in that, include: The on-board reset circuit is used to detect the external power supply and internal power supply. Determine whether fluctuations occur in the external power supply and / or the internal power supply; When fluctuations in the external power supply and / or the internal power supply are detected, the on-board reset circuit generates a reset signal, causing the main controller to be in a reset state. This ensures that the SPI interface of the main controller remains silent during fluctuations in the external power supply and / or the internal power supply, preventing the generation of unexpected operation commands to operate the flash memory.

2. The SPI interface flash memory data protection method according to claim 1, characterized in that, The method for determining whether the on-board reset circuit experiences fluctuations in external power supply includes: The on-board reset circuit passes through The pin receives external power after being divided by the first voltage divider resistor and the second voltage divider resistor; It is determined that the voltage divided by the first voltage divider resistor and the second voltage divider resistor decreases, and the voltage divided by the second voltage divider resistor is lower than the voltage divided by the first voltage divider resistor. After the pin threshold is reached, it is determined that the external power supply is fluctuating.

3. The SPI interface flash memory data protection method according to claim 1, characterized in that, The method by which the on-board reset circuit determines whether the internal power supply has fluctuated includes: Once the voltage supplied to the on-board reset circuit drops to an internal threshold, it is determined that the internal power supply is fluctuating; the internal power supply is used to power the on-board reset circuit, the main controller, and the flash memory.

4. The SPI interface flash memory data protection method according to claim 1, characterized in that, The reset signal includes a low level output by the on-board reset circuit, which pulls down the rst pin of the main controller that has been pulled high by an external pull-up resistor.

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