A management method of a phase change memory and a phase change memory
By dynamically updating the number of refreshes and the erase/write operations in the phase-change memory, the aging problem caused by frequent refreshes is solved, the thermal crosstalk of the memory cells is optimized, and the lifespan of the memory is extended.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 新存科技(武汉)有限责任公司
- Filing Date
- 2026-03-25
- Publication Date
- 2026-07-14
AI Technical Summary
In existing technologies, frequent data refresh operations significantly reduce the write life of phase-change memory, leading to memory aging and affecting data integrity and accuracy.
By refreshing when the number of operations reaches a threshold and dynamically updating the threshold based on the mitigation characteristics of thermal crosstalk, combined with erase and write operations, the thermal crosstalk problem of memory cells is optimized, the error frequency and severity are reduced, and the memory life is extended.
It effectively alleviates thermal crosstalk issues, reduces the need for refresh operations, avoids excessive aging, and improves the stability and lifespan of storage units.
Smart Images
Figure CN122392589A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of phase-change memory technology, specifically to a management method for a phase-change memory and a phase-change memory itself. Background Technology
[0002] To address thermal crosstalk in memory, data refresh is used to rewrite the data in the storage cells back into memory, thereby suppressing thermal crosstalk and ensuring data integrity and accuracy. However, refreshing increases the number of write operations to the memory, and frequent refreshes significantly reduce write lifetime, accelerate memory aging, and shorten the memory's lifespan. Summary of the Invention
[0003] This application provides a management method for phase change memory and a phase change memory to slow down the aging of the phase change memory and extend its service life.
[0004] In a first aspect, this application provides a management method for a phase-change memory, the method comprising: The erase / write step, in response to a data operation command, performs an erase / write operation on the phase-change memory; The refresh step involves refreshing the phase-change memory if the number of operations exceeds a threshold, and updating the threshold based on the thermal crosstalk mitigation characteristics. Based on the updated number of times threshold, the erase / write step is repeated until the refresh step.
[0005] In some embodiments of this application, the thermal crosstalk mitigation characteristics include a scaling factor; The step of updating the number threshold based on the thermal crosstalk mitigation characteristics includes: Based on the scaling factor, the frequency threshold is updated to obtain the updated frequency threshold.
[0006] In some embodiments of this application, the updated number threshold is obtained according to the following formula: Tn'=Tn×(1+m); In the formula, Tn' is the updated number threshold, Tn is the number threshold, and m is the scaling factor.
[0007] In some embodiments of this application, the phase-change memory includes a storage array, the storage array includes multiple storage blocks, each storage block includes multiple storage cells, and each storage block corresponds to a primary threshold; the data operation instruction includes the location information of the target storage cell; The erase / write operation on the phase-change memory includes: Based on the location information of the target storage unit, an erase / write operation is performed on the target storage unit; The number of operations to update the target storage block where the target storage unit is located; Accordingly, prior to the refresh step, the method further includes: The number of operations on the target storage block is compared with the threshold number of operations corresponding to the target storage block.
[0008] In some embodiments of this application, the initial value of the number of times threshold corresponding to the storage block is determined based on the number of storage cells in the storage block and the write endurance performance of the phase change memory.
[0009] In some embodiments of this application, refreshing the phase-change memory includes: Refresh each storage unit within the target storage block.
[0010] In some embodiments of this application, the erase / write step is repeated if the number of operations is less than or equal to the number threshold.
[0011] In some embodiments of this application, the number of operations for updating the target storage block where the target storage unit is located includes: Obtain the current number of operations on the target storage block; After performing an erase / write operation on the target storage unit, the current operation count is incremented by 1.
[0012] In some embodiments of this application, the method further includes, prior to the erasure / write step: Initialize the number of operations for each of the target storage blocks.
[0013] Secondly, this application also provides a phase-change memory, comprising: The erase / write module is used to perform erase / write operations on the phase-change memory in response to data operation commands; The refresh module is used to refresh the phase-change memory when the number of operations exceeds a threshold, and to update the threshold based on the thermal crosstalk mitigation characteristics.
[0014] Through one or more embodiments of the above embodiments in this application, at least the following technical effects can be achieved: In the phase-change memory (PCM) management method provided in this application, erase and write operations are repeatedly performed on the PCM according to a threshold number of operations. These multiple operations mitigate thermal crosstalk, thereby reducing the frequency and severity of errors caused by thermal crosstalk. This reduces the need for refresh operations, avoids excessive aging caused by frequent refreshes, and extends the lifespan of the PCM. Furthermore, by dynamically updating the threshold number of operations, the erase and write operations of the PCM can be optimized based on the thermal crosstalk mitigation characteristics of the memory cells, further alleviating thermal crosstalk, improving the stability of the memory cells, and extending their lifespan. Attached Figure Description
[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0016] Figure 1 This is one of the flowcharts illustrating the management method of phase-change memory provided in the embodiments of this application; Figure 2 This is a schematic diagram illustrating the relationship between the number of refreshes and the refresh threshold provided in an embodiment of this application; Figure 3 This is a second schematic flowchart of the phase-change memory management method provided in the embodiments of this application; Figure 4 This is a schematic diagram of the target storage block provided in an embodiment of this application; Figure 5 This is a schematic diagram of the experimental results provided in the embodiments of this application. Detailed Implementation
[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0018] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0019] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.
[0020] The use of "applies to" or "configured to" in this application implies open and inclusive language, which does not preclude applicability to or configuration to devices performing additional tasks or steps. Furthermore, the use of "based on" implies openness and inclusivity, because processes, steps, calculations, or other actions "based on" one or more conditions or values may in practice be based on additional conditions or values beyond those conditions.
[0021] In this application, the term "exemplary" is used to mean "used as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use this application. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be made without using these specific details. In other instances, well-known structures and processes are not described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.
[0022] The management method and phase change memory provided in the embodiments of this application are described below with reference to the accompanying drawings.
[0023] like Figure 1 As shown in the embodiment of this application, a management method for a phase-change memory is provided, which includes the following steps: The S101 erase / write step, in response to a data operation command, performs an erase / write operation on the phase-change memory.
[0024] Data manipulation instructions can include various operations on the phase-change memory, such as data modification, deletion, or rewriting. The erase / write operation is performed on a storage cell in the phase-change memory to delete the original data in the cell and reset it to its initial state so that new data can be stored.
[0025] In some examples, for phase change memory (PCM), the erase / write operation involves changing the phase change material in the memory cell from a low-resistivity state to a high-resistivity state, thereby erasing the data. Through the erase / write operation, the resistance state of the memory cell is cleared, preparing it for the writing of new data.
[0026] In the S102 refresh step, if the number of operations exceeds the threshold, the phase-change memory is refreshed, and the threshold is updated according to the thermal crosstalk mitigation characteristics.
[0027] The number of operations is the total number of erase / write operations performed. Each erase / write operation increases the number of operations.
[0028] The purpose of the refresh operation is to ensure data integrity and reliability through specific correction steps when the state of a storage cell changes, especially when data distortion is caused by thermal crosstalk. Specifically, thermal crosstalk can cause heat conduction between adjacent storage cells, affecting the stability of data storage. The refresh operation restores the correct state of the storage cell by reading the data from the storage cell and correcting and rewriting the data as necessary. In this way, even if the storage cell changes due to thermal effects, the original data content will not be lost, and the phase-change memory can still maintain data correctness.
[0029] Furthermore, in phase-change memory (PCM), the resistive state of the memory cell is determined by the physical structure of the phase-change material. During the initial erase and write operation, the thermal effect between memory cells is quite significant. Due to the concentrated heat, thermal crosstalk can be severe, leading to data errors. However, as the number of erase and write cycles increases, the accumulation of thermal effect gradually slows down. This means that the temperature change generated by each erase and write operation becomes smaller and smaller, and the thermal crosstalk between memory cells also weakens. In other words, through repeated erase and write operations, the thermal response characteristics of the memory cell gradually stabilize during the material's "break-in" process (i.e., the mitigation of thermal crosstalk). With this increased stability, the frequency and severity of errors caused by thermal crosstalk are significantly reduced, thereby reducing the need for refresh operations.
[0030] Understandably, if the number of operations is less than or equal to the threshold, the erase / write steps are repeated until the number of operations exceeds the threshold, triggering a refresh operation.
[0031] S103, based on the updated number of times threshold, repeat the erase / write step S101 to the refresh step S102.
[0032] In this step, the erase / write step S101 is repeated according to the updated number of times threshold until the number of operations exceeds the updated number of times threshold, at which point the refresh step is executed.
[0033] The phase-change memory (PCM) management method provided in this application repeatedly performs erase and write operations on the PCM according to a threshold number of operations. By performing multiple erase and write operations, thermal crosstalk problems are mitigated, thereby reducing the frequency and severity of errors caused by thermal crosstalk. This reduces the need for refresh operations, avoids excessive aging caused by frequent refreshes, and extends the lifespan of the PCM. Furthermore, by dynamically updating the threshold number of operations, the erase and write operations of the PCM can be optimized based on the thermal crosstalk mitigation characteristics of the memory cells, further alleviating thermal crosstalk problems, improving the stability of the memory cells, and extending their lifespan.
[0034] In some embodiments of this application, the thermal crosstalk mitigation characteristics include a scaling factor m (m > 0). This scaling factor m reflects the degree to which the impact of thermal crosstalk on the memory cell gradually decreases with device lifetime or number of operations. The value of m directly reflects the degree to which the cumulative effect of thermal crosstalk is suppressed, released, or passivated. When m is larger, the adverse effect of thermal crosstalk on the memory cell decreases faster, and the allowable number of operations increases faster. When m is smaller, the mitigation process is relatively slow, and a more conservative increase in the number of operations threshold is needed to maintain reliability. The scaling factor m can be obtained by offline testing and fitting, or it can be dynamically calibrated by the controller based on online statistical information or configured by block; there is no limitation on this.
[0035] The threshold for updating the number of iterations is based on the thermal crosstalk mitigation characteristics, including: Based on the scaling factor, the number of times threshold is updated to obtain the updated number of times threshold.
[0036] The phase-change memory management method provided in this application introduces the scaling factor m into the update process of the refresh threshold, enabling the refresh threshold to more accurately control the refresh trigger timing, thereby further suppressing the performance degradation and reliability risks caused by thermal crosstalk and effectively extending the usable life of the phase-change memory.
[0037] In some examples, the updated count threshold is obtained using the following formula: Tn'=Tn×(1+m); In the formula, Tn' is the updated number threshold, Tn is the number threshold, and m is the scaling factor.
[0038] In some examples, by analyzing the test data, we can obtain results such as... Figure 2 The relationship between the threshold number of refreshes and the refresh count shown is derived from... Figure 2 It can be seen that as the number of refreshes increases, the threshold for the number of refreshes generally shows an upward trend, indicating that a higher number of erase and write operations can be allowed in the later stages without frequently triggering refreshes, thereby reducing the refresh frequency.
[0039] Furthermore, a significant exponential relationship exists between the refresh threshold and the number of refreshes. That is, the increase in the refresh threshold is not a constant linear increase, but rather the increase gradually accelerates with the accumulation of refreshes. This relationship indicates that as the number of refreshes increases, the storage unit's resistance to effects such as thermal crosstalk gradually strengthens, thus allowing for more erase operations without requiring frequent refreshes.
[0040] After the k-th refresh is completed, the threshold number of refreshes can be expressed as Tnk' = Tn0×(1+m). kTn0 is the initial value of the count threshold. In some examples, the count threshold can also be combined with upper and lower thresholds, saturation constraints, etc., to avoid insufficient maintenance due to an excessively large count threshold or excessive maintenance due to an excessively small count threshold.
[0041] In some embodiments of this application, the phase-change memory includes a memory array, which includes multiple memory blocks, and each memory block includes multiple memory cells.
[0042] To facilitate differentiated management of usage intensity and reliability risks for different storage blocks, each storage block is assigned an independent number of write / erase cycles threshold. For example, due to differences in physical location, thermal coupling strength, process variations, or historical stress accumulation, different storage blocks may have different allowable consecutive write / erase cycles or allowable thermal crosstalk accumulation levels. Therefore, configuring independent number of write / erase cycles thresholds for different storage blocks can improve the targeting and granularity of management.
[0043] Data operation instructions include the location information of the target storage unit. This location information can be a logical address, a physical address, or a mapping address between the two. Specifically, it may include block address, page address, row / column address, word line selection information, bit line selection information, etc., so as to locate the target storage block where the target storage unit is located and the target storage unit itself through decoding circuitry or address mapping unit. In some embodiments, data operation instructions may also include operation type identifiers (e.g., erase, write, erase-write), data length, verification information, priority information, or timestamp information, etc., without limitation.
[0044] Erasing and writing operations on phase-change memory include: Based on the location information of the target storage unit, perform erase and write operations on the target storage unit; The number of operations to update the target storage block where the target storage unit is located.
[0045] In some examples, the controller can perform address decoding and block gating based on location information. After locating the target storage unit, it first performs an erase operation on the target storage unit to clear the existing data in the target storage unit and restore the storage state to the programmable state, which facilitates the writing of new data.
[0046] To reflect the cumulative usage intensity of the target storage block, the total number of operations on the target storage block is updated after each erase / write operation is completed. In some examples, the number of operations on the target storage block is incremented by 1 for each erase / write operation; in other examples, each erase and each programmable operation can be weighted and accumulated with different weights. This is not limited, as long as it can characterize the cumulative operational load of the target storage block.
[0047] Accordingly, prior to the refresh step, the method also includes: The number of operations on the target storage block is compared with the threshold number of operations corresponding to the target storage block, and a refresh operation is triggered based on the comparison result.
[0048] In some embodiments, if the number of operations on the target storage block is greater than the threshold number corresponding to the target storage block, it is determined that the target storage block has reached or exceeded the preset reliability risk control conditions, and then all storage units in the target storage block are refreshed.
[0049] In other embodiments, if the number of operations on the target storage block is less than or equal to the threshold number corresponding to the target storage block, the target storage block is considered to be within an acceptable operational load range. The erase / write operations on the target storage cells within the target storage block continue, and the total number of operations on the target storage block is updated after each erase / write operation. This process can be repeated until the total number of operations on the target storage block exceeds the threshold number corresponding to the target storage block, at which point a refresh of the target storage block is triggered.
[0050] In some embodiments of this application, the initial value Tn0 of the threshold number corresponding to the storage block is determined based on the number of storage cells within the storage block and the write endurance performance of the phase-change memory, while also taking into account the system's requirements for bit error rate or reliability indicators. The number of storage cells reflects the capacity of the storage block. For a single storage block, what is recorded is the total number of operations accumulated across all storage cells within the block, rather than accurately counting the number of times a single storage cell is actually accessed during the process.
[0051] Specifically, as the number of storage cells within a storage block increases, each erase / write or programming operation indirectly affects more adjacent cells through thermal coupling paths, increasing the potential disturbance boundaries and raising the risk of accumulated thermal crosstalk. In some examples, to ensure that the failure probability of a single storage cell within its write endurance limit (e.g., approximately 300 times per cell) is lower than the system tolerance threshold (e.g., 0.0001), the initial value Tn0 of the operation threshold corresponding to the storage block should be appropriately reduced as the number of storage cells within the block increases. Assuming that storage cells are accessed via random addresses, the expected number of accesses for a single storage cell can be approximated as the total number of block operations divided by the number of block cells. Based on the Poisson statistical distribution, the total number of block operations can be set to a value that meets the failure probability requirement for a single cell. For example, for a block containing 1000 storage cells, if the cell write endurance is approximately 300 times and the required failure probability is less than 0.0001, the total number of block operations can be set to approximately 200,000.
[0052] In addition, the write endurance of the memory also affects Tn0. That is, with long-term operation and repeated erasure and writing, the thermal crosstalk tolerance of a single memory cell decreases. The initial number of times the memory block is written can be appropriately reduced to ensure system reliability.
[0053] In some embodiments of this application, the number of operations for updating the target storage block where the target storage unit is located includes: Get the current number of operations on the target storage block; After performing an erase / write operation on the target storage unit, the current operation count is incremented by 1 to update the current operation count. It is understood that erase / write operations include both erase and write operations. Regardless of whether an erase or write operation is performed, each operation is counted in the block's cumulative operation count, thus reflecting the cumulative programming load on the storage units within that block.
[0054] In some embodiments of this application, the method further includes the following steps before the erase / write step: Initialize the number of operations for each target storage block. That is, initialize the number of operations for each target storage block to 0, and also initialize the threshold number of operations for each target storage block to Tn0.
[0055] like Figure 3 As shown in the embodiments of this application, a method for managing a phase-change memory is also provided, the method comprising the following steps: S301, initialize all counters C(n) and the count threshold Tn, that is, clear counter C(n) to zero and initialize the count threshold Tn to Tn0.
[0056] It should be noted that before initialization, the storage array is divided into N storage blocks, and each storage block corresponds to a counter C(n) that records the number of operations and a threshold number Tn.
[0057] Indicatively, such as Figure 4 As shown, the storage array is divided into N storage blocks Z1, Z2, ..., Zn, ..., ZN of equal size. Each storage block Zn includes multiple storage units, and each storage unit is responsible for storing one data bit. By dividing the entire storage array into multiple smaller storage blocks, data management and operations can be performed more efficiently. In other embodiments of this application, the size of each storage block may also be different, and this is not limited.
[0058] in addition, Figure 4 The thermal crosstalk manager stores a program that, when invoked, executes the phase-change memory management method provided in any embodiment of this application. During erase / write or refresh operations, the memory controller, through the multiplexer MUX, can select one or more of the corresponding memory blocks Z1 to ZN as needed, and access and operate them.
[0059] It is understandable that the Tn0 corresponding to each storage block Zn can be the same or different, and there is no restriction on this.
[0060] S302, according to the data operation instructions, performs an erase / write operation on the target storage cell in the storage block Zn.
[0061] S303: After completing the erase / write operation of the target memory cell, the counter is incremented by one, that is, C(n)'=C(n)+1.
[0062] S304, determine whether the count value is greater than the current count threshold Tn, that is, determine whether C(n)' > Tn. If the determination is negative, proceed to step S302; if the determination is positive, proceed to step S305.
[0063] S305, refresh all storage cells in storage block Zn, and at the same time clear the counter C(n), update the number of times threshold Tn using the scaling factor m, that is, Tn'=Tn×(1+m).
[0064] Depend on Figure 5 The experimental results shown indicate the trend of the raw bit error rate (RBER) of different storage blocks at different stacking layer locations as a function of the number of erase / write cycles. Figure 5 The horizontal axis represents the cumulative number of erase / write operations (EOL) performed on the storage cell, and the vertical axis represents the error rate (RBER) of the storage cell without error correction coding. Figure 5 The positions of the bit line BL0 and word line WL0 of the bottom and top stack layers of three memory blocks Z1, Z2, and Z3 were statistically analyzed. Curves were marked with different colors corresponding to erase / write cycle points CYC1, CYC50, CYC100, CYC150, CYC200, CYC300, and CYC700. With increasing erase / write cycles, the RBER curve of the block initially maintained a low bit error rate, then slowly increased, and stabilized during high erase / write cycles. This trend reflects that the thermal crosstalk accumulation effect is gradually mitigated during continuous erase / write operations, meaning that the sensitivity of memory cells to thermal crosstalk decreases with increasing erase / write cycles. The differences in curves between different memory blocks and stack layers also indicate that block capacity and stack layer position affect the rate and extent of thermal crosstalk accumulation. Larger capacity blocks or bottom-level memory cells are more prone to interference accumulation, while top-level memory cells have a lower accumulation rate.
[0065] based on Figure 5 The experimental results shown can be used to determine the operation threshold and thermal crosstalk mitigation factor for each storage block. In actual operation, the cumulative load of storage cells can be controlled through dynamic refresh or partition management strategies to ensure that the failure probability of a single storage cell within its write endurance limit is lower than the system tolerance threshold, while effectively mitigating the impact of thermal crosstalk on memory reliability.
[0066] The phase-change memory (PCM) management method provided in this application repeatedly performs erase and write operations on the PCM according to a threshold number of operations. By performing multiple erase and write operations, thermal crosstalk problems are mitigated, thereby reducing the frequency and severity of errors caused by thermal crosstalk. This reduces the need for refresh operations, avoids excessive aging caused by frequent refreshes, and extends the lifespan of the PCM. Furthermore, by dynamically updating the threshold number of operations, the erase and write operations of the PCM can be optimized based on the thermal crosstalk mitigation characteristics of the memory cells, further alleviating thermal crosstalk problems, improving the stability of the memory cells, and extending their lifespan.
[0067] This application also provides a phase-change memory, which includes an erase / write module and a refresh module.
[0068] The erase / write module is used to perform erase / write operations on the phase-change memory in response to data operation commands; The refresh module is used to refresh the phase change memory when the number of operations exceeds a threshold, and to update the threshold based on the thermal crosstalk mitigation characteristics. Based on the updated number of times threshold, the erase / write module is repeatedly executed until the refresh module is refreshed.
[0069] The phase-change memory (PCM) provided in this application repeatedly performs erase and write operations on the PCM according to a threshold number of operations. This multiple erase and write operations mitigate thermal crosstalk, thereby reducing the frequency and severity of errors caused by thermal crosstalk. Consequently, the need for refresh operations is reduced, avoiding excessive aging caused by frequent refreshes and extending the lifespan of the PCM. Furthermore, by dynamically updating the threshold number of operations, the erase and write operations of the PCM can be optimized based on the thermal crosstalk mitigation characteristics of the memory cells, further alleviating thermal crosstalk, improving the stability of the memory cells, and extending their lifespan.
[0070] In some embodiments of this application, the thermal crosstalk mitigation characteristics include a scaling factor.
[0071] Accordingly, the refresh module is specifically used for: Based on the scaling factor, the number of times threshold is updated to obtain the updated number of times threshold.
[0072] In some embodiments of this application, the updated number threshold is obtained according to the following formula: Tn'=Tn×(1+m); In the formula, Tn' is the updated number threshold, Tn is the number threshold, and m is the scaling factor.
[0073] In some embodiments of this application, the phase-change memory includes a storage array, the storage array includes multiple storage blocks, each storage block includes multiple storage cells, and each storage block corresponds to a primary threshold; the data operation instruction includes the location information of the target storage cell.
[0074] Accordingly, the erase / write module is specifically used for: Based on the location information of the target storage unit, perform erase and write operations on the target storage unit; The number of operations to update the target storage block where the target storage unit is located; Accordingly, the phase-change memory also includes a comparison module, which is specifically used for: Compare the number of operations on the target storage block with the threshold number of operations corresponding to the target storage block.
[0075] In some embodiments of this application, the initial value of the number of times threshold corresponding to the storage block is determined based on the number of storage cells in the storage block and the write endurance performance of the phase change memory.
[0076] In some embodiments of this application, the refresh module is specifically used for: Refresh each storage unit within the target storage block.
[0077] In some embodiments of this application, the phase-change memory is also used to repeatedly execute the erase / write module when the number of operations is less than or equal to a threshold number.
[0078] In some embodiments of this application, the number of operations for updating the target storage block where the target storage unit is located includes: Get the current number of operations on the target storage block; After performing an erase / write operation on the target storage unit, increment the current operation count by 1.
[0079] In some embodiments of this application, the phase-change memory further includes an initialization module, which is specifically used for: Initialize the number of operations for each target storage block.
[0080] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.
[0081] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods of various embodiments or some parts of embodiments.
[0082] The above provides a detailed description of a phase-change memory management method and a phase-change memory provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A management method for a phase-change memory, characterized in that, The method includes: The erase / write step, in response to data operation commands, performs erase / write operations on the phase-change memory; The refresh step involves refreshing the phase-change memory if the number of operations exceeds a threshold, and updating the threshold based on the thermal crosstalk mitigation characteristics. Based on the updated number of times threshold, the erase / write step is repeated until the refresh step.
2. The management method according to claim 1, characterized in that, The thermal crosstalk mitigation characteristics include a scaling factor; The step of updating the number threshold based on the thermal crosstalk mitigation characteristics includes: Based on the scaling factor, the frequency threshold is updated to obtain the updated frequency threshold.
3. The management method according to claim 2, characterized in that, The updated threshold number is obtained according to the following formula: Tn'=Tn×(1+m); In the formula, Tn' is the updated number threshold, Tn is the number threshold, and m is the scaling factor.
4. The management method according to claim 1, characterized in that, The phase-change memory includes a storage array, which includes multiple storage blocks, each storage block includes multiple storage cells, and each storage block corresponds to a primary threshold; the data operation instruction includes the location information of the target storage cell; The erase / write operation on the phase-change memory includes: Based on the location information of the target storage unit, an erase / write operation is performed on the target storage unit; The number of operations to update the target storage block where the target storage unit is located; Accordingly, prior to the refresh step, the method further includes: The number of operations on the target storage block is compared with the threshold number of operations corresponding to the target storage block.
5. The management method according to claim 4, characterized in that, The initial value of the number of times threshold corresponding to the storage block is determined based on the number of storage cells in the storage block and the write endurance performance of the phase change memory.
6. The management method according to claim 4, characterized in that, The refresh of the phase-change memory includes: Refresh each storage unit within the target storage block.
7. The management method according to any one of claims 1 to 6, characterized in that, If the number of operations is less than or equal to the threshold number, the erase / write step is repeated.
8. The management method according to claim 4, characterized in that, The number of operations to update the target storage block where the target storage unit is located includes: Obtain the current number of operations on the target storage block; After performing an erase / write operation on the target storage unit, the current operation count is incremented by 1.
9. The management method according to claim 4, characterized in that, Prior to the erasing / writing step, the method further includes: Initialize the number of operations for each of the target storage blocks.
10. A phase-change memory, characterized in that, include: The erase / write module is used to perform erase / write operations on the phase-change memory in response to data operation commands; The refresh module is used to refresh the phase-change memory when the number of operations exceeds a threshold, and to update the threshold based on the thermal crosstalk mitigation characteristics.