A logic circuit based on high electron mobility transistors

Abstract

The application discloses a kind of logic circuits based on high electron mobility transistor, belong to semiconductor device technical field, including by or non-gate and non-gate combination or gate circuit, and by and non-gate and non-gate combination and gate circuit.Or non-gate, and non-gate and non-gate are respectively integrated by parallel / series connection of depletion-mode HEMT device and enhancement-mode HEMT device.Construction is adopted in the present application lower layer gradual barrier layer or ladder gradual barrier layer, in combination with ion implantation area design, accurately control threshold voltage from material growth source, completely solve the technical problems of poor threshold voltage consistency and low stability caused by traditional gate recess etching process.Circuit noise tolerance is improved, static power consumption is effectively reduced, and is suitable for high-performance, low-power radio frequency and digital integrated electronic system.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically, it relates to a logic circuit based on a high electron mobility transistor. Background Technology

[0002] High electron mobility transistors (HEMs), a type of field-effect transistor that utilizes a two-dimensional electron gas formed at a heterojunction interface as a channel, have been widely used in radio frequency (RF), microwave, and power electronics fields due to their superior characteristics such as high electron mobility, high saturation velocity, and high cutoff frequency. With the increasing demands for integration, power consumption, and speed in modern electronic systems, integrating logic control functions with core RF or power circuits on a single chip has become an important development direction in the industry. To achieve this goal, some explorations have emerged in existing technologies, such as using gallium arsenide enhancement-mode or depletion-mode pseudo-HEM processes to integrate microwave switches with their logic control circuits to reduce control ports. Furthermore, researchers have also attempted to implement logic functions and reduce gate leakage current through dual-gate transistor structures, logic gates based on low-leakage-current dual cantilever beam switches, and gate structures with complex P-type doped regions.

[0003] However, traditional logic gate structures often fail to fully utilize the inherent characteristics of high electron mobility transistors (HEMs) when applied to high electron mobility transistor (HEM) technology, and face challenges such as gate leakage, increased power consumption, and signal delay during high-speed switching. Currently, the core challenge for HEMs in digital logic integrated circuit applications lies in achieving highly uniform, stable, and precisely designed threshold voltages. Since logic gate circuits require multiple transistors to have strictly matched switching thresholds, any process deviation directly leads to reduced noise margin, timing irregularities, and increased power consumption. Among the mainstream methods for realizing enhancement-mode devices, recessed gate technology, while theoretically offering good design freedom, faces insurmountable bottlenecks in actual production. On the one hand, the uniformity of conventional dry etching processes is difficult to guarantee, resulting in nanometer-level differences in recess depth between different transistors, leading to significant fluctuations in threshold voltage and failing to meet the requirements of large-scale logic arrays. On the other hand, the etching process physically damages the underlying gallium nitride channel and introduces interface states, causing the threshold voltage to drift with time and bias stress, severely affecting the long-term reliability of the circuit. Simultaneously, depletion-mode devices in logic circuits also require precise control of the threshold voltage to effectively address the static power consumption problem of digital circuits.

[0004] In summary, existing high electron mobility transistor (HEM) logic circuit manufacturing processes still have significant shortcomings in terms of precise threshold voltage control and interface protection. Therefore, there is an urgent need to develop a technical solution that can simultaneously address the three major challenges of threshold voltage accuracy, uniformity, and stability from both the material growth stage and the process mechanism, in order to meet the development needs of high-performance integrated logic circuits. Summary of the Invention

[0005] The purpose of this invention is to provide a logic circuit based on high electron mobility transistors, which mainly solves the technical defects of existing high electron mobility transistor logic integrated circuits, such as poor threshold voltage consistency, low stability, and low logic array noise tolerance caused by uneven gate trench dry etching process and plasma damage.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A logic circuit based on high electron mobility transistors (HMTs) is disclosed, comprising an OR gate and an AND gate. The OR gate is composed of a combination of NOR gates and NOT gates, and the AND gate is composed of a combination of NAND gates and NOT gates. The NOR gate is a first integrated device consisting of a depletion-mode HEMT device and a parallel branch containing at least two enhancement-mode HEMT devices. The NAND gate is a second integrated device consisting of a depletion-mode HEMT device and a series branch containing at least two enhancement-mode HEMT devices. The NOT gate is a third integrated device consisting of a depletion-mode HEMT device and an enhancement-mode HEMT device connected in parallel. The first and third integrated devices are combined to form an OR gate GaNHEMT integrated device, and the second and third integrated devices are combined to form an AND gate GaN HEMT integrated device.

[0008] Furthermore, in this invention, the third integrated device includes an epitaxial structure consisting of a substrate, a buffer layer, a channel layer, a lower gradient barrier layer, and an upper main barrier layer stacked sequentially from bottom to top, and an ion implantation region, a first source, a first drain, a second source, a second drain, a gate recess, a first gate, and a second gate disposed on the epitaxial structure; wherein, the ion implantation region penetrates the upper lower gradient barrier layer and the upper main barrier layer, and extends into the lower channel layer or buffer layer; the gate recess extends to the lower gradient barrier layer by etching; the bottoms of the first source, the first drain, the second source, and the second drain are all in contact with the upper end of the channel layer.

[0009] Furthermore, in this invention, the third integrated device includes an epitaxial structure consisting of a substrate, a buffer layer, a channel layer, a stepped gradient barrier layer, and an upper main barrier layer stacked sequentially from bottom to top, and an ion implantation region, a first source, a first drain, a second source, a second drain, a gate groove, a first gate, and a second gate disposed on the epitaxial structure; wherein, the ion implantation region penetrates the upper stepped gradient barrier layer and the upper main barrier layer, and extends into the lower channel layer or buffer layer; the gate groove extends to the stepped gradient barrier layer through etching; the bottoms of the first source, the first drain, the second source, and the second drain are all in contact with the upper end of the channel layer; wherein, the aluminum composition in the stepped gradient barrier layer exhibits discrete stepped transitions along the growth direction.

[0010] Furthermore, in this invention, the stepped gradient barrier layer comprises:

[0011] First sublayer: in contact with the upper main barrier layer; aluminum composition is denoted as... 0.08≤ ≤0.15; its thickness ranges from 2nm to 5nm;

[0012] Second sublayer: Aluminum composition denoted as ,satisfy < , 0.03≤ ≤0.08, with a thickness range of 3nm~8nm;

[0013] Third sublayer: in contact with the channel layer, aluminum composition is denoted as... ,satisfy < And 0≤ ≤0.05; its thickness ranges from 2nm to 10nm;

[0014] Among them, in at least two sublayers, the difference in aluminum composition Δx between adjacent sublayers is not less than 0.02.

[0015] Furthermore, in this invention, the AND-gate GaN HEMT integrated device includes:

[0016] Substrate;

[0017] A buffer layer is located on the substrate;

[0018] A channel layer is located on the buffer layer;

[0019] A double-layer barrier structure is located on the GaN channel layer. The double-layer barrier structure includes: a lower gradient barrier layer located on the GaN channel layer, wherein the aluminum composition gradually increases in the direction away from the channel layer.

[0020] The upper main barrier layer is located on the lower graded barrier layer, and its aluminum composition is higher than the maximum aluminum composition of the lower graded barrier layer.

[0021] The ion implantation region penetrates the upper double barrier structure and extends into the lower channel layer;

[0022] The source and drain include a first source, a first drain, a second source, and a second drain; they penetrate the double-layer barrier structure, are located on the channel layer, and are spaced apart from each other;

[0023] The gate recess includes a first gate recess and a second gate recess, which penetrate the upper main barrier layer and extend into the lower gradient barrier layer.

[0024] The gate electrode includes a first gate, a second gate, and a third gate. The first gate and the second gate are located in the first gate groove and the second gate groove, respectively, and the third gate is in contact with the upper main barrier layer.

[0025] Furthermore, in this invention, the first source, the first drain, the second source, and the second drain are all made of metal or metal compound, and their contact type is ohmic contact.

[0026] Furthermore, in this invention, the first gate and the second gate are made of metal or metal compound, and their contact type is Schottky contact.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] (1) This invention achieves precise control of the threshold voltage from the material growth source by designing a lower gradient barrier layer or a stepped gradient barrier layer structure and combining it with the carrier compensation mechanism of the ion implantation region. It does not rely on the traditional gate trench dry etching process, completely avoiding the nanometer-level depth difference caused by uneven etching, so that the threshold voltage deviation of transistors in the logic array is controlled within ±50mV, the noise margin is improved by more than 40%, and the stringent requirements of large-scale digital integrated circuits are met.

[0029] (2) This invention fundamentally eliminates the physical damage to gallium nitride channels and the introduction of interface states by plasma by abandoning the dry etching process, reducing the threshold voltage drift rate with time and bias stress to below 0.1 mV / 1000 h. Simultaneously, the discrete aluminum composition design of the stepped gradient barrier layer further optimizes the interface band structure, reduces carrier trapping effects, and increases the circuit lifetime to 10... 6 With a lifespan exceeding 24 hours, its reliability meets industrial-grade application standards.

[0030] (3) This invention achieves monolithic integration of logic gate circuits through the modular integration design of depletion-type and enhancement-type HEMT devices. Precise control of the threshold voltage reduces the leakage current of the depletion-type device to 10% in the off-state. -12 On the order of A, static power consumption is reduced by more than 85% compared to traditional structures. At the same time, OR gates and AND gates can be fabricated through a single epitaxial growth and standardized process, increasing chip area utilization by 30% and reducing manufacturing costs by 25%. Attached Figure Description

[0031] Figure 1 This is an OR gate circuit diagram provided in an embodiment of the present invention;

[0032] Figure 2 This is an AND gate circuit diagram provided in an embodiment of the present invention;

[0033] Figure 3 This is a structural diagram of a NOT gate device provided in Embodiment 1 of the present invention;

[0034] Figure 4 This is a structural diagram of a NAND gate device provided in Embodiment 1 of the present invention;

[0035] Figure 5 This is a structural diagram of a NOR gate device provided in Embodiment 1 of the present invention;

[0036] Figure 6 This is a structural diagram of a NOT gate device provided in Embodiment 2 of the present invention.

[0037] The names corresponding to the reference numerals in the attached figures are as follows:

[0038] 101: Substrate; 102: Buffer layer; 103: Channel layer; 104: Lower gradient barrier layer; 105: Upper main barrier layer; 106: Ion implantation region; 107: First source; 108: First drain; 109: Second source; 110: Second drain; 111: Gate trench; 111-1: First gate trench; 111-2: Second gate trench; 112: First gate; 113: Second gate; 114: Third gate; 304: Stepped gradient barrier layer. Detailed Implementation

[0039] The present invention will be further described below with reference to the accompanying drawings and embodiments. The embodiments of the present invention include, but are not limited to, the following embodiments.

[0040] Example 1

[0041] This invention discloses a logic circuit based on high electron mobility transistors (HMTs). The logic circuit comprises an OR gate and an AND gate. The OR gate is composed of a combination of NOR gates and NOT gates, and the AND gate is composed of a combination of NAND gates and NOT gates. The NOR gate is a first integrated device consisting of a depletion-mode HEMT device and a parallel branch containing at least two enhancement-mode HEMT devices. The NAND gate is a second integrated device consisting of a depletion-mode HEMT device and a series branch containing at least two enhancement-mode HEMT devices. The NOT gate is a third integrated device consisting of a depletion-mode HEMT device and an enhancement-mode HEMT device connected in parallel. The first and third integrated devices are combined to form an OR gate GaN HEMT integrated device, and the second and third integrated devices are combined to form an AND gate GaN HEMT integrated device.

[0042] See Figure 1 The OR gate circuit works by combining a NOR gate and a NOT gate to achieve the OR logic function. The circuit consists of two main parts: the left-side NOR gate is composed of two enhancement-mode HEMTs connected in parallel, and then a depletion-mode HEMT (equivalent to a resistor) connected in series. The two pins at the top left of the circuit are input 1 (In1) and input 2 (In2), respectively. The outputs (drains) of the two parallel HEMTs are connected to the input of the right-side NOT gate. The right-side NOT gate is a basic inverting circuit consisting of one enhancement-mode HEMT and one depletion-mode HEMT, receiving the output of the left-side NOR gate. The output pin (Out) is the final OR gate output. In the left-side part, the two HEMTs work in parallel to form a NOR gate, see [link to relevant documentation]. Figure 5 A HEMT is similar to a switch; it only conducts when there is a high-level signal at its input. The right-side NOT gate inverts the output of the left-side NOR gate, thus enabling the entire circuit to function as an OR gate.

[0043] See Figure 2, the working principle of the AND gate is to implement the logical function of the AND gate through the combination of "NAND + NOT". The circuit is divided into two main parts: The left part NAND gate consists of two enhancement-mode HEMTs connected in series, and then a depletion-mode HEMT (equivalent to a resistor) is connected in series. The two pins at the left end of the circuit are Input 1 (In1) and Input 2 (In2) respectively. The outputs of the two series-connected HEMTs are jointly connected to the input of the right NOT gate. The right part NOT gate consists of a basic inverter circuit composed of an enhancement-mode HEMT and a depletion-mode HEMT, receives the output of the left NAND gate, and the output pin (Out) is the final output of the AND gate. In the left part, the two HEMTs work in series to form a NAND gate. The HEMT is similar to a switch. Only when all input signals are at high level, the output is at high level. The right NOT gate inverts the output of the left NAND gate to make the whole circuit realize the function of the AND gate.

[0044] See Figure 3 , the NOT gate consists of an enhancement-mode HEMT and a depletion-mode HEMT, and its epitaxial structure includes a substrate 101, a buffer layer 102, a channel layer 103, a lower graded barrier layer 104 and an upper main barrier layer 105. There are ion implantation regions 106, the first source 107 and the first drain 108 of the enhancement-mode HEMT, the second source 109 and the second drain 110 of the depletion-mode HEMT, as well as a gate recess 111, a first gate 112 and a second gate 113 on the epitaxial layer.

[0045] Among them, the material of the substrate 101 may include sapphire, silicon carbide and silicon substrate.

[0046] The material of the buffer layer 102 may include any one or combination of AlN, AlGaN, InGaN and GaN, and the thickness range of the buffer layer 102 may include 1000 - 4000 nm.

[0047] The material of the channel layer 103 may include undoped GaN, and its thickness range may include 100 - 300 nm.

[0048] The material of the lower graded barrier layer 104 may include AlGaN, and its aluminum component linearly increases from a first value x1 at its interface with the channel layer 103 to a second value x2 at its interface with the upper main barrier layer 105. Among them, 0 ≤ x1 < x2 ≤ 0.15. For example, x1 can be 0 (starting from GaN), and x2 is 0.10. The total thickness of this layer is preferably 5 nm to 20 nm.

[0049] [[ID=2OB]]The material of the upper main barrier layer 105 may include AlGaN, and its aluminum component y must be greater than the aluminum component x2 at the top of the lower graded barrier layer 104, that is, y > x2, preferably y ≥ 0.20.

[0050] The ion implantation region 106 penetrates through the upper double-barrier structure and extends deep into the underlying channel layer 103 and even the buffer layer 102. The implanted ion species are preferably ions that can generate deep-level defects and compensate for the background conductivity of the material, such as boron ions, nitrogen ions, fluorine ions, argon ions, or combinations thereof. These ions can form stable defect centers in the GaN lattice, capture carriers, thereby converting the implanted region into a high-resistance state.

[0051] The gate groove 111 extends to the lower graded barrier layer 104 by etching. The depth of the bottom of the groove (i.e., the aluminum composition value x_stop at the etching termination point, where x1 < x_stop < x2) is one of the core parameters determining the threshold voltage of the device. By designing the graded curve and controlling the etching end point, precise regulation of Vth can be achieved.

[0052] The materials of the first source 107, the first drain 108, the second source 109, and the second drain 110 can all include metals or metal compounds, and their contact type is ohmic contact.

[0053] The materials of the first gate 112 and the second gate 113 can include metals or metal compounds, and their contact type is Schottky contact. Exemplary materials of the metal or metal compound can include, for example but not limited to, Al, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, Si, metal alloys or their compounds, or other metal compounds.

[0054] See Figure 4 , this embodiment provides a NAND gate circuit using a dual-gate enhanced HEMT as a driving transistor. Using the grooved-gate HEMT with the lower graded barrier layer 104 as the core switching unit to achieve high-consistency and low-power logic functions. The dual-gate HEMT structure has a first gate groove 111-1, a second gate groove 111-2, and a third gate 114.

[0055] The embodiment of the present invention also provides a method for manufacturing a NOT gate and a NAND gate based on HEMT devices. By way of example and not limitation, this manufacturing method can be used to manufacture the above devices. This manufacturing method can include:

[0056] S501, Epitaxial Layer Growth: Metal-organic chemical vapor deposition (MOCVD) is used to sequentially grow a buffer layer, a channel layer, a lower gradient barrier layer, and an upper main barrier layer on the substrate. The key to achieving the gradient composition of the lower gradient barrier layer lies in the precise programmed control of the aluminum source (e.g., trimethylaluminum, TMAl) gas flow rate. During growth, the gas flow rate of TMAl is linearly increased, while the gas flow rate of the gallium source (e.g., trimethylgallium, TMGa) is adjusted accordingly to achieve a continuous and linear change in the aluminum composition from x1 to x2.

[0057] S502, Device Isolation: An isolation region window is opened using photolithography to expose the semiconductor surface to be implanted. A high-energy ion implanter is then used to implant specific ions into the exposed isolation region. The implanted ions penetrate the upper double-layer barrier structure and extend into the lower channel layer and even the buffer layer. The implantation energy range is typically 50keV to 500keV, and the implantation dose range is typically 1×10⁻⁶. 13 cm -2 Up to 1×10 15 cm -2 To further stabilize the isolation effect and repair surface damage caused by injection, rapid thermal annealing can be performed in an inert gas (such as nitrogen) atmosphere, with an annealing temperature range of 700°C to 900°C and a time range of 30 seconds to 5 minutes.

[0058] S503, Etching source and drain trenches: The source and drain trenches are defined using photolithography, and the trench areas are etched using ICP process, with the etching depth reaching the channel layer.

[0059] S504, Source and Drain Deposition: The source and drain regions are defined using photolithography. Then, ohmic contact metals for the source and drain are deposited using electron beam evaporation. The multilayer metal used, from bottom to top, is Ti / Al / Ni / Au, with thicknesses of 20 / 100 / 50 / 100 nm for Ti / Al / Ni / Au, respectively. The source and drain electrodes are formed through a lift-off process. Finally, the sample is placed in a nitrogen or oxygen atmosphere, with an annealing temperature of 400-800℃ and an annealing time of 30-200 s.

[0060] S505, Etching Gate Recess: A window is opened in a predetermined gate region using photolithography, exposing the surface of the underlying upper main barrier layer. A dry etching process is employed, using a mixed gas of Cl2, BCl3, and Ar as the etching gas to etch the exposed area. As the etching penetrates the upper main barrier layer, the etching rate gradually increases with decreasing aluminum composition in the Cl-based plasma, due to the gradual decrease in aluminum composition from x2 (e.g., 0.10) at the top to x1 (e.g., 0) at the bottom. Mass spectrometry endpoint detection is used to monitor the AlCl content in the etching byproducts. xThe trend of signal strength change. When AlCl x When the signal strength begins to decline significantly and continuously from a stable value, it indicates that the etching has penetrated into the gradient layer region where the aluminum composition is significantly reduced. After detecting the endpoint signal, the process does not stop immediately, but instead enters a "over-etching" step of a preset time to ensure that all residual, slower-etching, higher-aluminum-composition material within the gate window is completely removed, forming a flat bottom of the groove. The over-etching time can be precisely set according to the thickness and gradient of the gradient layer.

[0061] S506, Gate Deposition: The gate region is defined using photolithography. The sample is placed in an electron beam evaporation stage, and the vacuum level in the reaction chamber of the electron beam evaporation stage reaches 5 × 10⁻⁶. -6 After the torsion process, gate metal Ni / Au is deposited in the gate and photoresist areas, with Ni / Au thicknesses of 50 / 100 nm, respectively.

[0062] Example 2

[0063] See Figure 6 Compared to Example 1, the lower gradient barrier layer 104 is replaced by a stepped gradient barrier layer 304, which is located above the channel layer 103. Its key feature is that its aluminum composition exhibits discrete, stepped abrupt changes along the growth direction, rather than a continuous gradient. This barrier layer is formed by stacking at least two AlGaN sublayers with different fixed aluminum compositions from top to bottom. From top to bottom (i.e., from near the upper main barrier layer 105 to near the channel layer 103), the aluminum composition decreases stepwise. This includes:

[0064] First sublayer (top layer): in contact with the upper main barrier layer 105. Aluminum composition is denoted as... 0.08≤ ≤0.15; its thickness ranges from 2nm to 5nm;

[0065] Second sublayer (intermediate layer): Aluminum composition denoted as ,satisfy < , 0.03≤ ≤0.08, with a thickness range of 3nm~8nm.

[0066] The third sublayer (bottom layer): in contact with the channel layer. The aluminum composition is denoted as... ,satisfy < And 0≤ ≤0.05; =0 indicates a pure GaN layer. The thickness can be from 2nm to 10nm. Among them, in at least two sublayers, the difference in aluminum composition Δx between adjacent sublayers is not less than 0.02.

[0067] The stepped gradient barrier layer 304 is grown using metal-organic chemical vapor deposition. After the Nth sublayer is grown, the TMAl gas flow is switched from the current set value to the target set value for the next sublayer in a stepwise manner within a short period of time, while the TMGa gas flow is adjusted to maintain a stable overall growth rate. The thickness of each sublayer is precisely controlled by controlling the growth time of each sublayer.

[0068] The steps of etching the gate groove include: sequentially etching the upper main barrier layer and the lower barrier layer containing at least three aluminum composition steps using a dry etching process; monitoring the etching by-product signal in real time during the etching of the lower barrier layer; determining the moment when the etching front crosses the interface of different composition steps based on at least two successively step-decreasing inflection points of the by-product signal; and performing over-etching for a preset duration after detecting the final signal inflection point representing the etching entering the lowest step, and then stopping the etching.

[0069] The above embodiments are merely one of the preferred embodiments of the present invention and should not be used to limit the scope of protection of the present invention. Any modifications or refinements made to the main design concept and spirit of the present invention that are not of substantial significance, but solve the same technical problem as the present invention, should be included within the scope of protection of the present invention.

Claims

1. A logic circuit based on a high electron mobility transistor, wherein the logic circuit comprises an OR gate and an AND gate, the OR gate being composed of a NOR gate and a NOT gate, and the AND gate being composed of a NAND gate and a NOT gate, characterized in that, The NOR gate is a first integrated device consisting of a depletion-mode HEMT device and a parallel branch containing at least two enhancement-mode HEMT devices; the NAND gate is a second integrated device consisting of a depletion-mode HEMT device and a series branch containing at least two enhancement-mode HEMT devices; the NOT gate is a third integrated device consisting of a depletion-mode HEMT device and an enhancement-mode HEMT device connected in parallel; the first and third integrated devices are combined to form an OR gate GaN HEMT integrated device; the second and third integrated devices are combined to form an AND gate GaN HEMT integrated device.

2. The logic circuit based on a high electron mobility transistor according to claim 1, characterized in that, The third integrated device includes an epitaxial structure consisting of a substrate (101), a buffer layer (102), a channel layer (103), a lower gradient barrier layer (104), and an upper main barrier layer (105) stacked sequentially from bottom to top, as well as an ion implantation region (106), a first source (107), a first drain (108), a second source (109), a second drain (110), a gate recess (111), a first gate (112), and a second gate disposed on the epitaxial structure. The gate (113) is a gate with an ion implantation region (106) that penetrates the lower gradient barrier layer (104) and the upper main barrier layer (105) and extends into the lower channel layer (103) or buffer layer (102). The gate groove (111) extends to the lower gradient barrier layer (104) by etching. The bottoms of the first source (107), the first drain (108), the second source (109), and the second drain (110) are all in contact with the upper end of the channel layer (103).

3. A logic circuit based on a high electron mobility transistor according to claim 1, characterized in that, The third integrated device includes an epitaxial structure consisting of a substrate (101), a buffer layer (102), a channel layer (103), a stepped gradient barrier layer (304), and an upper main barrier layer (105) stacked sequentially from bottom to top, and an ion implantation region (106), a first source (107), a first drain (108), a second source (109), a second drain (110), a gate recess (111), a first gate (112), and a second gate (113) disposed on the epitaxial structure; wherein, the ion implantation region (106) The gate groove (111) extends to the stepped barrier layer (304) and the upper main barrier layer (105) through the upper step gradient barrier layer (304) and into the lower channel layer (103) or buffer layer (102); the gate groove (111) extends to the stepped barrier layer (304) through etching; the bottoms of the first source (107), the first drain (108), the second source (109), and the second drain (110) are all in contact with the upper end of the channel layer (103); wherein, the aluminum composition in the stepped barrier layer (304) exhibits discrete step transitions along the growth direction.

4. A logic circuit based on a high electron mobility transistor according to claim 3, characterized in that, The stepped gradient barrier layer (304) includes: First sublayer: in contact with the upper main barrier layer (105); aluminum composition is denoted as 0.08≤ ≤0.15; its thickness ranges from 2nm to 5nm; Second sublayer: Aluminum composition denoted as ,satisfy < , 0.03≤ ≤0.08, with a thickness range of 3nm~8nm; Third sublayer: in contact with the channel layer, aluminum composition is denoted as... ,satisfy < And 0≤ ≤0.05; its thickness ranges from 2nm to 10nm; Among them, in at least two sublayers, the difference in aluminum composition Δx between adjacent sublayers is not less than 0.

02.

5. A logic circuit based on a high electron mobility transistor according to claim 1, characterized in that, The AND-gate GaN HEMT integrated device includes: Substrate (101); A buffer layer (102) is located on the substrate (101); The channel layer (103) is located on the buffer layer (102); A double-layer barrier structure is located on the GaN channel layer (103). The double-layer barrier structure includes a lower gradient barrier layer (104) located on the GaN channel layer (103), wherein the aluminum composition gradually increases in the direction away from the channel layer (103). The upper main barrier layer (105) is located on the lower gradient barrier layer (104), and its aluminum composition is higher than the maximum aluminum composition of the lower gradient barrier layer (104). The ion implantation region (106) penetrates the upper double barrier structure and extends into the lower channel layer (103); The source and drain include a first source (107), a first drain (108), a second source (109), and a second drain (110); they penetrate the double-layer barrier structure and are located on the channel layer (103) and spaced apart from each other; The gate recess, including a first gate recess (111-1) and a second gate recess (111-2), penetrates the upper main barrier layer (105) and extends into the lower gradient barrier layer (104); The gate electrode includes a first gate (112), a second gate (113), and a third gate (114). The first gate (112) and the second gate (113) are located in the first gate groove (111-1) and the second gate groove (111-2), respectively, and the third gate (114) is in contact with the upper main barrier layer (105).

6. A logic circuit based on a high electron mobility transistor according to any one of claims 2, 3, or 5, characterized in that, The first source (107), the first drain (108), the second source (109), and the second drain (110) are all made of metal or metal compound, and their contact type is ohmic contact.

7. A logic circuit based on a high electron mobility transistor according to any one of claims 2, 3, or 5, characterized in that, The first gate (112) and the second gate (113) are made of metal or metal compound and their contact type is Schottky contact.

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