A high power density transistor and its fabrication method
By employing an innovative structure with thin and thick base regions in the transistor, the contact area between the base and collector regions is increased, overcoming the limitations of traditional transistors in improving power density, achieving higher current density and power density, and reducing the base-collector saturation voltage.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- YANGZHOU YANGJIE ELECTRONIC TECH CO LTD
- Filing Date
- 2026-04-22
- Publication Date
- 2026-07-14
AI Technical Summary
Existing transistors have limitations in improving power density. The emitter doping concentration, base thickness, and area parameters of traditional structures are basically fixed, making it difficult to further improve current density and power density.
An innovative structure is adopted, in which a thin base region and a thick base region are prepared by two injections respectively. The emitter region is prepared in the thick base region and the base electrode is prepared on the thin base region. This reduces carrier recombination, increases the contact area between the base and the collector region, and improves the current density per unit area.
With the same device area, the power density is increased by 10%-20%, and the base-collector saturation voltage is reduced, thereby improving the current gain and energy efficiency of the transistor.
Smart Images
Figure CN122395972A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a high power density transistor and its fabrication method. Background Technology
[0002] In the field of power electronic device technology, transistors are a commonly used semiconductor device, often used in switching circuits and amplifier circuits. As the power density requirements of power electronic device applications become increasingly higher, the development of high power density transistors has always been an industry trend.
[0003] Current density refers to the intensity of current flowing per unit area. In transistors, it typically refers to the amount of current carried per unit area of the collector or emitter. The formula is current density = current / area (units are amperes per square decimeter or amperes per square millimeter). Increasing the current density per unit area means handling a higher current per unit area of the transistor, which directly improves the power density (power handled per unit volume or unit area), which is crucial for optimizing transistor performance. Its significance is mainly reflected in the following aspects: 1. Improve current gain and amplification efficiency: Increasing current density allows the transistor to collect more charge carriers (such as electrons or holes) in the same area, thereby enhancing current gain (β value), improving amplification performance, and making signal processing more efficient.
[0004] 2. Reduce collector resistance and power consumption: Higher current density reduces the internal resistance of the collector, reduces voltage drop and conduction loss caused by resistance, and allows more power supply voltage to be effectively used for amplification, improving overall energy efficiency.
[0005] Currently, the main technologies for increasing the power density of transistors are achieved through the following core methods: 1. Increase the doping concentration in the emitter region to improve the emitter injection efficiency and increase the power density of the transistor; 2. Reduce the thickness of the base region to decrease carrier recombination in the base region and increase the power density of the transistor; 3. Increase the emitter area, thereby improving the emitter injection efficiency and increasing the power density of the transistor; While the above methods can improve the power density of transistors, for transistors, the higher the emitter doping concentration, the higher the transistor turn-on voltage. Therefore, the emitter doping concentration parameters of transistors in different application scenarios are basically fixed. Regarding reducing the base thickness, the base thickness and doping concentration parameters below the emitter region of transistors in different application scenarios are basically fixed. Regarding increasing the emitter area, it will reduce the base area per unit area, affecting other electrical parameters of the transistor. Therefore, for traditional structure transistors, the emitter doping concentration, base thickness, and emitter area are basically fixed once the application scenario is determined.
[0006] Therefore, adopting a new transistor structure is an effective way to improve the power density of transistors. This case starts with an innovative transistor structure, which prepares a thin base region and a thick base region through two injections. The emitter region is prepared in the thick base region, and the base electrode is prepared on the thin base region. Compared with the traditional structure, the thickness of the base region on both sides of the emitter region is reduced, which reduces the recombination of charge carriers in the base region on both sides of the emitter region, thereby improving the power density of the transistor. In addition, compared with the traditional structure, the contact area between the base region and the collector region is larger, which improves the efficiency of the collector region in collecting charge carriers. Based on the same area, the current density and power density per unit area of the transistor are increased. Summary of the Invention
[0007] To address the above problems, this invention provides a high-power-density transistor and its fabrication method that increases the current density per unit area and reduces the base-collector saturation voltage while improving power density within the same device area.
[0008] The technical solution of this invention is: A high power density transistor and its fabrication method, comprising the following steps: Step S100: Prepare a first heavily doped thin base region in the epitaxial wafer, and prepare a first heavily doped thick base region in the first heavily doped thin base region. Step S200: Prepare a second doped emitter region within the first doped thick base region; Step S300: Prepare a first isolation layer on the epitaxial wafer, and open windows at the first heavily doped thin base region and the first heavily doped thick base region to prepare the base electrode; In step S400, a window is opened in the second doped emitter region to prepare the emitter electrode; Step S500: Prepare a collector electrode on the back side of the epitaxial wafer.
[0009] Specifically, step S100 includes: Step S110: Using photolithography, a mask is used to protect the outer region of the first heavily doped thin base region; the first heavily doped thin base region is formed by diffusion or ion implantation. Step S120: Using photolithography, a mask is used to protect the outer region of the first heavily doped thick base region; the first heavily doped thick base region is formed by diffusion or ion implantation.
[0010] Specifically, in step S100, the first heavily doped thick base region is formed within the first heavily doped thin base region using a self-aligned process.
[0011] Specifically, step S200 includes: Step S210: Using photolithography, a mask is used to protect the outer region of the second doped emitter region; the second doped emitter region is formed by diffusion or ion implantation.
[0012] Specifically, step S300 includes: Step S310: The first isolation layer is prepared by chemical vapor deposition, and the outer area of the base electrode is protected by photolithography using a mask and etched to open the window. Step S320: Use a stripping or etching process to prepare the base electrode at the window opening.
[0013] Specifically, step S400 includes: Step S410: Using photolithography, a mask is used to protect the outer area of the emitter electrode, and an etching process is used to open a window. Step S420: Use a stripping or etching process to prepare an emitter electrode at the window opening.
[0014] Specifically, step S500 includes: Step S510: Thin the epitaxial wafer using a thinning process, and fabricate a collector electrode on the back side of the epitaxial wafer using a sputtering or deposition process.
[0015] A high power density transistor includes a collector electrode, an epitaxial wafer, and a first isolation layer arranged sequentially from bottom to top. The epitaxial wafer is provided with: The first doped thick base region extends downward from the top surface of the epitaxial wafer; The first heavily doped thin base region is provided in several parts, which extend downward from the top surface of the epitaxial wafer and are connected to the first heavily doped thick base region; the depth (Z direction) of the first heavily doped thin base region is less than the depth of the first heavily doped thick base region. The second doped emitter region is provided in several forms, which extend downward from the top surface of the first doped thick base region and are spaced apart from the bottom of the first doped thick base region. A first isolation layer is deposited on the top surface of the epitaxial wafer; The base electrode has several portions, which extend downward from the top of the first isolation layer, and are respectively connected to the first heavily doped thin base region and the first heavily doped thick base region at their bottom, and form ohmic contact with the first heavily doped thin base region and the first heavily doped thick base region. The emitter electrode is provided in several parts, which are located on the side of the base electrode, extend downward from the top surface of the first isolation layer, connect with the second heavily doped emitter region, and form a good ohmic contact with the second heavily doped emitter region.
[0016] Specifically, the thickness of the first heavily doped thick base region is greater than that of the first heavily doped thin base region.
[0017] Specifically, the first heavily doped thick base region and the first heavily doped thin base region are connected.
[0018] Beneficial effects of this invention: This invention employs an innovative structure to fabricate a thin base region and a thick base region through two separate injection processes. The emitter region is fabricated within the thick base region, while the base electrode is fabricated on the thin base region. Compared to traditional structures, this reduces the thickness of the base regions on both sides of the emitter region, thereby reducing carrier recombination and increasing the unit current density. Simultaneously, this innovative structure increases the area of the base region and collector region junction below the base electrode. The height difference between the thin and thick base regions allows the side of the thick base region to contact the collector region, further increasing the area of the base region and collector region junction. This, in turn, increases the number of carriers collected in the base region by the collector region, thereby increasing the unit area current density and improving the power density. Attached Figure Description
[0019] Figure 1 This is a process flow diagram of the present invention; Figure 2 This is a top view schematic diagram of the fabrication of the first-doped thin base region; Figure 3 This is a top view schematic diagram of the fabrication of the first-layer doped thick-base region; Figure 4 This is a top view schematic diagram of the fabrication of the second-doped emitter region; Figure 5 This is a schematic diagram of the fabrication of the second-doped emitter region along the X1 cross section; Figure 6 This is a schematic diagram of the fabrication of the second-doped emitter region along the X2 cross section; Figure 7 This is a top view schematic diagram of the fabrication of the first isolation layer, base electrode, and emitter electrode; Figure 8 This is a schematic diagram of the fabrication of the base electrode and emitter electrode along the X1 cross section; Figure 9 This is a schematic diagram of the fabrication of the base electrode and emitter electrode along the X2 cross section; Figure 10 This is a schematic diagram of the cross-sectional structure of the current collector electrode; In the figure, 1 is the epitaxial wafer, 2 is the first heavily doped thin base region, 3 is the first heavily doped thick base region, 4 is the second heavily doped emitter region, 5 is the first isolation layer, 6 is the base electrode, 7 is the emitter electrode, and 8 is the collector electrode. Detailed Implementation
[0020] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.
[0021] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0022] The following is for reference. Figure 1-10 Describe the present invention; A method for fabricating a high power density transistor includes the following steps: Step S100: A first heavily doped thin base region 2 is prepared within the epitaxial wafer 1, and a first heavily doped thick base region 3 is prepared within the first heavily doped thin base region 2, as shown in the figure. Figure 2-3 As shown; Step S110: Using photolithography, a mask is used to protect the outer region of the first heavily doped thin base region 2; the first heavily doped thin base region 2 is formed by diffusion or ion implantation. In step S120, the outer region of the first heavily doped thick base region 3 is protected using a photolithography process and a mask; the first heavily doped thick base region 3 is formed by a diffusion process or an ion implantation process.
[0023] Accordingly, the first and second doped regions are either P-regions or N-regions with opposite doping charges. The thickness of epitaxial wafer 1 is 100-2000 μm, the thickness of the first heavily doped thin base region 2 is set to 0.5-20 μm, the thickness of the first heavily doped thick base region 3 is set to 1-50 μm, and the doping concentration range of N-type doping is 1e. 14 .cm -3 -1e 20 .cm -3 The doping concentration range for P-type doping is 1e 15 .cm -3 -1e 20 .cm -3 The relevant parameter settings are related to the electrical design of the device; In this embodiment, the first doped region is a P-region, the second doped region is an N-region, and the thickness of the epitaxial wafer 1 is 350 μm; the thickness of the first heavily doped thin base region 2 is 1 μm, and the doping concentration is 1e. 16 .cm -3 The first doped thick base region 3 has a thickness of 5 μm and a doping concentration of 1e. 16 .cm -3 The first heavily doped thin base region 2 and the first heavily doped thick base region 3 were prepared using ion implantation.
[0024] Step S200: Prepare a second heavily doped emitter region 4 within the first heavily doped thick base region 3, referring to... Figure 4-6 As shown; In step S210, the outer region of the second heavily doped emission region 4 is protected by a mask using photolithography; the second heavily doped emission region 4 is formed by diffusion or ion implantation.
[0025] Accordingly, the thickness of the second doped emitter region 4 is set to 0.5-49 μm; In this embodiment, the thickness of the second doped emitter region 4 is set to 3 μm, and the doping concentration is 1e. 19. cm -3 .
[0026] Step S300: A first isolation layer 5 is prepared on the epitaxial wafer 1. Windows are opened at the first heavily doped thin base region 2 and the first heavily doped thick base region 3 to prepare the base electrode 6, as shown in the figure. Figure 7-10 As shown; Step S310: Prepare the first isolation layer 5 by chemical vapor deposition, protect the external area of the base electrode 6 by photolithography using a mask, and open the window by etching. In step S320, the base electrode 6 is prepared at the window using a stripping or etching process.
[0027] Correspondingly, the first isolation layer 5 serves a protective function. It is made of SiO2 or Si3N4 and has a thickness of 10-5000nm. It uses ICP dry etching to create a window. The window extends from the top surface of the first isolation layer 5 downward into the first heavily doped thin base region 2 and the first heavily doped thick base region 3. The base electrode 6 contacts the first heavily doped thin base region 2 and the first heavily doped thick base region 3 to form an ohmic contact. The relevant parameter settings are related to the electrical design of the device. In this embodiment, Si3N4 is used as the first isolation layer 5 with a thickness of 200nm. ICP dry etching is used to create a window with a depth of 200nm. A 200nm thick Ti / Al two-layer metal is prepared as the base electrode 6 using a local heavy doping remetallization process and a lift-off process.
[0028] Step S400: A window is opened in the second heavily doped emitter region 4 to prepare the emitter electrode 7, as per [reference]. Figure 7-10 As shown; Step S410: Using photolithography, a mask is used to protect the external area of the emitter electrode 7, and an etching process is used to open a window. Step S420: Using a stripping or etching process, prepare the emitter electrode 7 at the window opening; Accordingly, ICP dry etching is used to create a window that extends downward from the top of the first isolation layer 7 into the interior of the second heavily doped emitter region 4. The emitter electrode 7 contacts the second heavily doped emitter region 4 to form an ohmic contact. The relevant parameter settings are related to the electrical design of the device. In this embodiment, ICP dry etching is used to create a window with a depth of 200 nm. A 200 nm thick Ti / Al double metal layer is then prepared as the emitter electrode 7 using a lift-off process.
[0029] Step S500: Fabricate collector electrode 8 on the back side of the epitaxial wafer, referring to... Figure 10 As shown.
[0030] Correspondingly, the epitaxial wafer 1 is thinned to the corresponding thickness through a thinning process, and the collector electrode 8 is prepared on the back side of the epitaxial wafer using a deposition process or a sputtering process; In this embodiment, a thinning process is used to reduce the thickness of the 350µm epitaxial wafer 1 to 180µm, and a deposition process is used to prepare a 1µm thick Ti / Al as the collector electrode 8.
[0031] A high power density transistor includes a collector electrode 8, an epitaxial wafer 1, and a first isolation layer 5 arranged sequentially from bottom to top. The epitaxial wafer 1 is provided with: The first heavily doped thick base region 3 extends downward from the top surface of the epitaxial wafer 1; The first heavily doped thin base region 2 is provided in several parts, which extend downward from the top surface of the epitaxial wafer 1 and are connected to the first heavily doped thick base region 3; the depth (Z direction) of the first heavily doped thin base region 2 is less than the depth of the first heavily doped thick base region 3. The second doped emitter region 4 is provided in several parts, which extend downward from the top surface of the first doped thick base region 3 and are spaced apart from the bottom of the first doped thick base region 3. The first isolation layer 5 is deposited on the top surface of the epitaxial wafer 1; The base electrode 6 is provided with several electrodes that extend downward from the top surface of the first isolation layer 5, and are respectively connected to the first heavily doped thin base region 2 and the first heavily doped thick base region 3 at their bottom, and form ohmic contact with the first heavily doped thin base region 2 and the first heavily doped thick base region 3. Emitter electrodes 7 are provided in several portions, each located on the side of the base electrode 6, extending downward from the top surface of the first isolation layer 5, and connected to the second heavily doped emitter region 4, forming a good ohmic contact with the second heavily doped emitter region 4.
[0032] The thickness of the first heavily doped thick base region 3 is greater than that of the first heavily doped thin base region 2.
[0033] The first heavily doped thick base region 3 and the first heavily doped thin base region 2 are connected.
[0034] This invention addresses the issue of improving the power density of transistors by providing a method for fabricating high-power-density transistors. This method increases the area of the junction between the base region and the collector region through an innovative structure, thereby increasing the number of charge carriers collected in the base region by the collector region. This increases the current density per unit area under the same device area, thereby improving the power density by 10%-20% under the same device area.
[0035] Regarding the information disclosed in this case, the following points need to be clarified: The accompanying drawings of the embodiments disclosed in this case only relate to the structures involved in the embodiments disclosed in this case; other structures can be referred to with ordinary designs. Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments; The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.
Claims
1. A high power density transistor and its fabrication method, characterized in that, Includes the following steps: Step S100: Prepare a first heavily doped thin base region (2) in the epitaxial wafer (1), and prepare a first heavily doped thick base region (3) in the region of the first heavily doped thin base region (2). Step S200: Prepare a second doped emitter region (4) within the first heavily doped thick base region (3); Step S300: Prepare a first isolation layer (5) on the epitaxial wafer (1), and open windows at the first heavily doped thin base region (2) and the first heavily doped thick base region (3) to prepare a base electrode (6). In step S400, a window is opened in the second heavily doped emission region (4) to prepare the emitter electrode (7). Step S500: Prepare a collector electrode (8) on the back side of the epitaxial wafer.
2. The method for fabricating a high power density transistor according to claim 1, characterized in that, Step S100 includes: Step S110: Using photolithography, a mask is used to protect the outer region of the first heavily doped thin base region (2); the first heavily doped thin base region (2) is formed by diffusion or ion implantation. Step S120: Using photolithography, a mask is used to protect the outer region of the first heavily doped thick base region (3); the first heavily doped thick base region (3) is formed by diffusion or ion implantation.
3. The method for fabricating a high power density transistor according to claim 1, characterized in that, In step S100, the first heavily doped thick base region (3) is formed in the region of the first heavily doped thin base region (2) using a self-aligned process.
4. The method for fabricating a high power density transistor according to claim 1, characterized in that, Step S200 includes: Step S210: Using photolithography, a mask is used to protect the outer region of the second doped emission region (4); the second doped emission region (4) is formed by diffusion or ion implantation.
5. The method for fabricating a high power density transistor according to claim 1, characterized in that, Step S300 includes: Step S310: Prepare the first isolation layer (5) by chemical vapor deposition, protect the outer area of the base electrode (6) by photolithography using a mask, and open the window by etching. Step S320: Use a stripping process or an etching process to prepare the base electrode (6) at the window opening.
6. The method for fabricating a high power density transistor according to claim 1, characterized in that, Step S400 includes: Step S410: Using photolithography, a mask is used to protect the external area of the emitter electrode (7), and an etching process is used to open the window. Step S420: Use a stripping process or an etching process to prepare an emitter electrode (7) at the window opening.
7. The method for fabricating a high power density transistor according to claim 1, characterized in that, Step S500 includes: Step S510: Thin the epitaxial wafer using a thinning process, and prepare a collector electrode (8) on the back side of the epitaxial wafer using a sputtering or deposition process.
8. A high power density transistor, fabricated by the method for fabricating a high power density transistor according to claim 1, characterized in that, It includes a collector electrode (8), an epitaxial wafer (1) and a first isolation layer (5) arranged sequentially from bottom to top; The epitaxial wafer (1) is provided with: The first heavily doped thick base region (3) extends downward from the top surface of the epitaxial wafer (1); The first heavily doped thin base region (2) is provided in several parts, which extend downward from the top surface of the epitaxial wafer (1) and are connected to the first heavily doped thick base region (3); the depth (Z direction) of the first heavily doped thin base region (2) is less than the depth of the first heavily doped thick base region (3); The second doped emitter region (4) is provided in several parts, which extend downward from the top surface of the first doped thick base region (3) and are spaced apart from the bottom of the first doped thick base region (3); A first isolation layer (5) is deposited on the top surface of the epitaxial wafer (1); The base electrode (6) is provided with several electrodes that extend downward from the top surface of the first isolation layer (5) and are connected to the bottom of the first heavily doped thin base region (2) and the first heavily doped thick base region (3) respectively, and form an ohmic contact with the first heavily doped thin base region (2) and the first heavily doped thick base region (3); The emitter electrode (7) is provided in several parts, which are located on the side of the base electrode (6), extend downward from the top surface of the first isolation layer (5), connect with the second heavily doped emitter region (4), and form a good ohmic contact with the second heavily doped emitter region (4).
9. A high power density transistor according to claim 7, characterized in that, The thickness of the first heavily doped thick base region (3) is greater than that of the first heavily doped thin base region (2).
10. A high power density transistor according to claim 7, characterized in that, The first heavily doped thick base region (3) and the first heavily doped thin base region (2) are connected.