A trench NMOS device, a preparation method and application of MOS device

Abstract

The application discloses a trench type NMOS device, a preparation method and application of a MOS device. The preparation method of the trench type NMOS device comprises the following steps: S11, forming a first trench on a substrate; S12, sequentially forming a buffer layer and an N channel layer of the NMOS device in the first trench, the electron mobility of the N channel layer is greater than that of the substrate, and the lattice constants of the substrate, the buffer layer and the N channel layer are sequentially increased; and S13, preparing a gate, a source and a drain of the NMOS device. The trench type NMOS device is mainly designed and optimized for the channel of a MOSFET chip. The lattice mismatch and thermal expansion of the substrate and the channel layer can be relieved through the arrangement of the buffer layer, meanwhile, the switching frequency of the device can be remarkably improved, and the device is suitable for advanced processes.

Description

Technical Field

[0001] This invention belongs to the field of chip process technology, specifically relating to a trench-type NMOS device, a method for fabricating a MOS device, and its application. Background Technology

[0002] Silicon (Si) MOSFETs (metal-oxide-semiconductor field-effect transistors) are suitable for advanced processes (such as below 5nm). To compensate for the short-channel effect, improved mobility is needed. Replacing Si with a material with a higher carrier velocity can significantly improve the switching frequency of the device, offering advantages in low power consumption and high-frequency performance. Silicon-based semiconductor processes are very mature. After decades of development, there is comprehensive technology and equipment support for all aspects, from crystal growth and wafer fabrication to device packaging. This makes the manufacturing cost of silicon-channel MOSFETs relatively low and the yield rate high. For example, in integrated circuit manufacturing, the diameter of silicon wafers can reach 300mm or even larger, enabling large-scale chip production and effectively controlling the unit chip cost. Silicon has good thermal conductivity, which is beneficial for heat dissipation during device operation. In power MOSFETs, good heat dissipation performance can ensure the relative stability of the device under high-power operation, reducing the risk of performance degradation or damage due to temperature rise. Silicon materials can achieve high voltage withstand levels through appropriate doping and structural design. For some applications that require high voltage withstand, such as high voltage DC transmission and motor drive in power electronics, silicon channel MOSFETs can meet the voltage withstand requirements by increasing the width of the drift region.

[0003] Silicon channel MOSFETs also have the following disadvantages: 1. Low electron mobility: The electron mobility of silicon is relatively low, approximately 1350 cm⁻¹. 2 The low electron mobility (V·s) limits the performance of silicon-channel MOSFETs in high-frequency, high-speed applications. In high-frequency signal processing or high-speed switching circuits, the lower electron mobility results in insufficient switching speed and increased signal transmission delay. 2. Limited optoelectronic performance: Silicon has relatively weak light absorption, and its photoelectric conversion efficiency is lower than some III-V semiconductor materials in certain wavelength ranges (such as the near-infrared band). Therefore, the performance of silicon-channel MOSFETs may be limited in optoelectronic devices or applications requiring optoelectronic integration. 3. Limited advanced process capability: Advanced processes require maintaining performance with shorter channel lengths, and silicon-channel MOSFETs are not suitable for advanced processes. Summary of the Invention

[0004] In view of all or part of the deficiencies of the prior art described above, the purpose of this invention is to provide a trench-type NMOS device and its fabrication method, a fabrication method and application of a trench-type MOS device. The trench-type NMOS device is mainly designed and optimized for the channel of MOSFET chips. By setting a buffer layer, the lattice mismatch and thermal expansion between the substrate and the channel layer can be alleviated, and the switching frequency of the device can be significantly improved, making it suitable for advanced processes.

[0005] To achieve the above-mentioned objectives, the present invention provides the following technical solution: This invention provides a method for fabricating a trench-type NMOS device, comprising the following steps: S11. Form a first trench on the substrate; S12. A buffer layer and an N-channel layer of an NMOS device are sequentially formed in the first trench. The electron mobility of the N-channel layer is greater than that of the substrate, and the lattice constants of the substrate, the buffer layer and the N-channel layer increase sequentially. S13. Prepare the gate, source, and drain of the NMOS device.

[0006] This invention forms trenches in a substrate and fills these trenches with an N-channel material. By selecting a material with a higher electron mobility than the substrate, such as silicon, as the N-channel material, the device switching frequency can be increased, operating voltage reduced, and power consumption decreased. This makes it more suitable for high-frequency applications than traditional silicon channels, allowing performance to be maintained at shorter channel lengths, and is suitable for advanced processes (e.g., below 5nm). Simultaneously, by placing a buffer layer between the substrate and the N-channel layer, the overall lattice constant of the buffer layer lies between that of the substrate and the N-channel layer, acting as a buffer and thus solving the problems of lattice mismatch and thermal expansion between the substrate and channel materials.

[0007] The substrate is made of silicon; the buffer layer is made of Si. X Ge 1-x Layer, wherein 0≤x≤1; the N-channel layer is In y Ga 1-y As layer, where 0 ≤ y ≤ 1. In y Ga 1-y The As layer has a high electron mobility, for example, the electron mobility of In with a high In content. 0.53 Ga 0.47 As has an electron mobility 7-10 times that of silicon, which can significantly improve the switching frequency of devices. Meanwhile, germanium has a lattice constant similar to that of gallium arsenide (GaAs), so using a silicon-germanium buffer layer can alleviate the interaction between the silicon substrate and the N-channel In layer. y Ga 1-y Lattice mismatch and thermal expansion between As.

[0008] The SiX Ge 1-x The layer includes a first component gradient layer, wherein x varies with Si X Ge 1-x The deposition process gradually decreases; the In y Ga 1-y The As layer includes a second component gradient layer, where y varies with In. y Ga 1-y The deposition process of As gradually increases. The buffer layer is set up to grow a higher quality indium gallium arsenide (IGaAs) layer. The lattice constants of the gradient components are matched using a first-component gradient layer and a second-component gradient layer, specifically matching the lattice constants of silicon, silicon germanium, and IGaAs. In the first-component gradient, the portion of the buffer layer closer to the substrate has a lower germanium content and a smaller lattice constant, closely matching the lattice constant of the substrate. Conversely, the portion of the buffer layer closer to the N-channel layer has a higher germanium content and a larger lattice constant, closely matching the lattice constant of the N-channel layer. In the second-component gradient, the portion of the N-channel layer closer to the buffer layer has a lower In content and a smaller lattice constant, closely matching the lattice constant of the buffer layer. Conversely, the portion of the N-channel layer closer to the gate layer has a higher In content and a larger lattice constant, closely matching the lattice constant of the buffer layer. y Ga 1-y As the In content increases, the lattice constant of the As layer increases, and the electron mobility increases accordingly. The final y value is controlled according to the desired electron mobility.

[0009] The Si X Ge 1-x The layer formation process includes: depositing Si in the first trench using a chemical vapor deposition process. X Ge 1-x The material is applied until it partially fills the first trench; germane (GeH4) and silane (SiH4) are used as the first reactant gases, and the ratio of the first reactant gases is used to control the gradual change of the first component, which can be linearly regulated or controlled by a fast-then-slow process. The deposition temperature is 550-750℃, and the pressure is less than 1×10⁻⁶. -5 Pa.

[0010] The In y Ga 1-y The formation process of the As layer includes: applying a physical vapor deposition (PVD) or chemical vapor deposition (CVD) process to the Si layer. X Ge 1-x In deposition on the surface of the layer y Ga 1-yAs material is used until the first trench is filled, followed by chemical mechanical polishing to expose the substrate surface; when molecular beam epitaxy (MBE) is used, the second component gradient is controlled by adjusting the electron beam current ratio of In, Ga, and As; or, when metal-organic chemical vapor deposition (MOCVD) is used, trimethylindium (TMIn), trimethylgallium (TMGa), and arsine (AsH3) are used as the second reactant gases, and the second component gradient is controlled by the ratio of the second reactant gases, either linearly or by a fast-then-slow adjustment, with a deposition temperature of 550-750℃ and a pressure less than 1×10⁻⁶. -5 Pa can be treated using UHV-CVD ultra-high vacuum chemical vapor deposition.

[0011] In step S13, the gate fabrication process includes: growing an oxide layer on the surface of the N-channel layer, depositing a gate material on the oxide layer, and selectively etching away the oxide layer and the gate material in a designated area using an etching process to form the gate; the source and drain fabrication processes include: in the In... y Ga 1-y Se in the non-gate region of the As layer + Si + or S + One or more ions are implanted, and after annealing, the source and drain regions of the NMOS device are formed.

[0012] The buffer layer further includes a first component fixing layer located between the first component gradient layer and the second component gradient layer, and the N-channel layer further includes a second component fixing layer located on the other side of the second component gradient layer; the silicon-germanium ratio of the first component fixing layer is fixed, and the InGa ratio of the second component fixing layer is fixed; the thickness of the first component gradient layer is 800-1000 nm, the thickness of the first component fixing layer is 80-120 nm, the thickness of the second component gradient layer is 50-300 nm, and the thickness of the second component fixing layer is 3-20 nm. Compared to setting multiple heterogeneous material layers with different lattice constants as buffer layers, this invention uses a component gradient method that does not require the formation of high aspect ratio trenches, reducing the process difficulty. Simultaneously, setting the first and second component fixing layers, with partial component fixation, can ensure the layer quality and process stability of the buffer layer and the N-channel layer.

[0013] The present invention also provides a trench-type NMOS device, which is prepared according to the above-described method for preparing a trench-type NMOS device.

[0014] This invention also provides a method for fabricating a trench-type MOS device, comprising the following steps: S21. Form a first trench and a second trench on the substrate; S22. Silicon-germanium material is grown in the first trench and the second trench, and the silicon-germanium material in the second trench serves as the P-channel layer of the PMOS device. S23. Remove part of the silicon-germanium material in the first trench and fill it with the N-channel layer of the NMOS device. The electron mobility of the N-channel layer is greater than that of the substrate. The lattice constants of the substrate, silicon-germanium material and N-channel layer increase in sequence. S24. Fabricate the gate, source, and drain of NMOS and PMOS devices.

[0015] Silicon-germanium material is grown simultaneously in the first and second trenches. The silicon-germanium material serves as a buffer layer in the first trench and also as the P-channel layer material in the second trench. By etching back the silicon-germanium material in the first trench (which may specifically include a first-component gradient layer and a first-component fixing layer), a portion of the silicon-germanium material is removed and filled with the N-channel layer material of the NMOS device. The removed silicon-germanium material may be the silicon-germanium material of the first-component fixing layer. The N-channel layer material filled in the first trench may include a second-component gradient layer and a second-component fixing layer. Excess second-component fixing layer in the first trench and excess silicon-germanium material (i.e., excess first-component fixing layer) in the second trench can be removed by grinding. This means the silicon-germanium material can grow beyond the depth of the first and second trenches. After grinding, a second trench is dug where N-channel layer material, such as InGaAs, needs to be grown, followed by InGaAs material growth. The P-channel layer material is silicon-germanium material. The P-channel layer of the PMOS device is formed in the second trench. The hole mobility of the P-channel layer is greater than that of the substrate, and the electron mobility of the N-channel layer is greater than that of the substrate, which can significantly improve the switching frequency of the device.

[0016] This invention involves forming trenches in a substrate and filling the trenches with N-channel and P-channel materials, respectively. By selecting a material with an electron mobility greater than that of the substrate, such as silicon, for the N-channel material, and a material with a hole mobility greater than that of the substrate, such as silicon, for the P-channel material, the device switching frequency can be increased, the operating voltage reduced, and power consumption decreased. This makes it more suitable for high-frequency applications than traditional silicon channels, allows performance to be maintained at shorter channel lengths, and is suitable for advanced processes (such as below 5nm).

[0017] The present invention also provides a method for fabricating a trench-type NMOS device, and / or the method for fabricating a trench-type MOS device, and its application in the fabrication of logic chips or memory chips. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic flowchart of a method for fabricating a trench-type NMOS device provided in Example 1; Figure 2 This is a schematic diagram of the formation of the first trench and buffer layer in Example 1; Figure 3 This is a schematic diagram of the formation of the channel layer, gate, source, and drain in Example 1; Figure 4 This is a schematic diagram of the structure of a trench-type NMOS device provided in Embodiment 2.

[0020] Reference numerals: 1-substrate; 10-first trench; 2-buffer layer; 3-N-channel layer; 4-gate; 5-source; 6-drain. Detailed Implementation

[0021] The technical solutions in specific embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] It should be noted that, in order to describe the technical solution more specifically, the steps described in the following embodiments do not strictly correspond one-to-one with the steps described in the invention content section. Example 1

[0023] A method for fabricating a trench-type NMOS device, referring to... Figures 1 to 3 This includes the following steps: S11. A first trench 10 is formed by etching on the substrate 1. In this embodiment, the material of the substrate 1 is silicon. In other embodiments, it can also be germanium, silicon-germanium, or silicon-on-insulator, etc.

[0024] S12. A buffer layer 2 is formed in the first trench 10. In this embodiment, the buffer layer 2 is Si. X Ge 1-x Layer, wherein 0≤x≤1, Si is deposited in the first trench 10 by chemical vapor deposition. X Ge 1-xThe material is applied until it fills at least partially the first trench 10, i.e., covering the bottom and sidewalls of the first trench 10. In this embodiment, the Si... X Ge 1-x The layer includes a first component gradient layer and a first component fixed layer, wherein x in the first component gradient layer varies with Si. X Ge 1-x The deposition process gradually decreases, with x decreasing from 1 to 0 or a smaller value. The silicon-germanium ratio of the first component fixed layer remains constant, i.e., x = 0 or a smaller value. Adjustable, the thickness of the first component gradient layer is 900 nm, and the thickness of the first component fixed layer is 100 nm. Methylgermanane and silane are used as the first reactant gases. The gradient of the first component is controlled by the ratio of the first reactant gases, allowing for linear or initial-fast-then-slow control. The deposition temperature is 550-750℃, and the pressure is less than 1 × 10⁻⁶. -5 Pa. Specifically, by controlling the surface composition to be relatively constant from fast to slow, the surface crystallization quality is improved. In this embodiment, UHV-CVD (ultra-high vacuum chemical vapor deposition) is used to grow the buffer layer 2.

[0025] An N-channel layer 3 for the NMOS device is further formed on the surface of the buffer layer 2, i.e., within the first trench 10. In this embodiment, the N-channel layer 3 is In... y Ga 1-y An As layer, wherein 0 ≤ y ≤ 1, is formed on the Si layer using either physical vapor deposition or chemical vapor deposition. X Ge 1-x In deposition on the surface of the layer y Ga 1-y As material, until the first groove 10 is completely filled, the In y Ga 1-y After the As layer is deposited, chemical mechanical polishing is performed to expose the surface of substrate 1, that is, to remove excess Si. X Ge 1-x and In y Ga 1-y As material is used to obtain the N-channel layer 3. In this embodiment, the In... y Ga 1-y The As layer includes a second component gradient layer and a second component fixed layer. In the second component gradient layer, y changes with In. y Ga 1-yThe deposition process of As gradually increases, and y gradually increases from 0 to the required ratio (adjusted according to the desired electron mobility). The InGa ratio of the second component fixed layer remains constant, for example, y=0.53. The thickness of the second component gradient layer is adjustable, ranging from 50-300 nm, and the thickness of the second component fixed layer is 3-20 nm. When using molecular beam epitaxy, the gradient of the second component is controlled by adjusting the electron beam current ratio of In, Ga, and As; or, when using organometallic chemical vapor deposition, trimethylindium, trimethylgallium, and arsenide are used as the second reactant gas, and the gradient of the second component is controlled by the ratio of the second reactant gas, allowing for linear or initial fast-then-slow adjustment. The deposition temperature is 550-750℃, and the pressure is less than 1×10⁻⁶. -5 Pa. Specifically, by controlling the surface composition to be relatively constant through a fast-then-slow approach, the surface crystallization quality is improved. In this embodiment, the N-channel layer 3 is grown using UHV-CVD (ultra-high vacuum chemical vapor deposition).

[0026] The present invention does not strictly limit the aspect ratio of the first trench 10, and it can be adjusted as needed. The depth of the first trench 10 is equal to the depth of the buffer layer 2 plus the depth of the N-channel layer 3. Further, the buffer layer 2 is a 900nm gradient layer (first component gradient layer) plus a 100nm high-quality buffer layer germanium layer (first component fixed layer) with a fixed silicon-germanium ratio, and the N-channel layer 3 is a 50-300nm gradient layer with varying In and Ga ratios (second component gradient layer) plus a 3-200nm high-quality channel layer In with a fixed In-Ga ratio. 0.53 Ga 0.47 As layer (second component fixation layer).

[0027] In other embodiments, the Si may also be used. X Ge 1-x After the layer deposition is completed, a first chemical mechanical polishing treatment is performed, and in the In y Ga 1-y After the As layer is deposited, a second chemical mechanical polishing treatment is performed.

[0028] In this embodiment, the electron mobility of the N-channel layer 3 is greater than that of the substrate 1, and the lattice constants of the substrate 1, buffer layer 2, and N-channel layer 3 increase sequentially (here referring to the overall lattice constants of the buffer layer 2 and the N-channel layer 3). The lattice constant of silicon is 5.431 Å, and that of germanium is 5.658 Å. In this embodiment, the buffer layer 2 comprises Si... X Ge 1-xThe buffer layer 2 is a germanium layer with a lattice constant that gradually changes from 5.431 to 5.658 Å and a fixed composition. The overall lattice constant of the buffer layer 2 is greater than 5.431 Å and less than 5.658 Å. The lattice constant of gallium arsenide is 5.653 Å. In this embodiment, the N-channel layer 3 is In... y Ga 1-y The lattice constant of the As (indium gallium arsenide) layer is 5.653-6.058 Å. This means that the overall lattice constant of the buffer layer 2 is between that of the substrate 1 and the N-channel layer 3, thus providing a buffering effect. At the interface between the buffer layer 2 and the N-channel layer 3, the lattice constants of germanium and gallium arsenide are very close, essentially identical. However, the electron mobility of the indium gallium arsenide material in the N-channel layer 3 is much greater than that of the silicon material in the substrate 1.

[0029] S13. Fabrication of the gate 4, source 5, and drain 6 of the NMOS device. The fabrication process of the gate 4 includes: growing an oxide layer (as a gate oxide layer) on the surface of the N-channel layer 3, depositing a gate material (such as polysilicon) on the oxide layer, and selectively etching away the oxide layer and the gate material in a designated area using an etching process to form the gate 4 (this also includes processes such as forming gate sidewalls, which are mature existing technologies and will not be described here). The fabrication process of the source 5 and drain 6 includes: on the In... y Ga 1-y Se is applied to the non-gate region of the As layer. + Si + or S + One or more ions are implanted, and after annealing, the source and drain regions of the NMOS device are formed, resulting in a trench NMOS device. Example 2

[0030] A trench-type NMOS device, see Figure 4 The device was fabricated according to the method provided in Example 1 for a trench-type NMOS device. It includes a silicon-germanium buffer layer 2 having a first component gradient layer and a first component fixation layer, and an indium gallium arsenide (IGaAs) N-channel layer 3 having a second component gradient layer and a second component fixation layer. Example 3

[0031] A method for fabricating a trench-type MOS device includes the following steps: S21. A first trench 10 and a second trench are formed on the substrate. In this embodiment, the substrate 1 is made of silicon; in other embodiments, it can also be germanium, silicon-germanium, or silicon-on-insulator, etc. The second trench can have the same morphology and dimensions as the first trench 10 in Embodiment 1.

[0032] S22. Silicon-germanium material is grown in the first trench 10 and the second trench, wherein the silicon-germanium material in the second trench serves as the P-channel layer of the PMOS device. In this embodiment, the silicon-germanium material may specifically include a first component gradient layer and a first component fixing layer, wherein the first component gradient layer is x-shaped as Si... X Ge 1-x The deposition process gradually decreases, with x decreasing from 1 to 0 or a smaller value. The silicon-germanium ratio of the first component fixing layer remains constant, i.e., x = 0 or a smaller value. Specifically, the silicon-germanium material is grown using UHV-CVD (ultra-high vacuum chemical vapor deposition). The silicon-germanium material fills the first trench 10 and the second trench, and a first chemical mechanical polishing treatment can be performed. The silicon-germanium material in the first trench 10 and the second trench may include a first component gradient layer or a first component gradient layer plus a portion of the first component fixing layer. In this embodiment, the silicon-germanium material in the first trench 10 and the second trench is a first component gradient layer plus a first component fixing layer, with the first component fixing layer serving as the surface layer, and the silicon-germanium material in the second trench serving as the material for the P-channel layer.

[0033] S23. A portion of the silicon-germanium material within the first trench 10 is removed, and the N-channel layer 3 of the NMOS device is filled in. The electron mobility of the N-channel layer 3 is greater than that of the substrate 1, and the lattice constants of the substrate 1, the silicon-germanium material, and the N-channel layer 3 increase sequentially. By etching back the silicon-germanium material filled within the first trench 10, a portion of the silicon-germanium material is removed, remaining within the first component fixing layer. The N-channel layer 3 continues to be formed on the first component fixing layer. Specifically, the N-channel layer 3 may include a second component gradient layer and a second component fixing layer. In the second component gradient layer, y increases with increasing In... y Ga 1-y The deposition process of As gradually increases, and y gradually increases from 0 to the required ratio (adjusted according to the desired electron mobility). The InGa ratio of the second component immobilization layer remains constant, for example, y=0.53. Specifically, UHV-CVD (ultra-high vacuum chemical vapor deposition) is used to deposit In... y Ga 1-y As material is grown, a second chemical mechanical polishing treatment can be performed to remove part of the material in the second component fixing layer. The thickness of each layer and the deposition process conditions are the same as in Example 1 and will not be repeated here.

[0034] S24. Fabricate the gate 4, source 5, and drain 6 of an NMOS device, and fabricate the gate, source, and drain of a PMOS device. The fabrication process of the gate 4 includes: growing an oxide layer (as a gate oxide layer) on the surface of the N-channel layer 3 and the P-channel layer; depositing a gate material (e.g., polysilicon) on the oxide layer; and selectively etching away the oxide layer and the gate material in a designated area using an etching process to form the gate 4. The fabrication process of the source 5 and drain 6 includes: on the Si...X Ge 1-x Boron ions are implanted into the non-gate region of the layer, and after annealing, the source and drain regions of the PMOS device are formed to obtain a trench PMOS device; in the In y Ga 1-y Se is applied to the non-gate region of the As layer. + Si + or S + One or more ions are implanted, and after annealing, the source and drain regions of the NMOS device are formed, resulting in a trench NMOS device; finally, a trench MOS device is obtained. Example 4

[0035] The application of the trench-type NMOS device fabrication method provided in Example 1 in the fabrication of logic chips or memory chips, and the application of the trench-type MOS device fabrication method provided in Example 3 in the fabrication of logic chips or memory chips, can be specifically applied to high-frequency / high-speed signal processing and circuit fields such as 5G communication and millimeter-wave radar.

[0036] In Example 1, silicon-germanium material is used as buffer layer 2 in the fabrication of NMOS devices. Silicon-germanium has a high hole mobility. In Example 3, the fabrication process of PMOS devices is to remove the growth process of indium gallium arsenide from the steps of Example 1. The trench-type NMOS devices suitable for high frequency / high speed fabricated in Example 1 are compatible with the trench-type MOS devices suitable for high frequency / high speed fabricated in Example 3, and can be used to fabricate some high-speed logic chips and memory chips, etc.

[0037] The above embodiments provide a transition-grown trench-type high-mobility NMOS device, a MOS device, a fabrication method, and applications. These belong to the category of channel design optimization for MOSFET chips in chip fabrication and can be applied to all products at any process node. Advantages include, but are not limited to, the following: This invention combines a gradient (gradually changing composition + fixed composition) silicon-germanium buffer layer 2 with an indium gallium arsenide (IGaAs) channel process, solving the problems of lattice mismatch and thermal expansion between the substrate silicon and IGaAs. Using IGaAs as the N-channel layer 3 material can improve the electron mobility of the product, i.e., the NMOS device. The electron mobility of the IGaAs channel is much greater than that of the traditional silicon channel, and InGaAs (e.g., In with a high In content)... 0.53 Ga 0.47 The electron mobility of As can reach 10,000-15,000 cm⁻¹. 2 / (V·s) is the electron mobility of silicon (~1,400 cm⁻¹). 2The electron saturation velocity of indium gallium arsenide (IGAA) is 7-10 times that of silicon-based devices. Higher carrier velocities can significantly increase device switching frequencies, making it suitable for high-frequency applications such as 5G communication and millimeter-wave radar. It also allows performance to be maintained with shorter channel lengths, making it suitable for advanced processes (such as below 5nm). Under the same drive current, the operating voltage can be reduced to 1 / 3 of that of silicon-based devices, significantly reducing power consumption (e.g., mobile devices, AI chips). Meanwhile, the electron saturation velocity of IGAA is 7-10 times that of silicon-based devices (~2.5 × 10⁻⁶ V·s). 7 (cm / s) far exceeds that of silicon (~1×10) 7 cm / s, suitable for high-frequency (above 100 GHz) applications.

[0038] The above description of the embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principle of the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A method for fabricating a trench-type NMOS device, characterized in that, Includes the following steps: S11. A first trench (10) is formed on the substrate (1). S12. A buffer layer (2) and an N-channel layer (3) of an NMOS device are sequentially formed in the first trench (10). The electron mobility of the N-channel layer (3) is greater than that of the substrate (1). The lattice constants of the substrate (1), the buffer layer (2) and the N-channel layer (3) increase sequentially. S13. Prepare the gate (4), source (5) and drain (6) of the NMOS device.

2. The method for fabricating a trench-type NMOS device according to claim 1, characterized in that, The substrate (1) is made of silicon; the buffer layer (2) is made of Si. X Ge 1-x Layer, wherein 0≤x≤1; the N-channel layer (3) is In y Ga 1-y A layer, where 0 ≤ y ≤ 1.

3. The method for fabricating a trench-type NMOS device according to claim 2, characterized in that, The Si X Ge 1-x The layer includes a first component gradient layer, wherein x varies with Si X Ge 1-x The deposition process gradually decreases; the In y Ga 1-y The As layer includes a second component gradient layer, where y varies with In. y Ga 1-y The deposition process of As gradually increases.

4. The method for fabricating a trench-type NMOS device according to claim 3, characterized in that, The Si X Ge 1-x The formation process of the layer includes: depositing Si in the first trench (10) by chemical vapor deposition. X Ge 1-x Material, until partially filling the first trench (10); using germane and silane as the first reaction gas, the first component is gradually changed by controlling the ratio of the first reaction gas, and linear or fast-then-slow control is performed. The deposition temperature is 550-750℃, and the pressure is less than 1×10. -5 Pa.

5. The method for fabricating a trench-type NMOS device according to claim 4, characterized in that, The In y Ga 1-y The formation process of the As layer includes: applying a physical vapor deposition (PVD) or chemical vapor deposition (CVD) process to the Si layer. X Ge 1-x In deposition on the surface of the layer y Ga 1-y As material is used until the first trench (10) is filled, and chemical mechanical polishing is performed to expose the surface of the substrate (1); when molecular beam epitaxy is used, the second component is gradually changed by adjusting the electron beam current ratio of In, Ga, and As; or, when metal-organic chemical vapor deposition is used, trimethylindium, trimethylgallium, and arsine are used as the second reaction gas, and the second component is gradually changed by adjusting the ratio of the second reaction gas, either linearly or by adjusting the speed first and then slowly, with a deposition temperature of 550-750℃ and a pressure of less than 1×10 -5 Pa.

6. The method for fabricating a trench-type NMOS device according to claim 2, characterized in that, In step S13, the fabrication process of the gate (4) includes: growing an oxide layer on the surface of the N-channel layer (3), depositing a gate material on the oxide layer, and selectively etching away the oxide layer and the gate material in a specified area using an etching process to form the gate; the fabrication process of the source (5) and drain (6) includes: growing an oxide layer on the surface of the N-channel layer (3), depositing a gate material on the oxide layer, and selectively etching away the oxide layer and the gate material in a specified area using an etching process to form the gate; y Ga 1-y Se is performed in the region of the As layer other than the gate (4). + Si + or S + One or more ions are implanted, and after annealing, the source and drain regions of the NMOS device are formed.

7. The method for fabricating a trench-type NMOS device according to claim 3, characterized in that, The buffer layer (2) further includes a first component fixing layer located between the first component gradient layer and the second component gradient layer, and the N-channel layer (3) further includes a second component fixing layer located on the other side of the second component gradient layer; The silicon-germanium ratio of the first component fixing layer remains constant, and the InGa ratio of the second component fixing layer remains constant. The thickness of the first component gradient layer is 800-1000nm, the thickness of the first component fixing layer is 80-120nm, the thickness of the second component gradient layer is 50-300nm, and the thickness of the second component fixing layer is 3-20nm.

8. A trench-type NMOS device, characterized in that, The trench-type NMOS device is prepared according to any one of claims 1-7.

9. A method for fabricating a trench-type MOS device, characterized in that, Includes the following steps: S21. A first trench (10) and a second trench are formed on the substrate (1); S22. Silicon-germanium material is grown in the first trench (10) and the second trench, and the silicon-germanium material in the second trench serves as the P-channel layer of the PMOS device. S23. Remove part of the silicon-germanium material in the first trench (10) and fill the N-channel layer (3) of the NMOS device. The electron mobility of the N-channel layer (3) is greater than that of the substrate (1). The lattice constants of the substrate (1), silicon-germanium material and N-channel layer (3) increase in sequence. S24. Fabricate the gate, source, and drain of NMOS and PMOS devices.

10. The method for fabricating a trench-type NMOS device according to any one of claims 1-7, and / or the method for fabricating a trench-type MOS device according to claim 9, and its application in the fabrication of logic chips or memory chips.

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