Cooling of backside power distribution network

By embedding through-silicon vias and microchannels on the front side of the silicon carrier, the active devices and TSV structures are separated to different substrates or material layers, solving the problems of low heat dissipation efficiency and space conflict in 3D packaging, and achieving more efficient cooling and packaging miniaturization.

CN122397381APending Publication Date: 2026-07-14INTERNATIONAL BUSINESS MACHINE CORPORATION
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
INTERNATIONAL BUSINESS MACHINE CORPORATION
Filing Date
2024-12-02
Publication Date
2026-07-14

AI Technical Summary

Technical Problem

In 3D packaging, through-silicon via (TSV) structures and microchannels have spatial conflicts, resulting in poor heat dissipation efficiency. Furthermore, the coexistence of active devices and TSV structures on the same substrate limits the miniaturization of the package.

Method used

By embedding through-silicon vias (TSVs) and microchannels on the front side of the silicon carrier, active devices and TSV structures are separated to different substrates or material layers. This utilizes different layers to separate active devices and cooling structures, avoiding spatial conflicts.

Benefits of technology

It improves heat dissipation efficiency, solves space conflict problems, and enables more efficient device cooling and packaging miniaturization.

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Abstract

An electrical device includes a thermal cooling through-silicon via (TSV) and microchannel embedded in a carrier wafer for a backside power distribution network (BSPDN). The carrier wafer is at one end of a stack of structures that provide the electrical device. At least one active device layer in the stack of structures is in a tier that is separate from a tier containing the thermal cooling through-silicon via (TSV) and microchannel in the electrical device.
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