Multi-objective optimization method for two-stage CMOS operational amplifier based on improved NSGA-II algorithm
By improving the NSGA-II algorithm and integrating it with various optimization algorithms, and combining it with a high-precision analytical model, the problems of low design efficiency, insufficient accuracy and slow convergence speed in the optimization of two-stage CMOS operational amplifiers are solved. This achieves efficient and automated multi-objective optimization, which is suitable for multi-parameter, high-performance CMOS operational amplifier design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ZHEJIANG UNIV
- Filing Date
- 2026-04-24
- Publication Date
- 2026-07-17
AI Technical Summary
Existing technologies in the optimization design of two-level CMOS operational amplifiers suffer from problems such as low design efficiency, insufficient optimization accuracy, poor constraint handling effect, uneven distribution of Pareto solution set, and slow convergence speed. In particular, it is difficult to achieve the global optimal solution in scenarios with multiple parameters and high performance requirements.
An improved NSGA-II algorithm is adopted, which combines a high-precision analytical model with the fusion of multiple optimization algorithms. By using adaptive crossover and mutation probabilities, adaptive constraint dominance strategies, and improved crowding calculation, the multi-objective optimization process of the secondary CMOS operational amplifier is optimized. This includes the fusion of algorithms such as particle swarm optimization (PSO), differential evolution (DE), and simulated annealing (SA) to achieve a balance between global search and local fine search.
It improves the optimization accuracy and efficiency of secondary CMOS operational amplifiers, reduces the need for simulation verification, adapts to different engineering requirements, enhances the automation and practicality of the design, and is applicable to mainstream CMOS process nodes such as 0.18μm and 0.35μm.
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