Switching drive circuit, switching drive method, and switching power supply

Abstract

This invention proposes a switch driving circuit, a switch driving method, and a switching power supply. The switch driving circuit, used to drive power devices, includes a sampling circuit, a soft-shutdown control circuit, and a driving circuit. The input of the sampling circuit is coupled to the power device, and the sampling circuit generates a sampled signal characterizing the driving signal. The soft-shutdown control circuit compares the sampled signal and a reference signal to generate a comparison result signal, and generates a first soft-shutdown control signal based on the comparison result signal, a pulse width modulation signal, and a fault signal. The input of the driving circuit is coupled to the output of the soft-shutdown control circuit, and the driving circuit controls the turn-off speed of the power device according to the first soft-shutdown control signal to adjust the driving signal. This invention provides a switch driving circuit, a switch driving method, and a switching power supply that, through adaptive soft-shutdown control, adapts to different types of power devices, achieving reliable soft-shutdown protection while reducing system response time.

Description

Technical Field

[0001] This invention belongs to the field of power electronics and relates to a switch control technology, particularly a switch driving circuit, a switch driving method, and a switch power supply. Background Technology

[0002] With the development of power systems, their complexity is constantly increasing, placing higher demands on the gate drive circuit, which acts as a bridge between the controller and power devices. Traditional gate drive chips only need to provide potential conversion and current amplification functions. However, with the increase in power system bus voltage, operating frequency, and the use of third-generation semiconductors such as silicon carbide (SiC) and gallium nitride (GaN), gate drivers are required to provide a series of protection functions such as overcurrent protection (OCP), undervoltage protection (UVP), and overtemperature protection (OTP). Intelligent gate drive chips integrating these functions have emerged to meet this need.

[0003] Soft turn-off technology, a common protection circuit used in gate driver chips, typically appears alongside overcurrent protection (OCP) functions. It is used to limit the rate of gate potential drop in power devices after an overcurrent fault, preventing accidental turn-on due to excessively rapid turn-off. Therefore, soft turn-off technology is widely used in insulated-gate bipolar transistors (IGBTs) and silicon carbide (SiC) dedicated gate driver chips with overcurrent protection.

[0004] Most existing soft-shutdown technologies utilize off-chip discrete devices, and in some specific applications, FPGAs (Field-Programmable Gate Arrays) are used for auxiliary control. The numerous off-chip components result in high system complexity and cost. Considering system complexity and cost, fully integrated soft-shutdown technology is undoubtedly the future direction of technological development. However, existing fully integrated soft-shutdown technologies, when faced with different types of power devices or overcurrent conditions of varying severity, can only shut down the power device with a fixed current after an overcurrent fault, without the ability to adjust the current appropriately.

[0005] In view of this, there is a need to provide a new structure or control method to solve at least some of the above problems. Summary of the Invention

[0006] To address one or more problems in the prior art, the present invention proposes a switch driving circuit, a switch driving method, and a switching power supply.

[0007] According to one aspect of the present invention, a switch driving circuit is disclosed, which is used to drive a power device. The switch driving circuit includes:

[0008] The sampling circuit, whose input is used to couple to the power device, is used to generate a sampling signal that characterizes the driving signal, which is used to drive the power device.

[0009] A soft-shutdown control circuit has inputs for acquiring a pulse-width modulation (PWM) signal, a sampled signal, and a fault signal, respectively. It compares the sampled signal with a reference signal to generate a comparison result signal, and generates a first soft-shutdown control signal based on the comparison result signal, the PWM signal, and the fault signal. During a switching cycle, if the time interval between the edge of the PWM signal and the edge of the comparison result signal is greater than a first preset time, or if the edge of the comparison result signal lags behind the edge of a first delayed signal, and the fault signal is in a triggered state, the first soft-shutdown control signal is controlled to a first level to accelerate the turn-off speed of the power device. The first delayed signal is the signal obtained by delaying the PWM signal by a first preset time.

[0010] The drive circuit has its input terminal coupled to the output terminal of the soft turn-off control circuit, and is used to control the turn-off speed of the power device according to the first soft turn-off control signal to adjust the drive signal.

[0011] In one embodiment, the soft-shutdown control circuit includes:

[0012] The comparator circuit has its first input terminal coupled to the output terminal of the sampling circuit, and its second input terminal used to acquire the reference signal.

[0013] The first delay circuit has its input terminal coupled to the pulse width modulation signal terminal to obtain the pulse width modulation signal;

[0014] A first D flip-flop, its data input terminal coupled to the output terminal of a first delay circuit, and its clock signal input terminal coupled to the output terminal of a comparator circuit; and

[0015] The first RS flip-flop has a set terminal used to acquire a fault signal, and its reset terminal is coupled to the output terminal of the first D flip-flop, which outputs the first soft shutdown control signal.

[0016] In one embodiment, the soft-shutdown control circuit includes:

[0017] The comparator circuit has its first input terminal coupled to the output terminal of the sampling circuit, and its second input terminal used to acquire the reference signal.

[0018] A first delay circuit, the input of which is used to acquire a pulse width modulation signal; and

[0019] The judgment circuit has its input terminals coupled to the output terminals of the comparison circuit and the first delay circuit, respectively. It is used to generate a judgment signal based on the edge of the comparison result signal and the edge of the first delay signal, and to generate a first soft shutdown control signal based on the judgment signal and the fault signal.

[0020] In one embodiment, the soft-shutdown control circuit includes:

[0021] The comparator circuit has its first input terminal coupled to the output terminal of the sampling circuit, and its second input terminal used to acquire a reference signal; and

[0022] The judgment circuit has its input terminals coupled to the output terminal of the comparison circuit and the pulse width modulation signal terminal, respectively. It is used to generate a judgment signal based on the time interval between the edge time of the pulse width modulation signal and the edge time of the comparison result signal and a first preset time, and to generate a first soft shutdown control signal based on the judgment signal and the fault signal.

[0023] In one embodiment, the sampling circuit includes a resistor divider circuit for generating a sampled signal characterizing the driving signal; or,

[0024] The sampling circuit includes a slope detection circuit, which is used to generate a sampling signal characterizing the driving signal.

[0025] In one embodiment, the drive circuit includes a soft-shutdown circuit, the input of which is coupled to the output of a soft-shutdown control circuit. The soft-shutdown circuit is used to control the turn-off speed of the power device according to a first soft-shutdown control signal.

[0026] In one embodiment, the soft-shutdown control circuit further includes:

[0027] A data selector, wherein its first data input is used to acquire a preset level signal, its second data input is used to receive a pulse width modulation signal, and its selection input is used to receive a fault signal; and

[0028] The NOT gate has its input coupled to the output of the data selector, and its output coupled to the reset terminal of the first D flip-flop.

[0029] In one embodiment, the soft-shutdown control circuit further includes:

[0030] The second delay circuit has its input terminal coupled to the pulse width modulation signal terminal;

[0031] The second D flip-flop has its data input coupled to the output of the second delay circuit, and its clock signal input coupled to the output of the comparator circuit; and

[0032] The second RS flip-flop has a set terminal used to acquire a fault signal, and its reset terminal is coupled to the output terminal of the second D flip-flop, which outputs the second soft shutdown control signal.

[0033] In one embodiment, the determination circuit includes an edge detection circuit, the input terminal of which is coupled to the output terminal of the comparison circuit and the output terminal of the first delay circuit, respectively. The edge detection circuit is used to obtain a first edge signal based on the comparison result signal and to obtain a second edge signal based on the first delay signal.

[0034] According to another aspect of the present invention, a switching power supply is disclosed, the switching power supply including a switching drive circuit as described in any of the preceding claims, the switching drive circuit being used to control a drive signal to drive power devices in the switching power supply.

[0035] According to another aspect of the present invention, a switch driving method is disclosed, which is used to control a switch driving circuit. The switch driving method includes:

[0036] Generate a sampled signal that characterizes the drive signal, which is used to drive the power device;

[0037] The sampled signal and the reference signal are compared to generate a comparison result signal. A first soft-shutdown control signal is generated based on the comparison result signal, the pulse width modulation signal, and the fault signal. During the switching cycle, if the time interval between the edge of the pulse width modulation signal and the edge of the comparison result signal is greater than a first preset time, or the edge of the comparison result signal lags behind the edge of the first delayed signal, and the fault signal is in a triggered state, the first soft-shutdown control signal is controlled to a first level to accelerate the turn-off speed of the power device. The first delayed signal is the signal obtained by delaying the pulse width modulation signal by a first preset time.

[0038] The turn-off speed of the power device is controlled according to the first soft turn-off control signal to adjust the drive signal.

[0039] This invention proposes a switch driving circuit, a switch driving method, and a switching power supply. The switch driving circuit drives a power device and includes a sampling circuit, a soft-turn-off control circuit, and a driving circuit. The input of the sampling circuit is coupled to the power device, and the sampling circuit generates a sampling signal characterizing the driving signal, which is used to drive the power device. The input of the soft-turn-off control circuit acquires a pulse-width modulation (PWM) signal, a sampling signal, and a fault signal, respectively. The soft-turn-off control circuit compares the sampling signal and a reference signal and generates a comparison result signal, and generates a first soft-turn-off control signal based on the comparison result signal, the PWM signal, and the fault signal. During the switching cycle, when the time interval between the edge of the PWM signal and the edge of the comparison result signal is greater than a first preset time, or the edge of the comparison result signal lags behind the edge of a first delayed signal, and the fault signal is in a triggered state, the soft-turn-off control circuit controls the first soft-turn-off control signal to a first level to accelerate the turn-off speed of the power device. The first delayed signal is the signal obtained by delaying the PWM signal by a first preset time. The input terminal of the drive circuit is coupled to the output terminal of the soft-shutdown control circuit. The drive circuit is used to control the turn-off speed of the power device according to the first soft-shutdown control signal to adjust the drive signal. The present invention proposes a switch drive circuit, a switch drive method, and a switching power supply, which, through adaptive soft-shutdown control, adapts to different types of power devices, achieving reliable soft-shutdown protection while reducing system response time. Attached Figure Description

[0040] The accompanying drawings are provided to further illustrate the invention and, together with the description, serve to explain embodiments of the invention, but do not constitute a limitation thereof. In the drawings:

[0041] Figure 1 A schematic diagram of the circuit structure of a switch driving circuit according to an embodiment of the present invention is shown;

[0042] Figure 2 A schematic diagram of the circuit structure of a switching power supply according to another embodiment of the present invention is shown;

[0043] Figure 3 A schematic diagram of the circuit structure of a switching power supply according to another embodiment of the present invention is shown;

[0044] Figure 4 A schematic diagram of the circuit structure of a soft shutdown control circuit according to an embodiment of the present invention is shown.

[0045] Figure 5 A schematic diagram of the circuit structure of a soft shutdown control circuit according to another embodiment of the present invention is shown;

[0046] Figure 6A schematic diagram of the circuit structure of a soft shutdown control circuit according to another embodiment of the present invention is shown;

[0047] Figure 7 A schematic diagram of the circuit structure of a soft shutdown control circuit according to an embodiment of the present invention is shown.

[0048] Figure 8 A schematic diagram of the signal waveform of a switching power supply according to an embodiment of the present invention is shown. Detailed Implementation

[0049] To further understand the present invention, preferred embodiments of the present invention are described below in conjunction with examples. However, it should be understood that these descriptions are only for further illustrating the features and advantages of the present invention, and not for limiting the scope of the claims of the present invention.

[0050] The description in this section pertains to only a few typical embodiments, and the present invention is not limited to the scope of the embodiments described. Combinations of different embodiments, substitution of some technical features in different embodiments, and substitution of similar or identical prior art with some technical features in the embodiments are also within the scope of the description and protection of the present invention.

[0051] The terms "coupled" or "connected" in this specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as a connection through an electrically conductive medium like a conductor, which may contain parasitic inductance or capacitance. It can also be a connection through intermediate circuits or components described in the embodiments of this specification. Indirect connections may also include connections through other active or passive devices that achieve the same or similar functions, such as connections through switches, signal amplification circuits, follower circuits, or other circuits or components. "A plurality of" or "more" indicates two or more. Furthermore, in this invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship or order between these technical features.

[0052] One embodiment of the present invention discloses a switch driving circuit, which is used to drive power devices in a switching power supply. In one embodiment, as shown... Figure 1As shown, the switch driving circuit includes a sampling circuit 10, a soft-turn-off control circuit 20, and a driving circuit 30. The input terminal of the sampling circuit 10 is coupled to a power device, and the sampling circuit 10 generates a sampling signal characterizing the driving signal, which is used to drive the power device. The sampling signal is proportional to or positively correlated with the driving signal Vgate. The input terminal of the soft-turn-off control circuit 20 is coupled to the output terminal of the sampling circuit to obtain the sampling signal, a pulse width modulation signal terminal to obtain the pulse width modulation signal, and a fault signal terminal to obtain the fault signal. The soft-turn-off control circuit 20 compares the sampling signal and a reference signal and generates a comparison result signal, and generates a first soft-turn-off control signal based on the comparison result signal, the pulse width modulation signal, and the fault signal. In one embodiment, during the switching cycle, when the time interval between the edge of the pulse width modulation signal and the edge of the comparison result signal is greater than a first preset time, and the fault signal is in a triggered state, the soft-turn-off control circuit 20 controls the first soft-turn-off control signal to a first level to accelerate the turn-off speed of the power device. In another embodiment, during the switching cycle, when the edge of the comparison result signal lags behind the edge of the first delay signal, and the fault signal is in a triggered state, the soft shutdown control circuit 20 controls the first soft shutdown control signal to a first level to accelerate the turn-off speed of the power device. The first delay signal is a signal obtained by delaying the pulse width modulation signal by a first preset time. The switching cycle is the switching cycle of the power device. The pulse width modulation signal can be used to control the switching cycle of the power device. In one embodiment, the edge time of the pulse width modulation signal refers to the moment when the pulse width modulation signal first experiences a rising edge during the current switching cycle. The edge time of the comparison result signal refers to the moment when the comparison result signal first experiences a rising edge during the current switching cycle. In another embodiment, the edge time of the pulse width modulation signal refers to the moment when the pulse width modulation signal first experiences a falling edge during the current switching cycle. The edge time of the comparison result signal refers to the moment when the comparison result signal first experiences a falling edge during the current switching cycle. Figure 1 As shown, the input terminal of the drive circuit 30 is coupled to the output terminal of the soft shutdown control circuit 20. The drive circuit 30 is used to control the shutdown speed of the power device according to the first soft shutdown control signal to adjust the drive signal.

[0053] In one embodiment, the input of the soft shutdown control circuit is used to acquire the pulse width modulation signal, the sampled signal, and the fault signal, respectively. The soft shutdown control circuit compares the sampled signal and the reference signal to generate a comparison result signal, and generates a first soft shutdown control signal based on the comparison result signal, the pulse width modulation signal, and the fault signal. During the switching cycle, when the edge of the comparison result signal lags behind the edge of the first delayed signal, and the fault signal is in a triggered state, the soft shutdown control circuit controls the first soft shutdown control signal to a first level to accelerate the turn-off speed of the power device. The first delayed signal is the pulse width modulation signal delayed by a first preset time.

[0054] In one embodiment, such as Figure 2 As shown, the switch driving circuit includes a sampling circuit 10, a soft-shutdown control circuit 20, and a drive circuit 30. The switch driving circuit has a sampling pin CLAMP and an output pin VOUT. The input of the sampling circuit 10 is coupled to the gate of the power device IGBT through the sampling pin CLAMP, and the output of the sampling circuit 10 outputs a sampling signal GATE_SENSE. The input of the soft-shutdown control circuit 20 is coupled to the output of the sampling circuit 10 to obtain the sampling signal GATE_SENSE, a pulse width modulation signal to obtain the pulse width modulation signal PWM, and a fault signal to obtain the fault signal FAULT. The output of the soft-shutdown control circuit 20 outputs a first soft-shutdown control signal SSD_1.

[0055] In one embodiment, such as Figure 2 As shown, the driving circuit 30 includes a soft-turn-off circuit 310. The input terminal of the soft-turn-off circuit is coupled to the output terminal of the soft-turn-off control circuit. The soft-turn-off circuit is used to control the turn-off current of the power device IGBT according to the first soft-turn-off control signal SSD_1. In one embodiment, the soft-turn-off circuit includes a pull-down transistor M0 and a first switching transistor M1. When the capacitance value of the input capacitor of the power device IGBT is less than a preset capacitance value, only the pull-down transistor M0 can be turned on to achieve soft turn-off of the power device IGBT during the turn-off phase. When the capacitance value of the input capacitor of the power device IGBT is greater than the preset capacitance value, both the pull-down transistor M0 and the first switching transistor M1 can be turned on simultaneously to achieve soft turn-off of the power device IGBT during the turn-off phase. In one embodiment, as shown... Figure 2 As shown, the soft-shutdown circuit 310 includes a pull-down transistor M0, a first switching transistor M1, a first switch, and an OR gate. The first input of the OR gate is coupled to a pulse width modulation (PWM) signal terminal to obtain a PWM signal, and the second input of the OR gate is coupled to an overcurrent protection (OCP) signal terminal to obtain an overcurrent protection (OCP) signal. In another embodiment, the first input of the OR gate is coupled to a PWM signal terminal to obtain a PWM signal, and the second input of the OR gate is coupled to a fault signal terminal to obtain a fault signal. In one embodiment, as... Figure 2 As shown, the first terminal of the pull-down transistor M0 is coupled to the gate of the power device IGBT, the second terminal of the pull-down transistor M0 is coupled to ground, and the control terminal of the pull-down transistor M0 is coupled to the output terminal of the OR gate. The first terminal of the first switch is coupled to the output terminal of the OR gate, and the control terminal of the first switch is coupled to the output terminal of the soft-turn-off control circuit to obtain the first soft-turn-off control signal SSD_1. The first terminal of the first switch transistor M1 is coupled to the gate of the power device IGBT, the second terminal of the first switch transistor M1 is coupled to ground, and the control terminal of the first switch transistor M1 is coupled to the second terminal of the first switch. In another embodiment, as shown... Figure 2As shown, the drive circuit 30 further includes a driver 320. The input terminal of the driver 320 is coupled to a pulse width modulation signal terminal to obtain a pulse width modulation signal PWM, and the output terminal of the driver 320 is used to couple to a power device IGBT. In another embodiment, the output terminal of the driver 320 is coupled to a first terminal of a drive resistor Rg, and the second terminal of the drive resistor Rg is coupled to the gate of the power device IGBT. In one embodiment, the switch drive circuit further includes a fault signal generation circuit 40, which outputs a fault signal FAULT. The fault signal generation circuit 40 can control the fault signal FAULT to a first level (e.g., a high level) when any of the abnormal operating conditions such as overcurrent, short circuit, overtemperature, overload, or overvoltage occur in the switching power supply.

[0056] In another embodiment, the drive circuit includes a soft-turn-off circuit. The soft-turn-off circuit regulates the turn-off speed of the power device by controlling the turn-off current of the power device. In one embodiment, the soft-turn-off circuit includes a pull-down circuit for coupling the gate of the power device. The pull-down circuit is a device with an adjustable pull-down current. A first soft-turn-off control signal can be used to adjust the pull-down current of the pull-down circuit. In a specific embodiment, the soft-turn-off circuit includes a pull-down transistor with an adjustable pull-down current. In another embodiment, the soft-turn-off circuit includes any one of a current source, an NMOS transistor, or an adjustable resistor with an adjustable pull-down current.

[0057] In one embodiment, such as Figure 3 As shown, the drive circuit 30 includes a soft-shutdown circuit 310. The soft-shutdown circuit 310 includes a pull-down transistor M0, a first switch M1, a second switch M2, a first switch, a second switch, and an OR gate. The first input of the OR gate is coupled to a pulse width modulation (PWM) signal terminal to obtain the PWM signal, and the second input of the OR gate is coupled to an overcurrent protection (OCP) signal terminal to obtain the OCP signal. The first terminal of the pull-down transistor M0 is coupled to the gate of the power device IGBT, the second terminal of the pull-down transistor M0 is coupled to ground, and the control terminal of the pull-down transistor M0 is coupled to the output of the OR gate. The first terminal of the first switch is coupled to the output of the OR gate, and the control terminal of the first switch is coupled to the output of the soft-shutdown control circuit to obtain a first soft-shutdown control signal SSD_1. The first terminal of the first switch M1 is coupled to the gate of the power device IGBT, the second terminal of the first switch M1 is coupled to ground, and the control terminal of the first switch M1 is coupled to the second terminal of the first switch. The first terminal of the second switch is coupled to the output terminal of the OR gate, and the control terminal of the second switch is coupled to the output terminal of the soft-shutdown control circuit to obtain the second soft-shutdown control signal SSD_2. The first terminal of the second switch transistor M2 is used to couple to the gate of the power device IGBT, the second terminal of the second switch transistor M2 is coupled to ground, and the control terminal of the second switch transistor M2 is coupled to the second terminal of the second switch.

[0058] In one embodiment, such as Figure 4As shown, the soft-shutdown control circuit 20 includes a comparator circuit 210, a first delay circuit 220, a first D flip-flop 230, and a first RS flip-flop 240. The first input terminal of the comparator circuit 210 is coupled to the output terminal of the sampling circuit to obtain the sampling signal GATE_SENSE. The second input terminal of the comparator circuit 210 is used to obtain the reference signal VREF. The output terminal of the comparator circuit 210 outputs the comparison result signal GATE_SENSE_PWM. The comparator circuit 210 includes a comparator. The non-inverting input terminal of the comparator is coupled to the output terminal of the sampling circuit to obtain the sampling signal GATE_SENSE. The inverting input terminal of the comparator is used to obtain the reference signal VREF. The output terminal of the comparator outputs the comparison result signal GATE_SENSE_PWM. In one embodiment, the input terminal of the first delay circuit 220 is coupled to the pulse width modulation signal terminal to obtain the pulse width modulation signal PWM. The first delay circuit 220 is used to delay the pulse width modulation signal for a first preset time to generate a first delay signal PWM_DELAY_1. The data input terminal D of the first D flip-flop 230 is coupled to the output terminal of the first delay circuit 220, and the clock signal input terminal CLK of the first D flip-flop 230 is coupled to the output terminal of the comparator circuit 210. The set terminal S of the first RS flip-flop 240 is used to obtain the fault signal FAULT, the reset terminal R of the first RS flip-flop 240 is coupled to the output terminal Q of the first D flip-flop 230, and the output terminal of the first RS flip-flop 240 outputs the first soft shutdown control signal SSD_1. In one embodiment, during the switching cycle, when the rising edge of the comparison result signal GATE_SENSE_PWM lags behind the rising edge of the first delay signal PWM_DELAY_1, the first D flip-flop 230 outputs a high level, and then returns to a low level when the low level of the pulse width modulation signal arrives. In another embodiment, during the switching cycle, when the rising edge of the comparison result signal GATE_SENSE_PWM lags behind the rising edge of the first delay signal PWM_DELAY_1, the first D flip-flop 230 outputs a high level, and after a set time, the first D flip-flop 230 returns to a low level. In one embodiment, as... Figure 4 As shown, after the output signal of the first D flip-flop 230 is latched with the fault signal by RS, the first RS flip-flop 240 generates a first soft shutdown control signal that is at the first level (e.g., high level) when a system fault occurs.

[0059] In existing technologies, for power devices with large input capacitance, the turn-off speed is too slow, resulting in excessive system operating time and negatively impacting system response speed. Conversely, for power devices with small input capacitance, the turn-off speed is too fast, leading to large dV / dt and di / dt values, posing a risk of secondary turn-on. To address these issues, an adaptive soft-turn-off technique is proposed. This invention obtains specific information about the power device's switching process, thereby adaptively adjusting the soft-turn-off current. The control process of this invention detects the power device's turn-on speed, and the delay relationship between the result signal GATE_SENSE_PWM and the first delay signal PWM_DELAY_1 corresponds to the size of the power device's input capacitance Ciss under the same driving capability. For input capacitances with small capacitance (compared to the preset capacitance value), the rising edge of GATE_SENSE_PWM precedes the rising edge of PWM_DELAY_1. In this case, the first D flip-flop will never output a high level, and soft turn-off is ultimately achieved only through the pull-down transistor M0, while the first switching transistor M1 remains inactive. For input capacitors with larger capacitance (compared to the preset capacitance value), the rising edge of GATE_SENSE_PWM lags behind the rising edge of PWM_DELAY_1. At this time, the first D flip-flop will output a high level. After being latched by RS with the fault signal, the first soft turn-off control signal SSD_1 goes high, selecting the first switching transistor M1 and generating a greater soft turn-off pull-down capability, thereby accelerating the turn-off speed of the power device.

[0060] In another embodiment, such as Figure 5 As shown, the soft shutdown control circuit 20 includes a comparison circuit 210, a first delay circuit 220, and a judgment circuit 230. The first input terminal of the comparison circuit 210 is coupled to the output terminal of the sampling circuit, and the second input terminal of the comparison circuit 210 is used to acquire the reference signal VREF. The input terminal of the first delay circuit 220 is used to acquire the pulse width modulation signal PWM. The input terminals of the judgment circuit 230 are coupled to the output terminals of the comparison circuit 210 and the first delay circuit 220, respectively. The judgment circuit 230 is used to generate a judgment signal based on the edge of the comparison result signal and the edge of the first delay signal, and to generate a first soft shutdown control signal SSD_1 based on the judgment signal and the fault signal. In one embodiment, during the switching cycle, when the edge of the comparison result signal lags behind the edge of the first delay signal, it can be determined that the capacitance value of the input capacitor of the power device is greater than a preset capacitance value, and the judgment circuit controls the judgment signal to a first level (e.g., high level). Otherwise, the judgment circuit controls the judgment signal to a second level (e.g., low level). In another embodiment, the determination circuit controls the first soft shutdown control signal to a first level if the determination signal is at a first level and the fault signal is also at a first level. Otherwise, the determination circuit controls the first soft shutdown control signal to a second level.

[0061] In one embodiment, such as Figure 5 As shown, the judgment circuit 230 includes an edge detection circuit 231 and a soft shutdown control signal generation circuit 232. The input terminals of the edge detection circuit 231 are coupled to the output terminals of the comparison circuit 210 and the first delay circuit 220, respectively. The edge detection circuit 231 is used to obtain a first edge signal based on the comparison result signal GATE_SENSE_PWM, and a second edge signal based on the first delay signal PWM_DELAY_1. The edge detection circuit 231 generates a judgment signal based on the first and second edge signals. The first input terminal of the soft shutdown control signal generation circuit 232 is coupled to the output terminal of the edge detection circuit 231, and the second input terminal is coupled to the fault signal terminal to obtain the fault signal FAULT. The soft shutdown control signal generation circuit 232 is used to generate a first soft shutdown control signal SSD_1 based on the judgment signal and the fault signal.

[0062] In another embodiment, the soft shutdown control circuit includes a comparator circuit and a judgment circuit. The first input terminal of the comparator circuit is coupled to the output terminal of the sampling circuit, and the second input terminal of the comparator circuit is used to acquire a reference signal. The input terminal of the judgment circuit is coupled to the output terminal of the comparator circuit and the pulse width modulation signal terminal, respectively. The judgment circuit generates a judgment signal based on the time interval between the edge of the pulse width modulation signal and the edge of the comparison result signal and a first preset time, and generates a first soft shutdown control signal based on the judgment signal and a fault signal. When the time interval is greater than the first preset time, it is known that the capacitance value of the power device's input capacitor is greater than a preset capacitance value, and the judgment circuit controls the judgment signal to a first level (e.g., high level). When the time interval is less than the first preset time, it is known that the capacitance value of the power device's input capacitor is less than the preset capacitance value, and the judgment circuit controls the judgment signal to a second level (e.g., low level).

[0063] In one embodiment, such as Figure 6As shown, the soft-shutdown control circuit 20 includes a comparator circuit 210, a first delay circuit 220, a first D flip-flop 230, a first RS flip-flop 240, a data selector 250, and an NOT gate. The first data input terminal D0 of the data selector 250 is used to acquire a preset level signal (e.g., a high level), the second data input terminal D1 of the data selector 250 is used to receive a pulse width modulation signal (PWM), and the selection input terminal S of the data selector 250 is used to receive a fault signal FAULT. When the fault signal FAULT is at the first level (e.g., a high level), the data selector 250 selects to output the PWM signal; when the fault signal FAULT is at the second level (e.g., a low level), the data selector 250 selects to output the preset level signal. The input terminal of the NOT gate is coupled to the output terminal of the data selector 250, and the output terminal of the NOT gate is coupled to the reset terminal nRST of the first D flip-flop 230. During the switching cycle, when the rising edge of the comparison result signal GATE_SENSE_PWM lags behind the rising edge of the first delay signal PWM_DELAY_1, the first D flip-flop 230 outputs a high level. This high level continues until the pulse width modulation signal PWM goes low. After the first D flip-flop 230 is reset, it outputs a low level. After the output signal of the first D flip-flop 230 is latched with the fault signal by RS, the first RS flip-flop 240 generates a first soft-shutdown control signal that is at the first level (e.g., high level) in the event of a system fault.

[0064] In one embodiment of the present invention, such as Figure 7As shown, the soft shutdown control circuit 20 includes a comparator circuit 210, a first delay circuit 220, a second delay circuit 260, a first D flip-flop 230, a second D flip-flop 270, a first RS flip-flop 240, a second RS flip-flop 280, a data selector 250, a first NOT gate, and a second NOT gate. In one embodiment, the input terminal of the second delay circuit 260 is coupled to the output terminal of the first delay circuit 220. In another embodiment, the input terminal of the second delay circuit is coupled to a pulse width modulation (PWM) signal terminal to obtain a PWM signal. The second delay circuit outputs a second delay signal PWM_DELAY_2. Based on the PWM signal, the delay time of the second delay signal is greater than the delay time of the first delay signal. The data input terminal D of the second D flip-flop 270 is coupled to the output terminal of the second delay circuit 260, and the clock signal input terminal CLK of the second D flip-flop 270 is coupled to the output terminal of the comparator circuit 210. The set input S of the second RS flip-flop 280 is used to acquire the fault signal FAULT. The reset input R of the second RS flip-flop 280 is coupled to the output Q of the second D flip-flop 270. The output of the second RS flip-flop 280 outputs the second soft-shutdown control signal SSD_2. The output of the first RS flip-flop 240 outputs the first soft-shutdown control signal SSD_1. The control principle of the second soft-shutdown control signal SSD_2 is similar to that of the first soft-shutdown control signal SSD_1, and will not be repeated here. The first soft-shutdown control signal SSD_1 is used to control the conduction of the first switch M1. The second soft-shutdown control signal SSD_2 is used to control the conduction of the second switch M2. The soft-shutdown circuit is used to control the turn-off speed of the power devices according to the first soft-shutdown control signal SSD_1 and the second soft-shutdown control signal SSD_2.

[0065] In one embodiment, such as Figure 7 As shown, the first data input terminal D0 of the data selector 250 is used to acquire a preset level signal (e.g., a high level), the second data input terminal D1 of the data selector 250 is used to receive a pulse width modulation signal (PWM), and the selection input terminal S of the data selector 250 is used to receive a fault signal (FAULT). The input terminal of the first NOT gate is coupled to the output terminal of the data selector 250, and the output terminal of the first NOT gate is coupled to the reset terminal nRST of the first D flip-flop 230. The input terminal of the second NOT gate is coupled to the output terminal of the data selector 250, and the output terminal of the second NOT gate is coupled to the reset terminal nRST of the second D flip-flop 270.

[0066] In one embodiment, the sampling circuit includes a resistor divider circuit. The resistor divider circuit includes a first voltage divider resistor and a second voltage divider resistor. A first terminal of the first voltage divider resistor is coupled to the gate of the power device. A first terminal of the second voltage divider resistor is coupled to a second terminal of the first voltage divider resistor, and the second terminal of the second voltage divider resistor is coupled to ground. The first terminal of the second voltage divider resistor is used to provide a sampling signal. In another embodiment, the sampling circuit includes a slope detection circuit. The input terminal of the slope detection circuit is coupled to the gate of the power device. The slope detection circuit detects the slope of the drive signal Vgate or a signal characterizing the drive signal Vgate and generates a sampling signal that characterizes the drive signal. In one embodiment, the sampling signal is proportional to or positively correlated with the slope of the drive signal.

[0067] In one embodiment, combined with Figure 8 The solid line indicated by Ciss1 represents the signals corresponding to the input capacitance of a power device with a smaller capacitance (compared to the preset capacitance value). The dashed line indicated by Ciss2 represents the signals corresponding to the input capacitance of a power device with a larger capacitance (compared to the preset capacitance value). L1 corresponds to the output voltage VOUT of the switch drive circuit when the input capacitance of the power device is small. L3 corresponds to the output voltage VOUT of the switch drive circuit when the input capacitance of the power device is large in the prior art. L2 corresponds to the output voltage VOUT of the switch drive circuit when the input capacitance of the power device is large in this invention. Figure 8 As shown, at the rising edge of each pulse width modulation (PWM) signal (corresponding to the power device's turn-on phase), the soft-shutdown control circuit of this invention compares the rising edge of the comparison result signal GATE_SENSE_PWM with the rising edge of the first delay signal PWM_DELAY_1 (not shown in the figure). If the rising edge of the comparison result signal GATE_SENSE_PWM lags behind the first delay signal PWM_DELAY_1, the output signal Q1 of the first D flip-flop will flip from low to high. At this time, if an overcurrent or overtemperature fault is detected, the fault signal FAULT will be pulled up, thereby generating the first soft-shutdown control signal SSD_1 at the first level (e.g., high level). The high level of the first soft-shutdown control signal SSD_1 will remain for the remaining PWM signal period until the next PWM signal high level arrives or the fault signal FAULT is pulled low, and the fault judgment is re-performed. The aforementioned switch drive circuit adaptively provides a larger soft-turn-off pull-down current when the power device has a large input capacitance Ciss, saving system response time compared to traditional fixed-current pull-down soft-turn-off technology. Conversely, when the power device has a small input capacitance Ciss, a fixed pull-down current can still be used to prevent excessively fast pull-down speeds.

[0068] This invention proposes a switch driving circuit, a switch driving method, and a switching power supply. Through adaptive soft-shutdown control, it adapts to different types of power devices, achieving reliable soft-shutdown protection while reducing system response time. Furthermore, the overall architecture of the switch driving circuit of this invention has good compatibility with existing intelligent gate driving functions, eliminating the need for additional sampling pins.

[0069] Another embodiment of the present invention discloses a switching power supply, which includes a switching drive circuit as described in any of the preceding claims. The switching drive circuit controls a drive signal to drive a power device in the switching power supply. In one embodiment, the power device is externally located within the switching drive circuit, and in the switching power supply, the power device is coupled to the switching drive circuit. In another embodiment, the power device is internally located within the switching drive circuit, which is a chip. The switching drive circuit generates a drive signal to control the switching state of the power device. In one embodiment, the power device is one of a switching transistor such as an insulated-gate bipolar transistor (IGBT), a metal-oxide-semiconductor field-effect transistor (MOSFET), or a junction field-effect transistor (JFET).

[0070] Another embodiment of the present invention discloses a switch driving method, which is used to control a switch driving circuit. The switch driving method includes:

[0071] Step S1: Generate a sampling signal characterizing the drive signal, which is used to drive the power device;

[0072] Step S2: Compare the sampled signal and the reference signal to generate a comparison result signal, and generate a first soft turn-off control signal based on the comparison result signal, the pulse width modulation signal, and the fault signal; within the switching cycle, when the time interval between the edge of the pulse width modulation signal and the edge of the comparison result signal is greater than a first preset time, or the edge of the comparison result signal lags behind the edge of the first delayed signal, and the fault signal is in a triggered state, control the first soft turn-off control signal to a first level to accelerate the turn-off speed of the power device. The first delayed signal is the signal obtained by delaying the pulse width modulation signal by a first preset time; and

[0073] Step S3: Control the turn-off speed of the power device according to the first soft turn-off control signal to adjust the drive signal.

[0074] In one embodiment, the switch driving circuit includes a sampling circuit, a soft-turn-off control circuit, and a driving circuit. The sampling circuit generates a sampling signal characterizing a driving signal, which is used to drive a power device. The soft-turn-off control circuit compares the sampling signal and a reference signal and generates a comparison result signal, and generates a first soft-turn-off control signal based on the comparison result signal, a pulse width modulation signal, and a fault signal. The step of generating the first soft-turn-off control signal based on the comparison result signal, the pulse width modulation signal, and the fault signal includes: during the switching cycle, when the time interval between the edge of the pulse width modulation signal and the edge of the comparison result signal is greater than a first preset time, and the fault signal is in a triggered state, controlling the first soft-turn-off control signal to a first level to accelerate the turn-off speed of the power device. The first delay signal is the signal obtained by delaying the pulse width modulation signal by a first preset time. The driving circuit controls the turn-off speed of the power device according to the first soft-turn-off control signal to adjust the driving signal.

[0075] In another embodiment, the switch driving circuit includes a sampling circuit, a soft-turn-off control circuit, and a driving circuit. The sampling circuit generates a sampled signal characterizing a driving signal, which is used to drive a power device. The soft-turn-off control circuit compares the sampled signal and a reference signal to generate a comparison result signal, and generates a first soft-turn-off control signal based on the comparison result signal, a pulse width modulation signal, and a fault signal. The step of generating the first soft-turn-off control signal based on the comparison result signal, the pulse width modulation signal, and the fault signal includes: during the switching cycle, when the edge of the comparison result signal lags behind the edge of a first delayed signal, and the fault signal is in a triggered state, controlling the first soft-turn-off control signal to a first level to accelerate the turn-off speed of the power device. The first delayed signal is a signal obtained by delaying the pulse width modulation signal by a first preset time. The driving circuit controls the turn-off speed of the power device according to the first soft-turn-off control signal to adjust the driving signal.

[0076] Existing adaptive soft-switching technologies often rely on real-time detection of the power device's turn-off process, using closed-loop control to change the soft-switching current. This involves complex detection logic and imposes high requirements on control speed. The proposed solution, however, does not detect the power device's turn-off process. Instead, it detects and stores information about the power device during the turn-on phase, employing an approximate open-loop control approach to achieve a detection-then-control adjustment process. Furthermore, this invention has low speed requirements for both the detection and control circuits, requiring no additional circuitry or detection pins. It is fully integrated, eliminating the need for external detection and control circuitry or increasing the number of pins in the chip package. This also ensures good compatibility with existing smart gate driver chips, reducing costs.

[0077] The switch driving circuit, switch driving method, and switching power supply proposed in this invention can achieve adaptive soft shutdown control. They can automatically adjust the gate pull-down current after triggering soft shutdown according to the input capacitance Ciss of the peripheral power device, thereby improving the adaptability of the driver chip to different types and current levels of power devices.

[0078] Those skilled in the art should know that the logic controls such as "high level" and "low level", "set" and "reset", "AND gate" and "OR gate", "non-inverting input" and "inverting input" in the logic control involved in the specification or drawings can be interchanged or changed, and the same function or purpose as the above embodiment can be achieved by adjusting the subsequent logic control.

[0079] The description and application of the present invention herein are illustrative and not intended to limit the scope of the invention to the embodiments described above. The effects or advantages described in the specification may not be apparent in actual experimental cases due to uncertainties in specific conditions or other factors, and such descriptions are not intended to limit the scope of the invention. Variations and modifications to the embodiments disclosed herein are possible, and various substitutions and equivalents of the components in the embodiments are well known to those skilled in the art. It should be understood by those skilled in the art that the invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials, and parts without departing from the spirit or essential characteristics of the invention. Other variations and modifications can be made to the embodiments disclosed herein without departing from the scope and spirit of the invention.

Claims

1. A switch driving circuit for driving power devices, characterized in that, The switch driving circuit includes: The sampling circuit, whose input is used to couple to the power device, is used to generate a sampling signal that characterizes the driving signal, which is used to drive the power device. A soft-shutdown control circuit has inputs for acquiring a pulse-width modulation (PWM) signal, a sampled signal, and a fault signal, respectively. It compares the sampled signal with a reference signal to generate a comparison result signal, and generates a first soft-shutdown control signal based on the comparison result signal, the PWM signal, and the fault signal. During a switching cycle, if the time interval between the edge of the PWM signal and the edge of the comparison result signal is greater than a first preset time, or if the edge of the comparison result signal lags behind the edge of a first delayed signal, and the fault signal is in a triggered state, the first soft-shutdown control signal is controlled to a first level to accelerate the turn-off speed of the power device. The first delayed signal is the signal obtained by delaying the PWM signal by a first preset time. The drive circuit has its input terminal coupled to the output terminal of the soft turn-off control circuit, and is used to control the turn-off speed of the power device according to the first soft turn-off control signal to adjust the drive signal.

2. The switch driving circuit as described in claim 1, characterized in that, The soft shutdown control circuit includes: The comparator circuit has its first input terminal coupled to the output terminal of the sampling circuit, and its second input terminal used to acquire the reference signal. The first delay circuit has its input terminal coupled to the pulse width modulation signal terminal to obtain the pulse width modulation signal; A first D flip-flop, its data input terminal coupled to the output terminal of a first delay circuit, and its clock signal input terminal coupled to the output terminal of a comparator circuit; and The first RS flip-flop has a set terminal used to acquire a fault signal, and its reset terminal is coupled to the output terminal of the first D flip-flop, which outputs the first soft shutdown control signal.

3. The switch driving circuit as described in claim 1, characterized in that, The soft shutdown control circuit includes: The comparator circuit has its first input terminal coupled to the output terminal of the sampling circuit, and its second input terminal used to acquire the reference signal. A first delay circuit, the input of which is used to acquire a pulse width modulation signal; and The judgment circuit has its input terminals coupled to the output terminals of the comparison circuit and the first delay circuit, respectively. It is used to generate a judgment signal based on the edge of the comparison result signal and the edge of the first delay signal, and to generate a first soft shutdown control signal based on the judgment signal and the fault signal.

4. The switch driving circuit as described in claim 1, characterized in that, The soft shutdown control circuit includes: The comparator circuit has its first input terminal coupled to the output terminal of the sampling circuit, and its second input terminal used to acquire a reference signal; and The judgment circuit has its input terminals coupled to the output terminal of the comparison circuit and the pulse width modulation signal terminal, respectively. It is used to generate a judgment signal based on the time interval between the edge time of the pulse width modulation signal and the edge time of the comparison result signal and a first preset time, and to generate a first soft shutdown control signal based on the judgment signal and the fault signal.

5. The switch driving circuit as described in claim 1, characterized in that, The sampling circuit includes a resistor voltage divider circuit, which is used to generate a sampling signal characterizing the driving signal; or, The sampling circuit includes a slope detection circuit, which is used to generate a sampling signal characterizing the driving signal.

6. The switch driving circuit as described in claim 1, characterized in that, The driving circuit includes a soft-shutdown circuit, the input of which is coupled to the output of the soft-shutdown control circuit. The soft-shutdown circuit is used to control the turn-off speed of the power device according to the first soft-shutdown control signal.

7. The switch driving circuit as described in claim 2, characterized in that, The soft shutdown control circuit also includes: A data selector, wherein its first data input is used to acquire a preset level signal, its second data input is used to receive a pulse width modulation signal, and its selection input is used to receive a fault signal; and The NOT gate has its input coupled to the output of the data selector, and its output coupled to the reset terminal of the first D flip-flop.

8. The switch driving circuit as described in claim 2, characterized in that, The soft shutdown control circuit also includes: The second delay circuit has its input terminal coupled to the pulse width modulation signal terminal; The second D flip-flop has its data input terminal coupled to the output terminal of the second delay circuit, and its clock signal input terminal coupled to the output terminal of the comparator circuit; and The second RS flip-flop has a set terminal used to acquire a fault signal, and its reset terminal is coupled to the output terminal of the second D flip-flop, which outputs the second soft shutdown control signal.

9. The switch driving circuit as described in claim 3, characterized in that, The judgment circuit includes an edge detection circuit. The input terminal of the edge detection circuit is coupled to the output terminal of the comparison circuit and the output terminal of the first delay circuit, respectively. The edge detection circuit is used to obtain a first edge signal based on the comparison result signal and to obtain a second edge signal based on the first delay signal.

10. A switching power supply, characterized in that, The switching power supply includes a switching drive circuit as described in any one of claims 1-9, the switching drive circuit being used to control drive signals to drive power devices in the switching power supply.

11. A switch driving method for controlling a switch driving circuit, characterized in that, The switch driving method includes: Generate a sampled signal that characterizes the drive signal, which is used to drive the power device; The sampled signal and the reference signal are compared to generate a comparison result signal. A first soft-shutdown control signal is generated based on the comparison result signal, the pulse width modulation signal, and the fault signal. During the switching cycle, if the time interval between the edge of the pulse width modulation signal and the edge of the comparison result signal is greater than a first preset time, or the edge of the comparison result signal lags behind the edge of the first delayed signal, and the fault signal is in a triggered state, the first soft-shutdown control signal is controlled to a first level to accelerate the turn-off speed of the power device. The first delayed signal is the signal obtained by delaying the pulse width modulation signal by a first preset time. The turn-off speed of the power device is controlled according to the first soft turn-off control signal to adjust the drive signal.

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