Semiconductor device and method of forming the same
By forming an alloy material layer on the test pads and performing a reflow process, the problem of uneven bonding interfaces in 3DIC technology was solved. This enabled yield testing of the core chip and flatness of the bonding interface before stacking, thereby improving the overall chip yield and bonding effect.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ICLEAGUE TECH CO LTD
- Filing Date
- 2026-05-28
- Publication Date
- 2026-07-17
AI Technical Summary
In 3D integrated circuit (3DIC) technology, existing technologies struggle to effectively address the challenge of achieving yield testing of core chips while ensuring the bonding interface remains as flat as possible, especially for screening core chips before stacking.
After the pin test is performed on the test pad, an alloy material layer is formed. The protrusion is removed by chemical mechanical polishing or wet etching, leaving the alloy material layer in the opening. Then, a reflow process is performed to allow the alloy material layer to flow back into the opening, repairing the pin marks on the test pad and ensuring a smooth bonding interface.
This technology enables yield screening of semiconductor structures before bonding, repairs damage to test pads, ensures a smooth bonding interface, improves the success rate and overall yield of subsequent bonding, and saves costs.
Smart Images
Figure CN122421731A_ABST