Resistor model and modeling method, system and readable storage medium thereof

Abstract

The application provides a resistance model, a modeling method, a system and a readable storage medium. In the constructed resistance model, the influence of resistance distribution density is considered, and the correction function f(T, D) about the test temperature T and the resistance distribution density D, the correction function f(V, D) about the test voltage V and the resistance distribution density D and the correction function f(D) about the resistance distribution density D are used as key fitting parameters to correct the resistance model, so that the influence of the resistance distribution density on the resistance is corrected. The corrected resistance model is more perfect and accurate, can guarantee the accuracy and reliability of subsequent integrated circuit design and simulation, helps engineers to optimize the design and process of the integrated circuit, and improves the design efficiency and actual production efficiency of the integrated circuit.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a resistance model, its modeling method, system, and readable storage medium. Background Technology

[0002] In the development of semiconductor technology, device miniaturization has always been a research hotspot in the industry. The resulting reduction in critical dimensions places higher demands on the accuracy of semiconductor model fitting. To meet the needs of industrial production, new integrated circuit simulation models need to be continuously developed. Model engineers measure the electrical characteristics of components, establish model equations, extract model parameters, and create model library files to provide integrated circuit designers with models that accurately characterize the electrical characteristics of semiconductor components. This allows designers to design circuits suitable for the current process node based on the model.

[0003] The existing resistor models currently used in the industry can generally be simplified as follows:

[0004] R = R sh ·SQ eff ·(1+rvc·V)·(1+tcr·ΔT).

[0005] Among them, R sh This is a sheet resistor, whose properties depend on the material, length, and cross-sectional area of ​​the resistor. V is the voltage applied across the resistor (in volts), and ΔT is the temperature change across the resistor. This resistor model has three types of parameters:

[0006] (1) Number of valid blocks SQ eff This is used to correct the effect of the length and width of a semiconductor on its resistance.

[0007] (2) Voltage parameter rvc, used to correct the effect of voltage V on resistance;

[0008] (3) Temperature parameter tcr, used to correct the effect of temperature T on resistance.

[0009] The aforementioned old resistance model is sufficient to meet the accuracy requirements of resistance simulation at mature nodes (e.g., 65nm and above). However, at new nodes, due to process deviations such as chemical mechanical polishing (CMP) (resistance distribution density affects the surface roughness and polishing rate of CMP, as well as the polishing quality) and etching (resistance distribution density affects the aspect ratio of the etching process), the resistance distribution density on the wafer becomes uneven, which in turn affects the actual measured resistance value. The aforementioned old resistance model ignores the impact of uneven resistance distribution density, resulting in a decrease in its fitting accuracy. Summary of the Invention

[0010] The purpose of this invention is to provide a resistance model, its modeling method, system, and readable storage medium to improve the fitting accuracy of the resistance model.

[0011] To achieve the above objectives, the present invention provides a method for modeling a resistance model, which includes the following steps:

[0012] S1, Design multiple resistors with different resistance distribution densities to form a test structure;

[0013] S2, Obtain the resistance data corresponding to the test structure;

[0014] S3, establish the basic resistance model R = Rsh·f(SQ)·f(T,D)·f(V,D)·f(D), where R is the corrected resistance value, R sh For a sheet resistor, f(SQ) is a correction function for the resistor length L and width W, f(T,D) is a correction function for the test temperature T and resistance distribution density D, f(V,D) is a correction function for the test voltage V and resistance distribution density D, and f(D) is a correction function for the resistance distribution density D.

[0015] S4. Using the resistance data, curve fitting is performed to obtain the expressions for each of the correction functions, thereby obtaining the required resistance model.

[0016] Optionally, in step S1, the test structure includes at least one of the following (1) to (4):

[0017] (1) The resistance distribution density of the resistors in the test structure increases;

[0018] (2) At least one resistor in the test structure comprises n standard resistor elements of the same size and with equal spacing, and the formula for calculating the resistance distribution density D of the resistor is:

[0019] D = W / (W + W) space ) or D = W / (W + weight·W) space ) or D = n·S R / S OD ,

[0020] Where W is the resistance width of the standard resistor element, and L is the resistance length of the standard resistor element. space The spacing between adjacent standard resistor elements in the resistor is S, where weight represents the weight value. R =W·L,S OD Let n be the total area of ​​the resistor, where n ≥ 1 and is an integer;

[0021] (3) At least one resistor in the test structure comprises n resistive elements R1 to R2 of different sizes. n The formula for calculating the resistance distribution density D of the resistor is:

[0022]

[0023] Among them, S Rk R is the k-th resistive element in the resistor. k The area, S Rk =(W+ΔW) k )·(L+ΔL k ), ΔW k For R k The offset of the resistor width relative to W, ΔL k For R k The offset of the resistor length relative to L, S OD Let n be the total area of ​​the resistor, where n ≥ 1 and is an integer;

[0024] (4) The resistive elements in each of the resistors are in the shape of strips or blocks.

[0025] Optionally, in step S2, the resistance data corresponding to the test structure is obtained by fabricating the test structure on the wafer and performing wafer testing, and / or the test structure is simulated and tested using a corresponding process processing model to obtain the resistance data corresponding to the test structure.

[0026] Optionally, in step S4, if the difference between the fitting result and the resistance data is too large, the process returns to step S2 to obtain new resistance data for fitting.

[0027] And / or, after step S4, step S5 is further included: verifying the resistance model; if the resistance model fails verification, return to step S3 to modify the expression of at least one of the correction functions in the resistance model, or return to step S4 to iteratively fit the parameter constants in the expression of at least one of the correction functions in the resistance model until the resistance model passes verification.

[0028] Optionally, the correction function expression obtained in step S4 or step S5 includes at least one of the following (1) to (4):

[0029]

[0030]

[0031]

[0032]

[0033] Wherein, W is the resistance width of the standard resistor element corresponding to the resistor, L is the resistance length of the standard resistor element, ΔW is the offset of the resistance width of the resistor element in the resistor, ΔL is the offset of the resistance length of the resistor element, D is the resistance distribution density of the resistor, AH, J, K, M, XZ, a, b, tc1r and rvc are all parameter adjustment constants, T is the test temperature, V is the test voltage, and T0 is the room temperature.

[0034] Based on the same inventive concept, the present invention also provides a modeling system for a resistance model, comprising:

[0035] A resistor design unit is configured to design multiple resistors with different resistance distribution densities to form a test structure;

[0036] A data acquisition unit is configured to acquire resistance data corresponding to the test structure designed by the resistance design unit.

[0037] The modeling unit is configured to establish the basic resistance model R = Rsh·f(SQ)·f(T,D)·f(V,D)·f(D), where R is the corrected resistance value. sh For a sheet resistor, f(SQ) is a correction function for the resistor length L and width W, f(T,D) is a correction function for the test temperature T and resistance distribution density D, f(V,D) is a correction function for the test voltage V and resistance distribution density D, and f(D) is a correction function for the resistance distribution density D.

[0038] A fitting unit is configured to perform curve fitting using the resistance data to derive expressions for each of the correction functions, thereby obtaining the desired resistance model.

[0039] Optionally, the modeling system further includes at least one of the following (1) to (9):

[0040] (1) The resistor design unit uses standard resistor elements and designs multiple resistors in a manner that increases the resistance distribution density, thereby forming at least part of the test structure;

[0041] (2) The resistor design unit uses resistor elements of different sizes to design multiple resistors with different resistance distribution densities, thereby forming at least part of the test structure;

[0042] (3) The resistive elements in each resistor in the test structure are all strip-shaped or block-shaped;

[0043] (4) The resistance distribution density of the resistors in the test structure designed by the resistance design unit increases progressively;

[0044] (5) At least one resistor in the test structure designed by the resistor design unit comprises n standard resistor elements of the same size and with equal spacing, and the formula for calculating the resistance distribution density D of the resistor is:

[0045] D = W / (W + W) space ) or D = W / (W + weight·W) space ) or D = n·S R / S OD ,

[0046] Where W is the resistance width of the standard resistor element, and L is the resistance length of the standard resistor element. space The spacing between adjacent standard resistor elements in the resistor is S, where weight represents the weight value. R =W·L,S OD Let n be the total area of ​​the resistor, where n ≥ 1 and is an integer;

[0047] (6) At least one resistor in the test structure designed by the resistor design unit includes n resistor elements R1 to R2 of different sizes. n The formula for calculating the resistance distribution density D of the resistor is:

[0048]

[0049] Among them, S Rk R is the k-th resistive element in the resistor. k The area, S Rk =(W+ΔW) k )·(L+ΔL k ), ΔW k For R k The offset of the resistor width relative to W, ΔL k For R k The offset of the resistor length relative to L, S OD Let n be the total area of ​​the resistor, where n ≥ 1 and is an integer;

[0050] (7) The data acquisition unit acquires the resistance data corresponding to the test structure by acquiring the wafer test data of the wafer where the test structure is located, and / or, the data acquisition unit performs process simulation processing and simulation testing on the test structure through the corresponding process processing model to acquire the resistance data corresponding to the test structure.

[0051] (8) When the difference between the curve fitting result and the resistance data is too large, the parameter fitting unit causes the data acquisition unit to provide new resistance data for curve fitting.

[0052] (9) The modeling system further includes a model verification unit configured to perform model verification on the resistance model; when the resistance model fails the verification by the model verification unit, the parameter fitting unit iteratively fits the parameter constant in the expression of at least one of the correction functions in the resistance model, or the modeling unit modifies the expression of at least one of the correction functions in the resistance model.

[0053] Optionally, the correction function expression obtained by the modeling unit or the parameter fitting unit includes at least one of the following (1) to (4):

[0054]

[0055]

[0056]

[0057]

[0058] Wherein, W is the resistance width of the standard resistor element corresponding to the resistor, L is the resistance length of the standard resistor element, ΔW is the offset of the resistance width of the resistor element in the resistor, ΔL is the offset of the resistance length of the resistor element, D is the resistance distribution density of the resistor, AH, J, K, M, XZ, a, b, tc1r and rvc are all parameter adjustment constants, T is the test temperature, V is the test voltage, and T0 is the room temperature.

[0059] Based on the same inventive concept, the present invention also provides a readable storage medium for storing a computer program or instructions, which, when executed by a processor, implement the modeling method for the resistance model as described in the present invention.

[0060] Based on the same inventive concept, the present invention also provides a resistance model, the resistance model comprising R = Rsh·f(SQ)·f(T,D)·f(V,D)·f(D), and the resistance model further comprising at least one of the following items (1) to (4):

[0061]

[0062]

[0063]

[0064]

[0065] Where R is the corrected resistance value of the resistor, Rsh Let f(SQ) be the sheet resistance of the resistor, f(SQ) be a correction function for the resistor length L and width W, f(T,D) be a correction function for the test temperature T and resistance distribution density D, f(V,D) be a correction function for the test voltage V and resistance distribution density D, and f(D) be a correction function for the resistance distribution density D; W is the resistance width of the standard resistor element corresponding to the resistor, L is the resistance length of the standard resistor element, ΔW is the offset of the resistance width of the resistor element in the resistor, ΔL is the offset of the resistance length of the resistor element, D is the resistance distribution density of the resistor, AH, J, K, M, XZ, a, b, tc1r and rvc are all parameter adjustment constants, T is the test temperature, V is the test voltage, and T0 is the room temperature (e.g., 25°C).

[0066] Compared with the prior art, the technical solution of the present invention considers the influence of resistance distribution density D in the constructed resistance model, and uses the correction functions f(T,D) with respect to test temperature T and resistance distribution density D, the correction functions f(V,D) with respect to test voltage V and resistance distribution density D, and the correction function f(D) with respect to resistance distribution density D as key fitting parameters to correct the resistance model, so as to correct the influence of resistance distribution density on resistance. The corrected resistance model is more complete and accurate, which can ensure the accuracy and reliability of subsequent integrated circuit design and simulation, and help engineers optimize the design and process of integrated circuits, thereby improving the design efficiency and actual production efficiency of integrated circuits. Attached Figure Description

[0067] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0068] Figure 1 This is a flowchart of the modeling method for the resistance model in a specific embodiment of the present invention.

[0069] Figure 2 This is a schematic diagram of an example test structure designed in the modeling method of the resistance model in a specific embodiment of the present invention.

[0070] Figure 3 yes Figure 2 A schematic diagram of the standard resistive element in the test structure shown.

[0071] Figure 4 This is another example structural diagram of the test structure designed in the modeling method of the resistance model in a specific embodiment of the present invention.

[0072] Figure 5 yes Figure 4 The table shows the data for the relevant parameters of the resistors in the test structure.

[0073] Figure 6 This is a data illustration table of relevant parameters of the resistor in the test structure designed in the modeling method of the resistor model in a specific embodiment of the present invention (the resistor width W is 1.2μm, the length L is 90μm, and the resistance distribution density D is different).

[0074] Figure 7 Based on Figure 6 The data shown in the diagram illustrates the R-D curve obtained from the data table.

[0075] Figure 8 This is a schematic diagram of the architecture of the modeling system for the resistance model in a specific embodiment of the present invention. Detailed Implementation

[0076] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention. It should be understood that the invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" other elements, it may be directly connected to other elements, or there may be intervening elements. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items. Furthermore, it should be noted that each block in the block diagrams and / or flowcharts herein, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer program instructions. It will be well known to those skilled in the art that implementation in hardware, implementation in software, and implementation using a combination of software and hardware are equivalent.

[0077] In semiconductor device manufacturing, Chemical Mechanical Polishing (CMP) and Etching processes are frequently used. CMP is a processing technique combining chemical etching and mechanical removal, which can grind the film thickness on the wafer surface to the target thickness while maintaining the wafer's surface flatness. Etching uses chemical or physical methods to remove the thin film not covered by photoresist to achieve pattern transfer. The resistivity density of surface devices such as resistors affects the polishing quality of CMP and the actual effect of etching, specifically influencing surface roughness and polishing rate, as well as the aspect ratio of etching. Furthermore, both CMP and etching processes result in uneven resistivity density (D), which in turn affects the actual measured resistance value. Existing resistance models (i.e., older models) do not account for the resistance value variation caused by resistivity density D, leading to decreased fitting accuracy.

[0078] Based on this, the present invention provides a resistance model, its modeling method, system, and readable storage medium scheme. It introduces resistance distribution density to correct the resistance model, thus not only eliminating the influence of process deviations on the resistance value itself, but also ensuring fitting accuracy in small-size applications, making the established resistance model more consistent with actual physical laws. Therefore, when designing integrated circuits, the resistance model of this embodiment can be used to extract resistance model parameters from integrated circuits, establish a model library file, and provide integrated circuit designers with a model that accurately characterizes the resistance characteristics of semiconductor components, enabling designers to design circuits suitable for the current process node based on this model.

[0079] The following is in conjunction with the appendix Figures 1 to 8 The technical solution of the present invention will be described in detail with reference to specific embodiments.

[0080] Please refer to Figure 1 An embodiment of the present invention provides a modeling method for a resistance model, which includes the following steps:

[0081] S1 (Testkey design) involves designing multiple resistors with different resistance distribution densities to form the required test key structure.

[0082] S2(Test), obtain the resistance data corresponding to the test structure;

[0083] S3 (Model building or Model fitting) establishes the basic resistance model R = R sh·f(SQ)·f(T,D)·f(V,D)·f(D), where f(SQ) is a correction function for the resistor length L and width W, f(T,D) is a correction function for the test temperature T and resistance distribution density D, f(V,D) is a correction function for the test voltage V and resistance distribution density D, and f(D) is a correction function for the resistance distribution density D;

[0084] S4 (Data vs Model): Using the resistance data, curve fitting is performed to derive the expressions for each of the correction functions, thereby obtaining the required resistance model.

[0085] Optionally, the modeling method of the resistance model in this embodiment further includes step S5 (QA) after step S4, to perform model verification on the resistance model.

[0086] In step S1, each resistor in the test structure can be designed according to any suitable design method.

[0087] In one example, please refer to Figure 2 and Figure 3 A standard resistor element Ra with a resistance width of W and a resistance length of L can be used to design multiple resistors RT1, RT2, RT3, RT4... with increasing resistance distribution density D, thus forming the required test structure or a part of a required test structure. In this test structure, the standard resistor elements Ra are arranged at equal intervals. Each standard resistor element Ra is elongated and has contact pads P at both ends. The standard resistor elements Ra in each resistor are made of the same material and have the same size. In these resistors, the higher the resistance distribution density D, the more standard resistor elements Ra are contained in the same area, and the greater the spacing W between the internal standard resistor elements Ra. space The smaller the value. The formula for calculating the resistance distribution density D of each resistor can be D = W / (W + W) space ) or D = W / (W + weight·W) space ) or D = n·S R / S OD Where W is the resistance width of the standard resistor element Ra, W space Ra represents the spacing between adjacent standard resistive elements Ra in this resistor, and weight represents the weight value, S R =W·L,S OD This represents the total area of ​​the resistor. For example, in resistor RT1, n=1; in resistor RT2, n=2; in resistor RT3, n=3; and in resistor RT4, n=4. The resistance distribution density D of RT1 to RT4 gradually increases.

[0088] In another example, please combine Figure 4 and Figure 5 Multiple resistors RT with different resistance distribution densities D can be designed using resistor elements R1 to Rn with different resistance widths W and lengths L, thus forming the desired test structure or a part of a desired test structure. The resistor elements R1 to Rn in these resistor structures are all elongated strips made of the same material, with contact pads at both ends. The number n of resistor elements in different resistors RT can be the same or different. The resistance distribution density D of the i-th resistor RTi in the test structure... i The calculation formula is:

[0089]

[0090] Where, n i The number of resistive elements in the RTi region of the resistor (i.e., R1 to Rn are provided in the RTi region). i ), S Rk Let S be the area of ​​the k-th resistive element Rk within the resistor RTi region. Rk =(W+ΔW) k )·(L+ΔL k ), S Rmin＝ W·L,S ODi W represents the total area of ​​resistor RTi. k L is the offset of the resistance width of the k-th resistor element Rk relative to the resistance width W of the standard resistor element. k It is the offset of the resistance length of the k-th resistor element Rk relative to the resistance length L of the standard resistor element.

[0091] In other embodiments of the present invention, multiple resistors with different resistance distribution densities D can be designed using resistive elements of the same width but different lengths. The number of resistive elements in each resistor can be the same or different, thereby forming a portion of the required test structure. The resistive elements in these resistors are all elongated or block-shaped, made of the same material, and have contact pads P at both ends. Exemplarily, a design rule for some of these resistors is that the larger the resistance distribution density D, the shorter the length L of the resistive elements used, the more resistive elements are contained in an area of ​​the same size, and the smaller the spacing S between the internal resistive elements.

[0092] In one example, step S1 is the process of completing the layout design of the test structure and fully validating the layout design, which may include the following stages:

[0093] 1. Layout: Plan the layout (or types) of the functional units such as the test structure;

[0094] 2. Routing: Internal routing connects the functional units such as the test structure and generates layout data (which is a GDSII file);

[0095] 3. Verification: Based on the layout data, the test structure undergoes a series of verifications, including design rule checking (DRC), design rule checking (LVS), and electrical rule checking (ERC), to ensure the accuracy and manufacturability of the layout data. Design rule checking examines the geometry of the test structure's layout (including linewidth, line length, spacing, area, stack-up, resistance distribution density D, etc.) to verify whether the design meets manufacturing process requirements and ensures that all design elements conform to the manufacturer's specified dimensions and spacing rules to avoid potential manufacturing problems. Layout checking compares the netlist of the original circuit diagram with the netlist of the circuit diagram extracted from the layout to ensure consistency and prevent design errors or deviations. Electrical rule checking checks for the presence of circuits, short circuits, etc.

[0096] In this example, further in step S2, the test structure designed in the final output of step S1 can be simulated and tested using a corresponding process processing model to obtain the resistance data corresponding to the test structure. This process processing model can simulate the actual manufacturing process (including mask fabrication, deposition, photolithography, etching, chemical mechanical polishing, etc.) of fabricating a series of test structures (i.e., resistors with different sizes and resistance distribution densities) on a wafer, and provide detailed simulation results for further simulation testing of the resistors formed by the process simulation.

[0097] In another example, in step S2, the resistance data corresponding to the test structure designed in step S1 is obtained by sequentially performing a Tape out (tape-out, pilot production) step and a wafer test step. The Tape out step is used to transform the final layout data file provided in step S1 into an actual wafer product through a series of process steps, much like an assembly line. The wafer test step is used to test the wafer product produced in the Tape out step, thereby obtaining the resistance data corresponding to the test structure designed in step S1.

[0098] In other words, the resistance data in step S2 can be obtained through simulation testing or through actual product testing. Regardless of the method, it is necessary to test and collect current data at different test temperatures T and different test voltages V to obtain the required resistance data.

[0099] It should be noted that in the above simulation test or actual wafer test process, the basic test parameters can remain unchanged. However, due to the difference in the resistance distribution density D of the resistors, the spacing of the test pads may change. Therefore, the automation script needs to be updated to ensure that the test proceeds smoothly.

[0100] In step S3, the basic resistance model is established: R = R sh ·f(SQ)·f(T,D)·f(V,D)·f(D). Where R is the corrected resistance value of the resistor. sh For a sheet resistor at a specific temperature (e.g., room temperature, such as 25°C) and a specific voltage (e.g., 0V), f(SQ) is a correction function for the resistor length L and width W, used to correct the influence of the resistor length L and resistor width W on the resistor value R; f(T,D) is a correction function for the test temperature T and resistance distribution density D, used to correct the combined influence of resistance distribution density D and test temperature T on the resistor value R, as well as the influence of test temperature T alone on the resistor value R. Therefore, its function expression contains interaction terms that cannot be decomposed into f(T)·f(D) and independent terms that can be decomposed into f(T); f(V,D) is a correction function for the test voltage. The correction functions for voltage V and resistance distribution density D are used to correct the combined effect of resistance distribution density D and test voltage V on the resistor value R, as well as the effect of test voltage V alone on the resistor value R. Therefore, its function expression contains interaction terms that cannot be decomposed into f(V)·f(D) and independent terms that can be decomposed into f(V). f(D) is a correction function for resistance distribution density D, used to correct the effect of resistance distribution density D alone on the resistor value R. Thus, appropriate function expressions are selected for each correction function f(SQ), f(T,D), f(V,D), and f(D) according to the actual resistor design (such as device density and size differences).

[0101] In one example, the basic resistance model established in step S3 is: R = Rsh·f(SQ)·f(T,D)·f(V,D)·f(D), and the resistance model further includes at least one of the following (1) to (4):

[0102]

[0103]

[0104]

[0105]

[0106] Where R is the corrected resistance value, R sh For a sheet resistor, W is the resistor width, L is the resistor length, ΔW is the offset of the resistor width, ΔL is the offset of the resistor length, D is the resistance distribution density, AH, J, K, XZ, a, b, tc1r and rvc are all parameter adjustment constants, T is the test temperature, V is the test voltage, and T0 is the room temperature (e.g., 25℃).

[0107] In one example,

[0108] It should be noted that the function expressions of the correction functions f(SQ), f(T,D), f(V,D), and f(D) in the above-described resistance model are merely illustrative examples and do not imply that the function expressions of f(SQ), f(T,D), f(V,D), and f(D) in the resistance model of the present invention are limited to the above-described forms. In other embodiments of the present invention, at least one of the correction functions f(SQ), f(T,D), f(V,D), and f(D) in the resistance model may adopt the corresponding function expressions described above. Alternatively, the function expressions of at least one of the correction functions f(SQ), f(T,D), f(V,D), and f(D) in the resistance model may be adaptively modified to a form different from the corresponding function expressions described above if step S4 and / or step S5 fails.

[0109] In step S4, corresponding resistance data can be selected from the resistance data obtained in step S2 to perform curve fitting on each correction function f(SQ), f(T,D), f(V,D), and f(D), thereby obtaining the fitted values ​​of the parameter constants AH, J, K, XZ, a, b, tc1r, and rvc in each correction function. This yields a resistance model that meets the fitting accuracy requirements.

[0110] It should also be noted that in step S4, if any fitting fails (i.e., the difference between the fitted curve and the selected resistance data is too large, or the selected resistance data deviates significantly from the fitted curve), the process can return to step S2 to select other wafer resistance data for iterative fitting, or return to step S3 to modify the expression of the correction function, thereby ensuring that a fitted curve with a smaller difference from the resistance data can be fitted in the end. For example, J and K can be equal to 1 or -1, or equal to 2 or -2, or any other suitable fitting value. When J and K are equal to -1, f(SQ) = (L + ΔL) / (W + ΔW).

[0111] In step S5, the resistance model obtained in step S4 is validated. The model validation in step S5 verifies the entire resistance model, which may include verifying whether there are jump points or abrupt changes in all dimensions of the entire resistance model at the corresponding process node, whether it is smooth, and whether the trend of changes in the electrical properties of the entire resistance model conforms to physical meaning, among other aspects. Through the model validation in step S6, the rationality, accuracy, and reliability of the entire resistance model, including the resistance model of this invention, can be ensured.

[0112] For example, in step S5, the rationality of the changing trend of the RD curve corresponding to the resistance model obtained in step S4 can be confirmed according to the model verification rule (QA rule). If it is found that the changing trend of the RD curve does not match the resistance data obtained in step S2, it indicates that the resistance model obtained in step S4 has failed model verification. The process can return to step S3 to modify the function expression of at least one of the correction functions f(SQ), f(T,D), f(V,D), and f(D), or return to step S4 to perform parameter iterative fitting on the resistance model until the resistance model output in step S4 passes model verification. If the resistance model output in step S4 passes model verification, the resistance model can be released for subsequent use.

[0113] In step S5, considering that the higher the resistance distribution density D, the deeper the chemical mechanical polishing (CMP) process, the smaller the cross-sectional area of ​​the metal resistor, and the lower the resistance, a model verification rule can be added that the resistance value increases monotonically with the increase of the resistance distribution density.

[0114] For example, in step S5, the resistance model obtained in step S4 can also be used to calculate the resistance of each resistor in the test results and compare it with the corresponding resistance data to determine the error between the two. If the errors corresponding to the test structure are all distributed within the required range, then the resistance model passes the model verification.

[0115] Please combine Figure 2 , Figure 6 and Figure 7 In one application example, using Figure 2 The same test structure is designed as shown. The test structure includes resistors RT1 to RT5. RT1 to RT5 are all made of the same material, with a length L of 90 μm and a W of 1.2 μm. The resistance distribution densities of RT1 to RT5 are 30%, 40%, 50%, 60%, and 80%, respectively.

[0116] The existing resistance model (model_old) does not consider the influence of the resistance distribution density D in the test structure on the resistance value R of each resistor. The calculated resistance values ​​for RT1 to RT5 are all 22.8 ohms. Furthermore, the error (error_old) between the calculated resistance values ​​of RT1, RT2, RT3, RT4, and RT5 and the corresponding resistance data is calculated. It can be seen that the existing resistance model (model_old) provides the best fit when D is 50%, with an error of 0%. However, it cannot be reconciled with resistance values ​​under other D conditions; the maximum error of the calculated resistance values ​​for RT1, RT2, RT4, and RT5 can reach 27%, indicating very poor fitting accuracy.

[0117] The resistance model (model_new) obtained by the modeling method in this embodiment takes into account the influence of the resistance distribution density D in the test structure on the resistance value R of each resistor. Therefore, the calculated resistance values ​​of RT1 to RT5 are no longer the same, and the error (error_new) between the calculated resistance values ​​of RT1, RT2, RT3, RT4, and RT5 and the corresponding resistance data are all within 1%, which significantly improves the fitting accuracy.

[0118] In addition, please refer to Figure 7 The trend of the RD fitting curve obtained by the modeling method in this embodiment is consistent with the trend of the resistance data data with respect to D, and each resistance data is close to the RD fitting curve.

[0119] In summary, the modeling method of the resistor model of the present invention considers the influence of resistance distribution density in the test key design stage (TestKeydesign, i.e., step S1) and designs resistors with different resistance distribution densities. Furthermore, in the model fitting stage (Model fitting, i.e., step S4), a correction function related to the resistance distribution density D is introduced, which can correct the resistor model and thus improve the fitting accuracy of the small-size resistor model.

[0120] Based on the same inventive concept, please refer to Figure 8 An embodiment of the present invention also provides a modeling system for a resistance model, which can implement the modeling method for the resistance model of the present invention. The modeling system includes:

[0121] The resistor design unit 11 is used to implement step S1 in the modeling method of the resistor model of the present invention, that is, the resistor design unit 11 is configured to design multiple resistors with different resistance distribution densities to form the required test structure.

[0122] The data acquisition unit 12 is used to implement step S2 in the modeling method of the resistance model of the present invention, that is, the data acquisition unit 12 is configured to acquire the resistance data corresponding to the test structure designed by the resistance design unit.

[0123] Modeling unit 13 is used to implement step S3 in the modeling method of the resistance model of the present invention, that is, the modeling unit 13 is configured to establish the basic resistance model R = Rsh·f(SQ)·f(T,D)·f(V,D)·f(D), where R is the corrected resistance value, R sh For a sheet resistor, f(SQ) is a correction function for the resistor length L and width W, f(T,D) is a correction function for the test temperature T and resistance distribution density D, f(V,D) is a correction function for the test voltage V and resistance distribution density D, and f(D) is a correction function for the resistance distribution density D.

[0124] The parameter fitting unit 14 is used to implement step S4 in the modeling method of the resistance model of the present invention, that is, it is configured to use the resistance data of the data acquisition unit 12 to perform curve fitting to obtain the expression of each correction function in the resistance model established by the modeling unit 13 and the parameter adjustment constant in the expression, so as to obtain the required resistance model.

[0125] Wherein, the correction function expression obtained by the modeling unit 13 or the parameter fitting unit 14 includes at least one of the following (1) to (4):

[0126]

[0127]

[0128]

[0129]

[0130] Where W is the resistor width, L is the resistor length, ΔW is the offset of the resistor width, ΔL is the offset of the resistor length, D is the resistance distribution density, AH, J, K, XZ, a, b, tc1r and rvc are all parameter adjustment constants, T is the test temperature, V is the test voltage, and T0 is the room temperature (e.g., 25℃).

[0131] In one example,

[0132] Optionally, the resistor design unit 11 uses standard resistor elements and designs multiple resistors in an increasing manner with increasing resistance distribution density to form at least part of the test structure.

[0133] Optionally, the resistor design unit 11 uses resistor elements of the same material but different sizes to design multiple resistors with different resistance distribution densities, thereby forming at least part of the test structure.

[0134] Optionally, each resistive element in the test structure designed by the resistor design unit 11 is in the shape of a strip or a block.

[0135] Optionally, the modeling system for the resistance model in this embodiment further includes a model verification unit 15, which is used to implement step S5 in the modeling method for the resistance model of the present invention. That is, the model verification unit 15 is configured to perform model verification on the resistance model output by the parameter fitting unit 14. When the resistance model fails the verification by the model verification unit 15, the parameter fitting unit 14 performs parameter iterative fitting on the resistance model, or the modeling unit 13 modifies the function expression of at least one of the correction functions f(SQ), f(T,D), f(V,D), and f(D) of the resistance model it constructs.

[0136] It is worth noting that the verification of the resistor model by the model verification unit 15 may also include: verifying whether there are jump points or abrupt changes in all dimensions of the entire resistor model at the corresponding process node, whether it is smooth, and whether the trend of the change of the electrical properties of the entire resistor model conforms to the physical meaning, etc. Through the model verification by the model verification unit 15, the rationality, accuracy and reliability of the resistor model including the present invention can be ensured.

[0137] It should be understood that the resistance design unit 11, data acquisition unit 12, modeling unit 13, parameter fitting unit 14 and model verification unit 15 in the modeling system of the resistance model of the present invention can be combined into one device, or any one of the units can be split into multiple devices, or at least part of the function of one unit can be combined with at least part of the function of another unit and implemented in one device.

[0138] Furthermore, at least one of the resistor design unit 11, data acquisition unit 12, modeling unit 13, parameter fitting unit 14, and model verification unit 15 in the resistor model modeling system of this embodiment can be at least partially implemented as a hardware circuit, such as a field-programmable gate array (FPGA), a programmable logic array (PLA), a system-on-a-chip, a system-on-a-substrate, a system-on-package, an application-specific integrated circuit (ASIC), or can be implemented in hardware or firmware in any other reasonable way of integrating or packaging the circuit, or in a suitable combination of software, hardware, and firmware implementation methods.

[0139] Alternatively, at least one of the resistor design unit 11, data acquisition unit 12, modeling unit 13, parameter fitting unit 14, and model verification unit 15 in the resistor model modeling system of this embodiment can be at least partially implemented as a computer program module. When the program is run by a computer, it can perform the functions of the corresponding module and can be upgraded.

[0140] In summary, the modeling method and system for the resistor model of the present invention can consider the influence of the resistance distribution density D in the constructed resistor model, and use the correction functions f(T,D), f(V,D), and f(D) with respect to the resistance distribution density D as key fitting parameters to correct the resistance model, thereby correcting the influence of the resistance distribution density on the resistor value R. The corrected resistor model is more complete and accurate, which can ensure the accuracy and reliability of subsequent integrated circuit design and simulation, and help engineers optimize the design and process of integrated circuits, thereby improving the design efficiency and actual production efficiency of integrated circuits.

[0141] Based on the same inventive concept, an embodiment of the present invention also provides a resistance model, which includes R = Rsh·f(SQ)·f(T,D)·f(V,D)·f(D), and the resistance model further includes at least one of the following items (1) to (4):

[0142]

[0143]

[0144]

[0145]

[0146] Where R is the corrected resistance value of the resistor, R sh Let f(SQ) be the sheet resistance of the resistor, f(SQ) be a correction function for the resistance length L and width W, f(T,D) be a correction function for the test temperature T and resistance distribution density D, f(V,D) be a correction function for the test voltage V and resistance distribution density D, and f(D) be a correction function for the resistance distribution density D; W is the resistance width of the standard resistor element corresponding to the resistor, L is the resistance length of the standard resistor element, ΔW is the offset of the resistance width of the resistor element in the resistor, ΔL is the offset of the resistance length of the resistor element in the resistor, D is the resistance distribution density of the resistor, AH, J, K, XZ, a, b, tc1r, and rvc are all parameter adjustment constants, T is the test temperature, V is the test voltage, and T0 is the room temperature (e.g., 25°C).

[0147] Based on the same inventive concept, the present invention also provides a readable storage medium for storing a computer program or instructions, which, when executed by a processor, implement the modeling method for the resistance model as described in the present invention.

[0148] The readable storage medium can be a tangible device capable of holding and storing instructions used by an instruction execution device, such as, but not limited to, electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples of the readable storage medium (a non-exhaustive list) include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination thereof. The computer program described herein can be downloaded from the readable storage medium to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. Each computing / processing device's network adapter card or network interface receives the computer program from the network and forwards it for storage in a readable storage medium within the respective computing / processing device. The computer program used to perform the operations of this invention can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as "C" or similar languages. The computer program can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuits, such as programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), are personalized by utilizing state information from a computer program. These electronic circuits can execute computer-readable program instructions, thereby realizing various aspects of the present invention.

[0149] Various aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, systems, and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by a computer program. These computer programs can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. These computer programs can also be stored in a readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the readable storage medium storing the computer program comprises an article of manufacture including instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams.

[0150] A computer program may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the computer program executing on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0151] In summary, the resistor model, modeling method, modeling system, and readable storage medium of this invention consider the influence of resistance distribution density D in the constructed resistor model. The model is modified using correction functions f(T,D) for test temperature T and resistance distribution density D, f(V,D) for test voltage V and resistance distribution density D, and f(D) for resistance distribution density D as key fitting parameters. This corrects the influence of resistance distribution density on resistance, resulting in a more complete and accurate resistor model. This ensures the accuracy and reliability of subsequent integrated circuit design and simulation, helping engineers optimize integrated circuit design and processes, and improving integrated circuit design efficiency and actual production efficiency.

[0152] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A modeling method for a resistance model, characterized in that, Includes the following steps: S1, Design multiple resistors with different resistance distribution densities to form a test structure; S2, Obtain the resistance data corresponding to the test structure; S3, Establish the basic resistance model R = R sh ·f(SQ)·f(T,D)·f(V,D)·f(D), where R is the corrected resistance value, R sh For a sheet resistor, f(SQ) is a correction function for the resistor length L and width W, f(T,D) is a correction function for the test temperature T and resistance distribution density D, f(V,D) is a correction function for the test voltage V and resistance distribution density D, and f(D) is a correction function for the resistance distribution density D. S4. Using the resistance data, curve fitting is performed to obtain the expressions for each of the correction functions, thereby obtaining the required resistance model.

2. The modeling method as described in claim 1, characterized in that, In step S1, the test structure includes at least one of the following (1) to (4): (1) The resistance distribution density of the resistors in the test structure increases; (2) At least one resistor in the test structure comprises n standard resistor elements of the same size and with equal spacing, and the formula for calculating the resistance distribution density D of the resistor is: D = W / (W + W space ) or D = W / (W + weight·W space ) or D = n·S R / S OD , Where W is the resistance width of the standard resistor element, and L is the resistance length of the standard resistor element. space The spacing between adjacent standard resistor elements in the resistor is S, where weight represents the weight value. R =W·L,S OD Let n be the total area of ​​the resistor, where n ≥ 1 and is an integer; (3) At least one resistor in the test structure comprises n resistive elements R1 to R2 of different sizes. n The formula for calculating the resistance distribution density D of the resistor is: Among them, S Rk R is the k-th resistive element in the resistor. k The area, S Rk =(W+ΔW) k )·(L+ΔL k ), ΔW k For R k The offset of the resistor width relative to W, ΔL k For R k The offset of the resistor length relative to L, S OD Let n be the total area of ​​the resistor, where n ≥ 1 and is an integer; (4) The resistive elements in each of the resistors are in the shape of strips or blocks.

3. The modeling method as described in claim 1, characterized in that, In step S2, the resistance data corresponding to the test structure is obtained by fabricating the test structure on the wafer and performing wafer testing, and / or the test structure is simulated and tested using a corresponding process processing model to obtain the resistance data corresponding to the test structure.

4. The modeling method as described in claim 3, characterized in that, In step S4, if the difference between the fitting result and the resistance data is too large, return to step S2 to obtain new resistance data for fitting. And / or, after step S4, step S5 is further included: performing model verification on the resistance model; if the resistance model fails model verification, then returning to step S3 to modify the expression of at least one of the correction functions in the resistance model, or returning to step S4 to iteratively fit the parameter constants in the expression of at least one of the correction functions in the resistance model until the resistance model passes verification.

5. The modeling method according to any one of claims 1-4, characterized in that, The correction function expression obtained in step S4 or step S5 includes at least one of the following (1) to (4): (1) (2) (3) (4) Wherein, W is the resistance width of the standard resistor element corresponding to the resistor, L is the resistance length of the standard resistor element, ΔW is the offset of the resistance width of the resistor element in the resistor, ΔL is the offset of the resistance length of the resistor element, D is the resistance distribution density of the resistor, AH, J, K, M, XZ, a, b, tc1r and rvc are all parameter adjustment constants, T is the test temperature, V is the test voltage, and T0 is the room temperature.

6. A modeling system for a resistance model, characterized in that, include: A resistor design unit is configured to design multiple resistors with different resistance distribution densities to form a test structure; A data acquisition unit is configured to acquire resistance data corresponding to the test structure designed by the resistance design unit. Modeling unit, configured to establish the basic resistance model R = R sh ·f(SQ)·f(T,D)·f(V,D)·f(D), where R is the corrected resistance value, R sh For a sheet resistor, f(SQ) is a correction function for the resistor length L and width W, f(T,D) is a correction function for the test temperature T and resistance distribution density D, f(V,D) is a correction function for the test voltage V and resistance distribution density D, and f(D) is a correction function for the resistance distribution density D. The parameter fitting unit is configured to perform curve fitting using the resistance data to derive expressions for each of the correction functions, thereby obtaining the desired resistance model.

7. The modeling system as described in claim 6, characterized in that, It also includes at least one of the following (1) to (9): (1) The resistor design unit uses standard resistor elements and designs multiple resistors in a manner that increases the resistance distribution density, thereby forming at least part of the test structure; (2) The resistor design unit uses resistor elements of different sizes to design multiple resistors with different resistance distribution densities, thereby forming at least part of the test structure; (3) The resistive elements in each resistor in the test structure are all strip-shaped or block-shaped; (4) The resistance distribution density of the resistors in the test structure designed by the resistance design unit increases progressively; (5) At least one resistor in the test structure designed by the resistor design unit comprises n standard resistor elements of the same size and with equal spacing, and the formula for calculating the resistance distribution density D of the resistor is: D = W / (W + W space ) or D = W / (W + weight·W space ) or D = n·S R / S OD , Where W is the resistance width of the standard resistor element, and L is the resistance length of the standard resistor element. space The spacing between adjacent standard resistor elements in the resistor is S, where weight represents the weight value. R =W·L,S OD Let n be the total area of ​​the resistor, where n ≥ 1 and is an integer; (6) At least one resistor in the test structure designed by the resistor design unit includes n resistor elements R1 to R2 of different sizes. n The formula for calculating the resistance distribution density D of the resistor is: Among them, S Rk R is the k-th resistive element in the resistor. k The area, S Rk =(W+ΔW) k )·(L+ΔL k ), ΔW k For R k The offset of the resistor width relative to W, ΔL k For R k The offset of the resistor length relative to L, S OD Let n be the total area of ​​the resistor, where n ≥ 1 and is an integer; (7) The data acquisition unit acquires the resistance data corresponding to the test structure by acquiring the wafer test data of the wafer where the test structure is located, and / or, the data acquisition unit performs process simulation processing and simulation testing on the test structure through the corresponding process processing model to acquire the resistance data corresponding to the test structure. (8) When the difference between the curve fitting result and the resistance data is too large, the parameter fitting unit causes the data acquisition unit to provide new resistance data for curve fitting. (9) The modeling system further includes a model verification unit configured to perform model verification on the resistance model; when the resistance model fails the verification by the model verification unit, the parameter fitting unit iteratively fits the parameter constant in the expression of at least one of the correction functions in the resistance model, or the modeling unit modifies the expression of at least one of the correction functions in the resistance model.

8. The modeling system as described in claim 6 or 7, characterized in that, The correction function expression obtained by the modeling unit or the parameter fitting unit includes at least one of the following (1) to (4): (1) (2) (3) (4) Wherein, W is the resistance width of the standard resistor element corresponding to the resistor, L is the resistance length of the standard resistor element, ΔW is the offset of the resistance width of the resistor element in the resistor, ΔL is the offset of the resistance length of the resistor element, D is the resistance distribution density of the resistor, AH, J, K, M, XZ, a, b, tc1r and rvc are all parameter adjustment constants, T is the test temperature, V is the test voltage, and T0 is the room temperature.

9. A readable storage medium, characterized in that, The readable storage medium is used to store a computer program or instructions, which, when executed by a processor, implement the modeling method of the resistance model as described in any one of claims 1-5.

10. A resistance model, characterized in that, The resistance model is R = R sh ·f(SQ)·f(T,D)·f(V,D)·f(D), and further includes at least one of the following (1) to (4): (1) (2) (3) (4) Where R is the corrected resistance value, R sh For a sheet resistor, f(SQ) is a correction function for the resistor length L and width W, f(T,D) is a correction function for the test temperature T and resistance distribution density D, f(V,D) is a correction function for the test voltage V and resistance distribution density D, and f(D) is a correction function for the resistance distribution density D. W is the resistance width of the standard resistor element corresponding to the resistor, L is the resistance length of the standard resistor element, ΔW is the offset of the resistance width of the resistor element in the resistor, ΔL is the offset of the resistance length of the resistor element, D is the resistance distribution density of the resistor, AH, J, K, M, XZ, a, b, tc1r and rvc are all parameter adjustment constants, T is the test temperature, V is the test voltage, and T0 is the room temperature.

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