Display panel and driving method

Abstract

The application provides a display panel and a driving method. A pixel circuit is located in a display area, and a selection circuit is located in a non-display area. The pixel circuit comprises a driving module and a voltage writing module. A first end of the voltage writing module is electrically connected with a signal transmission line. A second end of the voltage writing module is electrically connected with a first control end of the driving module. A control end of the voltage writing module is connected with a second gate signal. The second gate signal comprises a first conduction level and a second conduction level. In a first stage, the voltage writing modules in a plurality of pixel circuits are simultaneously turned on in response to the first conduction level, and a first reset voltage is simultaneously transmitted to the first control end of the driving module. In a third stage, the voltage writing modules in the plurality of pixel circuits are sequentially turned on in response to the second conduction level, and a data voltage is sequentially transmitted to the first control end of the driving module. The application can reduce the number of signal lines and the number of transistors in the pixel circuit by transmitting two signals at different times through the selection circuit, and can improve PPI.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and driving method. Background Technology

[0002] Organic light-emitting diode (OLED) and flat panel display devices based on light-emitting diode (LED) technologies are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body and wide range of applications, becoming the mainstream of display devices.

[0003] However, the performance of current OLED display panels needs improvement. Summary of the Invention

[0004] In order to overcome the technical problems mentioned in the above technical background, this application provides a display panel and a driving method, which aims to improve the performance of the display panel.

[0005] This application provides a display panel, including a display area and a non-display area surrounding at least a portion of the display area. The display panel includes pixel circuits and selection circuits. The pixel circuits are located in the display area, and the selection circuits are located in the non-display area. A selection circuit is electrically connected to multiple pixel circuits via a signal transmission line.

[0006] The pixel circuit includes a driving module and a voltage writing module. The first end of the voltage writing module is electrically connected to the signal transmission line, and the second end of the voltage writing module is electrically connected to the first control end of the driving module. The control end of the voltage writing module is connected to a second gate signal, which includes a first conduction level and a second conduction level. In the first stage, the selection circuit transmits the first reset voltage to the first terminal of the voltage writing module through the signal transmission line. The voltage writing modules in the multiple pixel circuits respond to the first conduction level and simultaneously conduct, transmitting the first reset voltage to the first control terminal of the drive module at the same time. In the third stage, the selection circuit transmits the data voltage to the first terminal of the voltage writing module through the signal transmission line. The voltage writing modules in the multiple pixel circuits respond to the second conduction level and turn on in sequence, transmitting the data voltage to the first control terminal of the drive module in sequence. The first phase precedes the third phase.

[0007] In one specific embodiment, the pixel circuit further includes a coupling module and a light-emitting device. The first end of the coupling module is electrically connected to the first control end of the driving module, the second end of the coupling module is electrically connected to the first end of the driving module, the second end of the driving module is electrically connected to the first power line, the first end of the light-emitting device is electrically connected to the first end of the driving module, and the second end of the light-emitting device is electrically connected to the second power line. In the first stage, the first power line transmits the second power voltage, and the second power line transmits the third power voltage. In the second stage, the first power line transmits the first power voltage, the voltage value of the first power voltage is greater than the voltage value of the second power voltage, the first power voltage charges the first end of the drive module, and performs threshold voltage compensation on the drive module. The second phase lies between the first and third phases; Furthermore, the coupling module includes a second capacitor, the first terminal of which is electrically connected to the first control terminal of the drive module, and the second terminal of which is electrically connected to the first terminal of the drive module.

[0008] In one specific embodiment, the first conduction level covers the second power supply voltage, and the start time of the first conduction level is the same as the start time of the second power supply voltage. Furthermore, the pulse width of the first conduction level is greater than the pulse width of the second conduction level, and the first conduction level is located before the second conduction level; Furthermore, the first conduction levels of the second gate signals connected to multiple pixel circuits are set to overlap; Furthermore, along the extension direction of the signal transmission line, the second conduction level of the second gate signal connected to multiple pixel circuits is shifted, wherein the multiple pixel circuits are electrically connected to the same selection circuit.

[0009] In one specific embodiment, the pixel circuit further includes a reset module, a first terminal of the reset module is connected to a second reset voltage, a second terminal of the reset module is electrically connected to the first terminal of the drive module, and a control terminal of the reset module is connected to a first gate signal. In the first stage, the reset module responds to the first gate signal and transmits the second reset voltage to the first terminal of the drive module; Furthermore, multiple pixel circuits are connected to the same first gate signal; Furthermore, the pulse width of the first gate signal's on-level is the same as the pulse width of the second power supply voltage; Furthermore, the first turn-on level of the second gate signal overrides the turn-on level of the first gate signal; Furthermore, the reset module includes a third transistor, the first terminal of the third transistor is connected to a second reset voltage, the second terminal of the third transistor is electrically connected to the first terminal of the drive module, and the gate of the third transistor is connected to a first gate signal.

[0010] In one specific embodiment, the pixel circuit further includes a storage module, a first terminal of which is connected to a sustaining voltage, and a second terminal of which is electrically connected to the first terminal of the driving module. Furthermore, the storage module includes a first capacitor, the first terminal of the first capacitor is connected to a sustaining voltage, and the second terminal of the first capacitor is electrically connected to the first terminal of the drive module. Furthermore, in the fourth stage, the second power line transmits the fourth power voltage, the voltage value of the third power voltage is greater than the voltage value of the fourth power voltage, and the voltage value of the first power voltage is greater than the voltage value of the fourth power voltage. Furthermore, the third power supply voltage covers the first, second, and third stages, while the fourth stage is located after the third stage.

[0011] In one specific embodiment, the drive module includes a second control terminal, which is electrically connected to the first terminal of the drive module; Furthermore, the driving module includes a first transistor, which includes a first gate and a second gate. The first gate of the first transistor serves as a first control terminal of the driving module, the second gate of the first transistor serves as a second control terminal of the driving module, the first electrode of the first transistor serves as a first terminal of the driving module, and the second electrode of the first transistor serves as a second terminal of the driving module. One of the first gate and the second gate of the first transistor is a top gate, and the other is a bottom gate. The voltage writing module includes a second transistor, whose first electrode serves as a first terminal of the voltage writing module, the second electrode of the second transistor serves as a second terminal of the voltage writing module, and the gate of the second transistor serves as a control terminal of the voltage writing module. Furthermore, the first transistor is an N-type transistor, and the semiconductor material of the first transistor includes metal oxide.

[0012] In one specific embodiment, the selection circuit includes a selection module, a first terminal of the selection module is connected to a first reset voltage, a second terminal of the selection module is connected to a data voltage, a third terminal of the selection module is electrically connected to a signal transmission line, a first control terminal of the selection module is connected to a first control signal, and a second control terminal of the selection module is connected to a second control signal. In the first and second stages, the selection module responds to the first control signal and turns on, transmitting the first reset voltage to the signal transmission line; In the third stage, the selected module responds to the second control signal and turns on, transmitting the data voltage to the signal transmission line; Furthermore, in a frame, the conduction level of the first control signal is before the conduction level of the second control signal, and the conduction levels of the first control signal and the second control signal do not overlap; Furthermore, the conduction level of the first control signal covers the first conduction level of the second gate signal, and the conduction level of the second control signal covers the second conduction level of the second gate signal.

[0013] In one specific embodiment, the selection module includes a fourth transistor and a fifth transistor. The first terminal of the fourth transistor serves as the first terminal of the selection module, the first terminal of the fifth transistor serves as the second terminal of the selection module, the gate of the fourth transistor serves as the first control terminal of the selection module, the gate of the fifth transistor serves as the second control terminal of the selection module, and the second terminals of the fourth transistor and the fifth transistor are electrically connected to form the third terminal of the selection module.

[0014] This application embodiment also provides a driving method for driving the pixel circuit and selection circuit in the above-mentioned display panel, the method including: In the first stage, the selection circuit transmits the first reset voltage to the first terminal of the voltage writing module through the signal transmission line. The voltage writing modules in the multiple pixel circuits simultaneously turn on in response to the first conduction level of the second gate signal, and simultaneously transmit the first reset voltage to the first control terminal of the drive module. In the third stage, the selection circuit transmits the data voltage to the first terminal of the voltage writing module through the signal transmission line. The voltage writing modules in the multiple pixel circuits are turned on in sequence in response to the second conduction level of the second gate signal, and transmit the data voltage to the first control terminal of the driving module in sequence. The first phase precedes the third phase.

[0015] In one specific embodiment, the selection circuit includes a selection module, a first terminal of the selection module is connected to a first reset voltage, a second terminal of the selection module is connected to a data voltage, a third terminal of the selection module is electrically connected to a signal transmission line, a first control terminal of the selection module is connected to a first control signal, and a second control terminal of the selection module is connected to a second control signal. The method also includes: In the first and second stages, the selection module responds to the first control signal and turns on, transmitting the first reset voltage to the signal transmission line; In the third stage, the selected module responds to the second control signal and turns on, transmitting the data voltage to the signal transmission line; The second phase lies between the first and third phases.

[0016] The technical solution provided in this application embodiment reduces the number of signal lines and transistors in the pixel circuit by selecting the circuit to transmit two signals in a time-division manner, thereby saving layout space and improving PPI.

[0017] It should be understood that the description in this section is not intended to identify key or important features of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a pixel circuit in the prior art; Figure 2 This is another pixel circuit in the prior art; Figure 3 for Figure 2 The timing diagram of the pixel circuit shown is as follows; Figure 4 This is a schematic diagram of a display panel structure according to an embodiment of this application; Figure 5 This is a pixel circuit architecture diagram according to an embodiment of this application; Figure 6 This is a pixel circuit structure diagram according to an embodiment of this application; Figure 7 This is another pixel circuit architecture diagram according to an embodiment of this application; Figure 8 This is another pixel circuit structure diagram according to an embodiment of this application; Figure 9 This is a selection circuit architecture diagram according to an embodiment of this application; Figure 10 This is a circuit structure diagram of one embodiment of the present application; Figure 11 This is a driving timing diagram according to an embodiment of this application. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0022] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. It should be noted that, unless otherwise specified, different features in the embodiments of this application can be combined with each other.

[0023] For ease of understanding, the accompanying diagram shows the mutually orthogonal X-axis, Y-axis, and Z-axis. The direction along the X-axis is called the X-direction, the direction along the Y-axis is called the Y-direction, and the direction along the Z-axis is called the Z-direction. The Z-direction is the normal direction relative to the plane containing the X and Y directions. Furthermore, a view where various elements are observed parallel to the plane containing the X and Y directions is called a top view. Alternatively, the planes in the X and Y directions can be planes parallel to the display surface of the display panel, and the Z-direction can be a direction parallel to the thickness direction of the display panel.

[0024] For certain elements, terms such as "above" or "over" are sometimes used when describing the position of an element located in the Z direction, and "below" or "under" are used when describing the position of an element located in the opposite direction. Furthermore, when using terms such as "above," "over," "below," "under," and "relative" to define the positional relationship between two elements, this includes not only the state where the two elements are directly connected, but also the state where the two elements are separated by a gap or other elements. Moreover, the terms "first," "second," and "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance or order. At least one may include one or more. At least part may include part or all. The first direction and the second direction intersect, for example, they may be perpendicular. At least one may include one or more. Connections may include direct connections or indirect connections. Equal or identical means equal or identical within a reasonable range of errors such as manufacturing errors, process errors, and measurement errors. The transistor may be a P-type transistor or an N-type transistor. A P-type transistor is turned on when its gate is connected to a low level and turned off when its gate is connected to a high level. An N-type transistor is turned on when its gate is connected to a high level and turned off when its gate is connected to a low level.

[0025] With the continuous development of display panel technology, the types and methods of display panels are becoming increasingly diverse, and people's demands for display panels in various scenarios are also increasing. In a display panel, pixel circuits provide driving current to the light-emitting devices. The pixel circuits can be... Figure 1The pixel circuit shown is a typical 2T1C pixel circuit, including a driving transistor M1, a data writing transistor M2, a storage capacitor C, and a light-emitting device. The first terminal of the driving transistor M1 is connected to the power supply voltage Vdd, the second terminal of the driving transistor M1 is electrically connected to the anode of the light-emitting device, the cathode of the light-emitting device is connected to the power supply voltage VSS, the gate of the driving transistor M1 is electrically connected to the first terminal of the data writing transistor M2, the second terminal of the data writing transistor M2 is connected to the data voltage Vdata, and the gate of the data writing transistor M2 is connected to the first scan signal scan1. The first terminal of the storage capacitor C is electrically connected to the gate of the driving transistor M1, and the second terminal of the storage capacitor C is connected to the power supply voltage Vdd. The driving transistor M1 generates a driving current based on the data voltage Vdata at its gate to drive the light-emitting device to emit light.

[0026] However, the 2T1C pixel circuit lacks threshold compensation, resulting in poor display quality. Therefore, the 7T1C pixel circuit with threshold compensation was further developed, such as... Figure 2As shown, the pixel circuit 7T1C includes a driving transistor M1, a data writing transistor M2, a threshold compensation transistor M3, a gate reset transistor M4, a first light-emitting control transistor M5, a second light-emitting control transistor M6, an anode reset transistor M7, a storage capacitor C, and a light-emitting device. The first terminal of the first light-emitting control transistor M5 is connected to the power supply voltage Vdd. The second terminal of the first light-emitting control transistor M5 is electrically connected to the first terminal of the driving transistor M1. The second terminal of the driving transistor M1 is electrically connected to the first terminal of the second light-emitting control transistor M6. The second terminal of the second light-emitting control transistor M6 is electrically connected to the anode of the light-emitting device. The gates of both the first and second light-emitting control transistors are connected to the control signal em. The cathode of the light-emitting device is connected to the power supply voltage VSS. The first terminal of the data writing transistor M2 is connected to the data voltage Vdata. The second terminal of the data writing transistor M2 is electrically connected to the first terminal of the driving transistor M1. The gate of the data writing transistor M2 is connected to the first scan signal scan1. The first terminal of the threshold compensation transistor M3 is electrically connected to the gate of the driving transistor M1. The second terminal of threshold compensation transistor M3 is electrically connected to the second terminal of driving transistor M1. The gate of threshold compensation transistor M3 is connected to the first scan signal scan1. The first terminals of gate reset transistor M4 and anode reset transistor M7 are both connected to the reset voltage vref. The second terminal of gate reset transistor M4 is electrically connected to the gate of driving transistor M1. The second terminal of anode reset transistor M7 is electrically connected to the anode of the light-emitting device. The gate of gate reset transistor M4 is connected to the second scan signal scan2. The gate of anode reset transistor M7 is connected to the first scan signal scan1. The first terminal of storage capacitor C is electrically connected to the gate of driving transistor M1. The second terminal of storage capacitor C is connected to the power supply voltage vdd. Driving transistor M1 generates a driving current according to the data voltage vdata of its gate to drive the light-emitting device to emit light.

[0027] Figure 3 for Figure 2 The timing diagram of the pixel circuit shown is illustrated below. The operation process of the pixel circuit is described as follows: Initial stage P0: This stage is the light-emitting stage of the previous display frame. The second scan signal scan2 and the first scan signal scan1 are both at high level, the control signal em is at low level, the driving transistor M1, the first light-emitting control transistor M5, and the second light-emitting control transistor M6 are turned on, and the other transistors are turned off. The driving transistor M1 generates a driving current to drive the light-emitting device to emit light.

[0028] Reset Phase P1: Control signal em and the first scan signal scan1 are both high, the second scan signal scan2 is low, gate reset transistor M4 is turned on, the gate of driving transistor M1 is reset, and the potential V of the gate of driving transistor M1... G=vref; During the writing and compensation phase P2: the control signal em and the second scan signal scan2 are both high, the first scan signal scan1 is low, the anode reset transistor M7 is turned on, the anode of the light-emitting device is reset, and the anode potential V of the light-emitting device is... Anode =vref, the driving transistor M1, the data writing transistor M2, and the threshold compensation transistor M3 are turned on. The data voltage signal vdata passes sequentially through the data writing transistor M2, the driving transistor M1, and the threshold compensation transistor M3, charging the gate of the driving transistor M1 until the potential V of the gate of the driving transistor M1 is reached. G =vdata+Vth, and this potential is stored in the storage capacitor C.

[0029] Light-emitting stage P3: This stage is the light-emitting stage of the current display frame. The second scan signal scan2 and the first scan signal scan1 are both high, and the control signal em is low. Driving transistor M1, the first light-emitting control transistor M5, and the second light-emitting control transistor M6 are turned on, while the remaining transistors are turned off, driving the light-emitting device to emit light. At this time, the light-emitting current... I OLED =(1 / 2) μ Cox (W / L) [(vdata+Vth)-vdd-Vth] 2 =(1 / 2) μ Cox (W / L) (vdata-vdd) 2 Among them, (1 / 2) μ Cox (W / L) is a fixed constant.

[0030] However, the large number of transistors in the pixel circuit described above makes it difficult to meet users' demands for high PPI. Therefore, this application provides the following solution.

[0031] This application provides a display panel. Figure 4 This is a schematic diagram of a display panel structure according to an embodiment of this application, such as... Figure 4As shown, the display panel 400 includes a display area AA and a non-display area NA surrounding at least a portion of the display area AA. In this embodiment, the non-display area NA surrounds the entire display area AA. The display panel 400 includes pixel circuits 100 and selection circuits 200. The pixel circuits 100 are arranged in an array in the display area AA, with a first direction X as the row direction and a second direction Y as the column direction. The selection circuits 200 are located in the non-display area NA and are located in a border of the column direction of the display panel 400, preferably near the border of the driver chip IC, which can reduce the signal loss when the driver chip IC transmits signals to the selection circuits 200. The driver chip IC can transmit a first reset voltage Vini and a data voltage Vdata to the selection circuits 200 in a time-division multiplexing manner. The display panel 400 also includes signal transmission lines 300, which extend from the display area AA to the non-display area NA. One signal transmission line 300 is electrically connected to one column of pixel circuits 100, and one selection circuit 200 corresponds to one signal transmission line 300. One selection circuit 200 is electrically connected to one column of pixel circuits 100 through the signal transmission line 300. This embodiment transmits two signals in a time-division manner through a single signal line, which can reduce the number of signal lines and save layout space.

[0032] In one embodiment, Figure 5 This is a pixel circuit architecture diagram according to an embodiment of this application, such as... Figure 5 As shown, the pixel circuit 100 includes at least a driving module 101 and a voltage writing module 102. The driving module 101 is used to generate a driving current. The first end of the voltage writing module 102 is electrically connected to the signal transmission line 300. The second end of the voltage writing module 102 is electrically connected to the first control end of the driving module 101. The control end of the voltage writing module 102 is connected to a second gate signal S2. The second gate signal S2 includes a first conduction level and a second conduction level. Both the first conduction level and the second conduction level of the second gate signal S2 can control the voltage writing module 102 to conduct.

[0033] In this embodiment, each frame of the display panel includes multiple working stages, such as... Figure 11 As shown, In the first stage t1, the driver chip IC outputs a first reset voltage Vini to the selection circuit 200. The selection circuit 200 outputs the first reset voltage Vini to the signal transmission line 300, and transmits the first reset voltage Vini to the first terminal of the voltage writing module 102 through the signal transmission line 300. It should be noted that in this embodiment, the conduction start time and conduction end time of the voltage writing modules 102 of all pixel circuits 100 are the same in this stage. That is, the voltage writing modules 102 in all pixel circuits 100 are simultaneously turned on in response to the first conduction level of the second gate signal S2, and the conduction duration is the same. That is, the first conduction levels of the second gate signal S2 are overlapped. Within the same time, the voltage writing modules 102 in all pixel circuits 100 transmit the first reset voltage Vini to the first control terminal of the driver module 101 at the same time, realizing the full-screen initialization of the first control terminal of the driver module 101.

[0034] In the third stage t3, the driver chip IC outputs a data voltage Vdata to the selection circuit 200. The selection circuit 200 outputs the data voltage Vdata to the signal transmission line 300, which then transmits the data voltage Vdata to the first terminal of the voltage writing module 102. It should be noted that in this embodiment, the voltage writing modules 102 of all pixel circuits 100 are turned on row by row in this stage. That is, at any given time, only one row of pixel circuits 100 has its voltage writing module 102 turned on. The voltage writing modules 102 in multiple pixel circuits 100 in the same column are turned on sequentially in response to the second conduction level of the second gate signal S2. This means the second conduction level of the second gate signal S2 is shifted, and the data voltage Vdata is transmitted sequentially to the first control terminal of the driver module 101, thus realizing the row-by-row writing of the data voltage Vdata.

[0035] In this embodiment, the first stage t1 is located before the third stage t3. This embodiment uses a single voltage writing module 102 to transmit two voltage signals in a time-division multiplexing manner, which can save layout space and increase pixel density (PPI).

[0036] In one embodiment, reference continues... Figure 5 The pixel circuit 100 also includes a coupling module 105 and a light-emitting device D. A first end of the coupling module 105 is electrically connected to a first control terminal of the driving module 101, and a second end of the coupling module 105 is electrically connected to a first end of the driving module 101. The second end of the driving module 101 is electrically connected to a first power line ACVDD. A first end (anode) of the light-emitting device D is electrically connected to a first end of the driving module 101, and a second end (cathode) of the light-emitting device D is electrically connected to a second power line ACVSS. The light-emitting device D emits light in response to a driving current. In this embodiment, the light-emitting device D includes an OLED device, but it can also be other types of light-emitting devices.

[0037] Continue to refer to Figure 11 In the first stage t1, the first power line ACVDD transmits the second power supply voltage VDDL, and the second power line ACVSS transmits the third power supply voltage VSSH. The second power supply voltage VDDL can initialize the second terminal of the driver module 101, while the third power supply voltage VSSH can reduce the voltage difference between the first and second terminals of the light-emitting device D, making the voltage difference between the first and second terminals of the light-emitting device D less than the turn-on voltage of the light-emitting device D, thereby turning off the light-emitting device D. No additional structure is needed to control the on / off of the light-emitting path between the first power line ACVDD and the second power line ACVSS, which can save layout space and increase pixel density PPI.

[0038] In the second stage t2, the first power line ACVDD transmits the first power supply voltage VDDH. The voltage value of the first power supply voltage VDDH is greater than the voltage value of the second power supply voltage VDDL. The first power supply voltage VDDH charges the first terminal of the driving module 101, performing threshold voltage compensation on the driving module 101. The second stage t2 is located between the first stage t1 and the third stage t3, meaning the threshold voltage compensation process of the driving module 101 occurs before the data voltage Vdata writing process. These two processes are performed separately, allowing the threshold voltage compensation time of the driving module 101 to be unrestricted by the data voltage Vdata writing time, resulting in more sufficient threshold voltage compensation time and improving uniformity during high refresh rate displays. Furthermore, the first power supply voltage VDDH is a global signal, meaning all pixel circuits 100 are connected to the same first power supply voltage VDDH. Therefore, all pixel circuits 100 perform threshold voltage compensation simultaneously, saving compensation time and improving the working efficiency of the pixel circuits 100.

[0039] In one embodiment, the first conduction level of the second gate signal S2 covers the second power supply voltage VDDL, and the start time of the first conduction level of the second gate signal S2 is the same as the start time of the second power supply voltage VDDL, which is beneficial to improving the initialization effect of the first control terminal and the second terminal of the drive module 101.

[0040] In one embodiment, the pulse width of the first conduction level of the second gate signal S2 is greater than the pulse width of the second conduction level of the second gate signal S2, and the first conduction level is located before the second conduction level. The first conduction level covers the first stage t1 and the second stage t2, and the second conduction level is located in the third stage t3, so that the voltage writing module 102 is turned on in different stages, thereby realizing the separation of threshold voltage compensation and data voltage Vdata writing.

[0041] In one embodiment, reference continues... Figure 5The pixel circuit 100 also includes a reset module 103. The first terminal of the reset module 103 is connected to the second reset voltage Vref, the second terminal of the reset module 103 is electrically connected to the first terminal of the drive module 101, and the control terminal of the reset module 103 is connected to the first gate signal S1.

[0042] In this embodiment, reference Figure 11 The first gate signal S1 is a global signal, meaning that the first gate signal S1 connected to the reset module 103 of all pixel circuits 100 in the display panel is the same signal.

[0043] In the first stage t1, the reset module 103 in all pixel circuits 100 simultaneously turns on and off in response to the first gate signal S1, and transmits the second reset voltage Vref to the first terminal of the driving module 101 and the first terminal of the light-emitting device D, thereby achieving simultaneous initialization of the first terminal of all driving modules 101 and the first terminal of all light-emitting devices D, saving initialization time and improving the working efficiency of the pixel circuit 100.

[0044] Furthermore, the conduction level pulse width of the first gate signal S1 is the same as the pulse width of the second power supply voltage VDDL, and the first conduction level of the second gate signal S2 covers the conduction level of the first gate signal S1, so that the initialization of the first terminal, the second terminal and the first control terminal of the driving module 101 are all performed simultaneously.

[0045] In one embodiment, reference continues... Figure 5 The pixel circuit 100 also includes a storage module 104. The first end of the storage module 104 is connected to a sustaining voltage, and the second end of the storage module 104 is electrically connected to the first end of the driving module 101 for storing the data voltage Vdata and the threshold voltage of the driving module 101.

[0046] In the fourth stage t4, the second power line ACVSS transmits the fourth power voltage VSSL, the voltage value of the third power voltage VSSH is greater than the voltage value of the fourth power voltage VSSL, and the voltage value of the first power voltage VDDH is greater than the voltage value of the fourth power voltage VSSL. In this embodiment, the third power supply voltage VSSH covers the first stage t1, the second stage t2, and the third stage t3. The fourth stage t4 is located after the third stage t3. In the first stage t1, the second stage t2, and the third stage t3, since the voltage value of the third power supply voltage VSSH is greater than the voltage value of the fourth power supply voltage VSSL, the voltage difference between the first and second terminals of the light-emitting device D is small, and the current is small. This keeps the light-emitting device D in an off state and prevents it from being lit up, which is beneficial to improving the display effect.

[0047] In one embodiment, Figure 6 This is a pixel circuit structure diagram according to an embodiment of this application, such as... Figure 6 As shown, the driving module 101 includes a first transistor T1, the voltage writing module 102 includes a second transistor T2, the reset module 103 includes a third transistor T3, the storage module 104 includes a first capacitor Cst1, and the coupling module 105 includes a second capacitor Cst2. The first transistor T1 is an N-type transistor, and the semiconductor material of the first transistor T1 includes metal oxides, such as IGZO (indium gallium zinc oxide) or IZO (indium zinc oxide). The second transistor T2 and the third transistor T3 are both P-type transistors, and the semiconductor materials of the second transistor T2 and the third transistor T3 both include low-temperature polycrystalline silicon, such as p-Si.

[0048] Specifically, the second terminal of the first transistor T1 is electrically connected to the first power line ACVDD, the first terminal of the first transistor T1 is electrically connected to the anode of the light-emitting device D, the cathode of the light-emitting device D is electrically connected to the second power line ACVSS, the first terminal of the second transistor T2 is electrically connected to the signal transmission line 300, the second terminal of the second transistor T2 is electrically connected to the gate of the first transistor T1, and the gate of the second transistor T2 is connected to the second gate signal S2, the first terminal of the third transistor T3 is connected to the second reset voltage Vref, the second terminal of the third transistor T3 is electrically connected to the first terminal of the first transistor T1, and the gate of the third transistor T3 is connected to the first gate signal S1, the first terminal of the first capacitor Cst1 is connected to the sustaining voltage Vcom, the second terminal of the first capacitor Cst1 is electrically connected to the first terminal of the first transistor T1, the first terminal of the second capacitor Cst2 is electrically connected to the gate of the first transistor T1, and the second terminal of the second capacitor Cst2 is electrically connected to the first terminal of the first transistor T1. The sustaining voltage Vcom can be a fixed voltage or the voltage transmitted by the first power line ACVDD.

[0049] In this embodiment, the pixel circuit 100 requires only three transistors and two capacitors, which greatly reduces the space occupied by the pixel circuit 100 and improves the space utilization of the array layout, which is beneficial to increasing the pixel density (PPI). Furthermore, the pixel circuit 100 only requires one set of gate driving circuits, which facilitates reducing the bezel of the display panel 400 and improving yield.

[0050] In one embodiment, Figure 9 This is a selection circuit architecture diagram according to an embodiment of this application, such as... Figure 9 As shown, the selection circuit 200 includes a selection module 201. The first terminal of the selection module 201 is connected to the first reset voltage Vini, the second terminal of the selection module 201 is connected to the data voltage Vdata, the third terminal of the selection module 201 is electrically connected to the signal transmission line 300, the first control terminal of the selection module 201 is connected to the first control signal SW1, and the second control terminal of the selection module 201 is connected to the second control signal SW2.

[0051] refer to Figure 11 In the first stage t1 and the second stage t2, the selection module 201 responds to the first control signal SW1 and turns on, transmitting the first reset voltage Vini to the signal transmission line 300.

[0052] In the third stage t3, the selection module 201 responds to the second control signal SW2 and turns on, transmitting the data voltage Vdata to the signal transmission line 300.

[0053] In this embodiment, the selection circuit 200 enables the time-division output of two different signals, which reduces the space occupied by the pixel circuit 100, allowing the display area AA to accommodate more pixel circuits 100 and improve PPI.

[0054] In one embodiment, in a frame, the conduction level of the first control signal SW1 is ahead of the conduction level of the second control signal SW2, and the conduction levels of the first control signal SW1 and the second control signal SW2 do not overlap, which helps to avoid crosstalk between the data voltage Vdata and the first reset voltage Vini.

[0055] In one embodiment, the conduction level of the first control signal SW1 covers the first conduction level of the second gate signal S2, and the conduction level of the second control signal SW2 covers the second conduction level of the second gate signal S2, so that the first reset voltage Vini and the data voltage Vdata can be normally output to the gate of the first transistor T1, realizing the time-division transmission of two signals by one transistor.

[0056] In one embodiment, Figure 10 This is a selection circuit structure diagram according to an embodiment of this application, such as... Figure 10 As shown, the selection module 201 includes a fourth transistor T4 and a fifth transistor T5. The first terminal of the fourth transistor T4 serves as the first terminal of the selection module 201, and the first terminal of the fifth transistor T5 serves as the second terminal of the selection module 201. The gate of the fourth transistor T4 is connected to a first control signal SW1, and the gate of the fifth transistor T5 is connected to a second control signal SW2. The second terminals of both the fourth transistor T4 and the fifth transistor T5 are electrically connected to the signal transmission line 300. Both the fourth transistor T4 and the fifth transistor T5 are P-type transistors, and the semiconductor materials of both transistors include low-temperature polycrystalline silicon, such as p-Si.

[0057] Figure 11This is a driving timing diagram according to an embodiment of this application, where signal S2(1) represents the timing of the second gate signal S2 connected to the first row pixel circuit 100, and signal S2(n) represents the timing of the second gate signal S2 connected to the nth row pixel circuit 100. The timing of the second gate signal S2 between the first row pixel circuit 100 and the nth row pixel circuit 100 is omitted in the figure. The following is in conjunction with Figure 11 right Figure 6 and Figure 10 The working process of the circuit shown is described below: Phase 1 (t1): This is the initialization phase. The first power line ACVDD transmits the second power supply voltage VDDL, and the second power line ACVSS transmits the third power supply voltage VSSH. The first gate signal S1 and the first control signal SW1 are both low. The second gate signal S2 is at the first conduction level (low level), and the second control signal SW2 is high. The fourth transistor T4 is turned on, and the fifth transistor T5 is turned off. The first reset voltage Vini is transmitted to the signal transmission line 300. The second transistor T2 is turned on, and the first reset voltage Vini is transmitted to the gate of the first transistor T1, realizing the full-screen gate initialization of the first transistor T1. The gate potential of the first transistor T1 is V. g =Vini, the second power supply voltage VDDL initializes the second terminal of the full-screen first transistor T1, the third transistor T3 is turned on, and the second reset voltage Vref is transmitted to the first terminal of the first transistor T1 and the anode of the light-emitting device D, realizing the simultaneous initialization of the first terminal of the full-screen first transistor T1 and the anode of the light-emitting device D. The potential of the first terminal of the first transistor T1 is the same as the potential of the anode of the light-emitting device D. The potential of the first terminal of the first transistor T1 V s =Vref.

[0058] Phase 2 (t2): This is the threshold voltage compensation phase. The first gate signal S1 jumps to a high level, the third transistor T3 is turned off, the first power line ACVDD transmits the first power supply voltage VDDH, and the gate potential of the first transistor T1 remains at V. g =Vini, the first transistor T1 is turned on, and the first power supply voltage VDDH charges the first terminal of the first transistor T1 through the first transistor T1 to perform threshold voltage compensation until the first terminal potential V of the first transistor T1 is reached. s =Vini-Vth, the first transistor T1 stops conducting, and the threshold voltage compensation of the first transistor T1 in the whole screen is completed at the same time, where Vth is the threshold voltage of the first transistor T1.

[0059] Phase 3 (t3): This is the data writing phase. The first control signal SW1 is high, the second control signal SW2 is low, the fourth transistor T4 is off, and the fifth transistor T5 is on, transmitting the data voltage Vdata to signal transmission line 300. The second gate signal S2 becomes the second on-level (low level), and the second transistor T2 turns on row by row, transmitting the data voltage Vdata to the gate of the first transistor T1 row by row. The gate potential of the first transistor T1 becomes V... g =Vdata, the gate potential difference of the first transistor T1 is △V = Vdata - Vini. Due to the capacitive coupling effect, the potential of the first transistor T1 becomes V. s =Vini-Vth+k △V, further calculated to obtain V s =Vini-Vth+k (Vdata-Vini), the difference V between the gate potential and the first electrode potential of the first transistor T1. gs = Vdata - Vini + Vth - k (Vdata-Vini)=(1-k)(Vdata-Vini)+Vth, where k=C2 / (C1+C2).

[0060] Phase 4 (t4): This is the light-emitting phase. The first control signal SW1 is low, the second control signal SW2 is high, the second power line ACVSS transmits the fourth power supply voltage VSSL, the second gate signal S2 goes high, the second transistor T2 and the third transistor T3 are both off, the first transistor T1 is on, and the full-screen light-emitting device D emits light simultaneously. The light-emitting current is: I OLED =(1 / 2) μ Cox (W / L) (V gs -Vth) 2 =(1 / 2) μ Cox (W / L) [ (1-k)(Vdata-Vini)+Vth –Vth] 2 =(1 / 2) μ Cox (W / L) [(1-k)(Vdata-Vini)] 2 Since k = C2 / (C1 + C2), the final calculation is: I OLED =(1 / 2) μ Cox (W / L) [(C1 / (C1+C2))(Vdata-Vini)] 2 Among them, (1 / 2) μ Cox (W / L) is a fixed constant.

[0061] In one embodiment, Figure 7 This is another pixel circuit architecture diagram according to an embodiment of this application, such as... Figure 7 As shown, the drive module 101 includes a second control terminal, which is electrically connected to the first terminal of the drive module 101, which helps to maintain the stability of the drive module 101.

[0062] In one embodiment, Figure 8 This is another pixel circuit structure diagram according to an embodiment of this application, such as... Figure 8 As shown, the first transistor T1 includes a first gate and a second gate. The first gate of the first transistor T1 serves as the first control terminal of the driving module 101, and the second gate of the first transistor T1 serves as the second control terminal of the driving module 101. The second gate of the first transistor T1 is electrically connected to the first terminal of the first transistor T1. One of the first gate and the second gate of the first transistor T1 is a top gate, and the other is a bottom gate. In this embodiment, the first transistor T1 is an N-type transistor, and the semiconductor material of the first transistor T1 includes metal oxide. Therefore, when the second gate of the first transistor T1 serves as a bottom gate, it can act as a light-shielding layer of the semiconductor material, preventing threshold voltage shift in the first transistor T1 caused by light exposure.

[0063] In one embodiment, Figure 11 The driver timing also applies. Figure 8 The pixel circuit 100 shown works in the same way as... Figure 6 The operation of the pixel circuit 100 shown is the same, and will not be described again here.

[0064] This application embodiment also provides a driving method for driving the pixel circuit 100 and the selection circuit 200 in the above embodiments, the method including: In the first stage t1, the driver chip IC outputs a first reset voltage Vini to the selection circuit 200. The selection circuit 200 outputs the first reset voltage Vini to the signal transmission line 300, and transmits the first reset voltage Vini to the first terminal of the voltage writing module 102 through the signal transmission line 300. It should be noted that in this embodiment, the conduction start time and conduction end time of the voltage writing modules 102 of all pixel circuits 100 are the same in this stage. That is, the voltage writing modules 102 in all pixel circuits 100 are simultaneously turned on in response to the first conduction level of the second gate signal S2, and the conduction duration is the same. That is, the first conduction levels of the second gate signal S2 are overlapped. Within the same time, the voltage writing modules 102 in all pixel circuits 100 transmit the first reset voltage Vini to the first control terminal of the driver module 101 at the same time, realizing the full-screen initialization of the first control terminal of the driver module 101.

[0065] In the third stage t3, the driver chip IC outputs a data voltage Vdata to the selection circuit 200. The selection circuit 200 outputs the data voltage Vdata to the signal transmission line 300, which then transmits the data voltage Vdata to the first terminal of the voltage writing module 102. It should be noted that in this embodiment, the voltage writing modules 102 of all pixel circuits 100 are turned on row by row in this stage. That is, at any given time, only one row of pixel circuits 100 has its voltage writing module 102 turned on. The voltage writing modules 102 in multiple pixel circuits 100 in the same column are turned on sequentially in response to the second conduction level of the second gate signal S2. This means the second conduction level of the second gate signal S2 is shifted, and the data voltage Vdata is transmitted sequentially to the first control terminal of the driver module 101, thus realizing the row-by-row writing of the data voltage Vdata.

[0066] In this embodiment, the first stage t1 is located before the third stage t3. This embodiment uses a single voltage writing module 102 to transmit two voltage signals in a time-division multiplexing manner, which can save layout space and increase pixel density (PPI).

[0067] In one embodiment, the selection circuit 200 includes a selection module 201. The first terminal of the selection module 201 is connected to a first reset voltage Vini, the second terminal of the selection module 201 is connected to a data voltage Vdata, the third terminal of the selection module 201 is electrically connected to a signal transmission line 300, the first control terminal of the selection module 201 is connected to a first control signal SW1, and the second control terminal of the selection module 201 is connected to a second control signal SW2.

[0068] The method in this embodiment also includes: In the first stage t1 and the second stage t2, the selection module 201 responds to the first control signal SW1 and turns on, transmitting the first reset voltage Vini to the signal transmission line 300.

[0069] In the third stage t3, the selection module 201 responds to the second control signal SW2 and turns on, transmitting the data voltage Vdata to the signal transmission line 300.

[0070] The second stage t2 is located between the first stage t1 and the third stage t3. That is, the threshold voltage compensation process of the driving module 101 is performed before the data voltage Vdata writing process. The two are performed separately, so that the threshold voltage compensation time of the driving module 101 is not limited by the data voltage Vdata writing time. The threshold voltage compensation time is more sufficient, which is beneficial to improving the uniformity of high refresh rate display.

[0071] The specific working process of this embodiment can be found by referring to... Figure 6 and Figure 10 The working process of the circuit shown will not be described in detail here.

[0072] The display panel 400 of this application embodiment can be applied to mobile phones, or to any electronic product with display function, including but not limited to the following categories: televisions, laptops, desktop monitors, tablets, digital cameras, smart bracelets / watches, smart glasses, in-vehicle displays, medical devices, industrial control equipment, touch interactive terminals, etc. This application embodiment does not make any special limitations on this.

[0073] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0074] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel comprising a display area and a non-display area surrounding at least a portion of the display area, characterized in that, The display panel includes a pixel circuit and a selection circuit. The pixel circuit is located in the display area, and the selection circuit is located in the non-display area. One selection circuit is electrically connected to multiple pixel circuits through a signal transmission line. The pixel circuit includes a driving module and a voltage writing module. The first end of the voltage writing module is electrically connected to the signal transmission line, and the second end of the voltage writing module is electrically connected to the first control end of the driving module. The control end of the voltage writing module is connected to a second gate signal, which includes a first conduction level and a second conduction level. In the first stage, the selection circuit transmits the first reset voltage to the first terminal of the voltage writing module through the signal transmission line. The voltage writing modules in the multiple pixel circuits simultaneously turn on in response to the first conduction level, and simultaneously transmit the first reset voltage to the first control terminal of the driving module. In the third stage, the selection circuit transmits the data voltage to the first terminal of the voltage writing module through the signal transmission line. The voltage writing modules in the plurality of pixel circuits turn on in sequence in response to the second conduction level, and transmit the data voltage to the first control terminal of the driving module in sequence. The first stage precedes the third stage.

2. The display panel according to claim 1, characterized in that, The pixel circuit further includes a coupling module and a light-emitting device. The first end of the coupling module is electrically connected to the first control end of the driving module, the second end of the coupling module is electrically connected to the first end of the driving module, the second end of the driving module is electrically connected to the first power line, the first end of the light-emitting device is electrically connected to the first end of the driving module, and the second end of the light-emitting device is electrically connected to the second power line. In the first stage, the first power line transmits the second power voltage, and the second power line transmits the third power voltage. In the second stage, the first power line transmits a first power voltage, the voltage value of the first power voltage is greater than the voltage value of the second power voltage, and the first power voltage charges the first end of the drive module to perform threshold voltage compensation on the drive module. The second stage is located between the first stage and the third stage; Preferably, the coupling module includes a second capacitor, the first terminal of the second capacitor being electrically connected to the first control terminal of the drive module, and the second terminal of the second capacitor being electrically connected to the first terminal of the drive module.

3. The display panel according to claim 2, characterized in that, The first conduction level covers the second power supply voltage, and the start time of the first conduction level is the same as the start time of the second power supply voltage. Preferably, the pulse width of the first conduction level is greater than the pulse width of the second conduction level, and the first conduction level is located before the second conduction level; Preferably, the first conduction levels of the second gate signals connected to the plurality of pixel circuits are set to overlap; Preferably, along the extension direction of the signal transmission line, the second conduction level of the second gate signal connected to the plurality of pixel circuits is shifted, wherein the plurality of pixel circuits are electrically connected to the same selection circuit.

4. The display panel according to claim 3, characterized in that, The pixel circuit further includes a reset module, the first terminal of which is connected to a second reset voltage, the second terminal of which is electrically connected to the first terminal of the driving module, and the control terminal of which is connected to a first gate signal. In the first stage, the reset module responds to the first gate signal and transmits the second reset voltage to the first terminal of the drive module; Preferably, multiple pixel circuits are connected to the same first gate signal; Preferably, the pulse width of the first gate signal's on-level is the same as the pulse width of the second power supply voltage; Preferably, the first on-level of the second gate signal covers the on-level of the first gate signal; Preferably, the reset module includes a third transistor, the first terminal of the third transistor is connected to a second reset voltage, the second terminal of the third transistor is electrically connected to the first terminal of the drive module, and the gate of the third transistor is connected to a first gate signal.

5. The display panel according to claim 4, characterized in that, The pixel circuit also includes a storage module, a first terminal of which is connected to a sustaining voltage, and a second terminal of which is electrically connected to the first terminal of the driving module. Preferably, the storage module includes a first capacitor, the first terminal of the first capacitor is connected to a sustaining voltage, and the second terminal of the first capacitor is electrically connected to the first terminal of the drive module. Preferably, in the fourth stage, the second power line transmits a fourth power voltage, the voltage value of the third power voltage is greater than the voltage value of the fourth power voltage, and the voltage value of the first power voltage is greater than the voltage value of the fourth power voltage. Preferably, the third power supply voltage covers the first stage, the second stage, and the third stage, and the fourth stage is located after the third stage.

6. The display panel according to any one of claims 1-5, characterized in that, The drive module includes a second control terminal, which is electrically connected to the first terminal of the drive module. Preferably, the driving module includes a first transistor, which includes a first gate and a second gate. The first gate of the first transistor serves as a first control terminal of the driving module, and the second gate of the first transistor serves as a second control terminal of the driving module. The first electrode of the first transistor serves as a first terminal of the driving module, and the second electrode of the first transistor serves as a second terminal of the driving module. One of the first gate and the second gate of the first transistor is a top gate, and the other is a bottom gate. The voltage writing module includes a second transistor, which includes a first electrode of the second transistor serving as a first terminal of the voltage writing module, and the second electrode of the second transistor serving as a second terminal of the voltage writing module. The gate of the second transistor serves as a control terminal of the voltage writing module. Preferably, the first transistor is an N-type transistor, and the semiconductor material of the first transistor includes metal oxide.

7. The display panel according to claim 1, characterized in that, The selection circuit includes a selection module. The first terminal of the selection module is connected to the first reset voltage, the second terminal of the selection module is connected to the data voltage, the third terminal of the selection module is electrically connected to the signal transmission line, the first control terminal of the selection module is connected to the first control signal, and the second control terminal of the selection module is connected to the second control signal. In the first and second stages, the selection module responds to the first control signal and turns on, transmitting the first reset voltage to the signal transmission line; In the third stage, the selection module responds to the second control signal and turns on to transmit the data voltage to the signal transmission line; Preferably, in a frame, the conduction level of the first control signal is before the conduction level of the second control signal, and the conduction level of the first control signal and the conduction level of the second control signal do not overlap; Preferably, the conduction level of the first control signal covers the first conduction level of the second gate signal, and the conduction level of the second control signal covers the second conduction level of the second gate signal.

8. The display panel according to claim 7, characterized in that, The selection module includes a fourth transistor and a fifth transistor. The first terminal of the fourth transistor serves as the first terminal of the selection module, the first terminal of the fifth transistor serves as the second terminal of the selection module, the gate of the fourth transistor serves as the first control terminal of the selection module, the gate of the fifth transistor serves as the second control terminal of the selection module, and the second terminals of the fourth transistor and the fifth transistor are electrically connected to form the third terminal of the selection module.

9. A driving method, characterized in that, The method for driving the pixel circuit and selection circuit in the display panel described in any one of 1-8, the method comprising: In the first stage, the selection circuit transmits the first reset voltage to the first terminal of the voltage writing module through the signal transmission line. The voltage writing modules in the plurality of pixel circuits simultaneously turn on in response to the first conduction level of the second gate signal, and simultaneously transmit the first reset voltage to the first control terminal of the driving module. In the third stage, the selection circuit transmits the data voltage to the first terminal of the voltage writing module through the signal transmission line. The voltage writing modules in the plurality of pixel circuits are turned on in sequence in response to the second conduction level of the second gate signal, and the data voltage is transmitted to the first control terminal of the driving module in sequence. The first stage precedes the third stage.

10. The driving method according to claim 9, characterized in that, The selection circuit includes a selection module. The first terminal of the selection module is connected to the first reset voltage, the second terminal of the selection module is connected to the data voltage, the third terminal of the selection module is electrically connected to the signal transmission line, the first control terminal of the selection module is connected to the first control signal, and the second control terminal of the selection module is connected to the second control signal. The method further includes: In the first and second stages, the selection module responds to the first control signal and turns on, transmitting the first reset voltage to the signal transmission line; In the third stage, the selection module responds to the second control signal and turns on to transmit the data voltage to the signal transmission line; The second stage is located between the first stage and the third stage.

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