Advanced 2.5d package-on-package structure and method of forming the same

Abstract

An advanced 2.5D panel-level packaging structure and a forming method thereof, the forming method comprising: forming a plurality of chip structures; forming a panel-level packaging body, the panel-level packaging body comprising a plurality of packaging units; bonding and connecting the plurality of chip structures and the plurality of packaging units correspondingly; and performing cutting processing on the panel-level packaging body to form a plurality of packaging units. By fully utilizing the advantage of the panel-level packaging body in size specification, the fixed limitation of wafer-level packaging in area utilization and cost control is broken. By performing cutting processing on the panel-level packaging body to form a plurality of packaging units, a plurality of packaging structures can be processed in parallel on the same panel, which significantly improves the production efficiency and reduces the unit manufacturing cost. In addition, the unified preparation of the panel-level packaging body provides a standardized platform for the subsequent integration of diversified chips, which is conducive to realizing the high-density heterogeneous integration of different functional chips and meeting the development needs of advanced packaging technology in system-level integration and multi-functional fusion.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to an advanced 2.5D board-level packaging structure and its formation method. Background Technology

[0002] With the rapid development of the semiconductor industry, chip manufacturing faces increasing challenges. At extremely small sizes, physical bottlenecks become more difficult to overcome, leading to rising R&D and production costs, declining product yields, and a gradual slowdown of Moore's Law, ushering in the post-Moore era for the semiconductor industry. Traditional packaging can no longer meet the new demands represented by artificial intelligence and high-performance computing. Leading companies in the semiconductor manufacturing field have begun to shift their focus from improving wafer manufacturing technology nodes to exploring innovations in system-in-package (SiP) technologies, giving rise to advanced packaging technologies.

[0003] Advanced packaging technologies have significantly improved chip performance by modifying packaging methods without shrinking process nodes. Emerging 2.5D and 3D packaging technologies further expand the application potential of flip-chip and wafer-level packaging processes by vertically stacking multiple chips, achieving more efficient input / output. Against the backdrop of the rapidly increasing computing power demands of artificial intelligence, these packaging technologies need to support higher frequencies and faster speeds of finer circuitry to shorten data transmission distances between chips, improve chip-to-die collaboration efficiency, thereby enhancing system performance and reducing overall power consumption.

[0004] However, there are still many problems in the formation process of the packaging structure in the existing technology. Summary of the Invention

[0005] The technical problem solved by this invention is to provide an advanced 2.5D board-level packaging structure and its formation method to achieve panel-level integrated manufacturing, improve efficiency and reduce costs.

[0006] To address the aforementioned problems, the present invention provides a method for forming an advanced 2.5D board-level package structure, comprising: forming a plurality of chip structures; forming a panel-level package, the panel-level package including a plurality of package units; bonding the plurality of chip structures to the plurality of package units accordingly; and after bonding, cutting the panel-level package to form a plurality of package units, the package unit including the package unit and a chip structure bonded to the package unit.

[0007] Optionally, the chip structure has several bonding bumps.

[0008] Optionally, the packaging unit includes an interposer layer, a first rewiring layer, a second rewiring layer, and a solder ball layer. The first rewiring layer and the second rewiring layer are located on opposite sides of the interposer layer and are electrically connected to the interposer layer. The wiring width and spacing in the second rewiring layer are both greater than the wiring width and spacing in the first rewiring layer. The solder ball layer is electrically connected to the second rewiring layer.

[0009] Optionally, the chip structure and the packaging unit are bonded together by bonding the bonding bumps to the first redistribution layer.

[0010] Optionally, the method for forming the plurality of chip structures includes: providing a chip wafer; forming a plurality of bonding bumps on the surface of the chip wafer; providing a wafer polishing film; attaching the chip wafer to the wafer polishing film, with the bonding bumps facing the wafer polishing film; performing a polishing and thinning process on the side of the chip wafer away from the wafer polishing film; after the polishing and thinning process, removing the wafer polishing film and providing a wafer carrier; supporting the chip wafer on the wafer carrier, with the thinned side of the chip wafer facing the wafer carrier; and dicing the chip wafer to form the plurality of chip structures.

[0011] Optionally, the method for forming a plurality of bonding bumps on the surface of the chip wafer includes: forming a dielectric layer on the surface of the chip wafer, the dielectric layer having a plurality of first conductive vias, the first conductive vias exposing the surface of the chip wafer; forming a first conductive seed layer in the first conductive vias and on the dielectric layer; forming a photoresist layer on the first conductive seed layer, the photoresist layer having a plurality of second conductive vias, the plurality of second conductive vias being respectively opposite to the plurality of first conductive vias; forming a conductive structure in the second conductive vias; after forming the conductive structure, removing the photoresist layer, and etching the first conductive seed layer based on the conductive structure until the surface of the chip wafer is exposed, thereby forming a plurality of bonding bumps.

[0012] Optionally, the method for forming the panel-level package includes: providing a first carrier board; forming a second conductive seed layer on the first carrier board; forming a plurality of conductive plugs on the second conductive seed layer; forming a first molding compound on the second conductive seed layer, the first molding compound exposing one end surface of the conductive plugs; forming a second redistribution layer on the first molding compound, the second redistribution layer being electrically connected to the conductive plugs; providing a second carrier board; bonding the second redistribution layer to the second carrier board and debonding the first carrier board; etching away the second conductive seed layer. A seed layer is formed, and the first molding compound is ground to expose the other end surface of the conductive plug. A first redistribution layer is formed on the first molding compound and electrically connected to the conductive plug. A third carrier is provided. The first redistribution layer is bonded to the third carrier and the second carrier is debonded. A solder ball layer is formed on the second redistribution layer and electrically connected to the second redistribution layer. A fourth carrier is provided. The solder ball layer is bonded to the fourth carrier and the third carrier is debonded.

[0013] Optionally, the method for forming the panel-level package includes: providing a first carrier board; forming a second conductive seed layer on the first carrier board; forming a plurality of conductive plugs on the second conductive seed layer; forming a first molding compound on the second conductive seed layer, the first molding compound exposing one end surface of the conductive plugs; forming a second redistribution layer on the first molding compound, the second redistribution layer being electrically connected to the conductive plugs; forming a solder ball layer on the second redistribution layer, the solder ball layer being electrically connected to the second redistribution layer; providing a second carrier board; bonding the solder ball layer to the second carrier board and debonding the first carrier board; etching away the second conductive seed layer and grinding the first molding compound to expose the other end surface of the conductive plugs; forming the first redistribution layer on the first molding compound, the first redistribution layer being electrically connected to the conductive plugs.

[0014] Optionally, after forming the conductive plug, the method further includes: providing a plurality of embedded elements; bonding the embedded elements to the second conductive seed layer; and exposing the electrical pins of the embedded elements in the first molding compound after the first molding compound is polished.

[0015] Optionally, the plurality of embedded elements include one or more of the following: bridging chips, passive devices, and heat dissipation devices.

[0016] Optionally, when the embedded element is the bridge chip or the passive device, the first molding layer covers the embedded element and exposes the electrical pins of the embedded element, and the first redistribution layer is electrically connected to the exposed electrical pins of the embedded element; when the embedded element is a heat dissipation device, the first molding layer covers the heat dissipation device.

[0017] Optionally, after bonding the chip structure and before dicing, the method further includes: filling the gap between the chip structure and the package unit after bonding; forming a second molding compound layer, the second molding compound layer covering the chip structure.

[0018] Optionally, the method for forming the second molding compound includes: forming a molding compound layer on the panel-level package, the molding compound layer covering the plurality of package units and the plurality of chip structures; and grinding the molding compound layer until the surface of the chip structure is exposed to form the second molding compound layer.

[0019] Optionally, after forming the package unit, the method further includes: providing an IC carrier board; and bonding the package unit to the IC carrier board.

[0020] Optionally, the thermal expansion coefficient of the packaging unit is greater than that of the chip structure, and the thermal expansion coefficient of the packaging unit is less than that of the external PCB board of the packaging structure.

[0021] Optionally, the thermal expansion coefficient of the packaging unit is in the range of 5ppm / ℃ to 10ppm / ℃.

[0022] Optionally, before bonding the chip structure to the packaging unit, the method further includes: providing a plurality of virtual chips; bonding the plurality of virtual chips to the packaging unit; providing a plurality of high-bandwidth memories; and bonding the plurality of high-bandwidth memories to the packaging unit.

[0023] Accordingly, the present invention also provides an advanced 2.5D board-level packaging structure, which is formed by the forming method described in any of the above technical solutions.

[0024] Compared with the prior art, the technical solution of the present invention has the following advantages: The advanced 2.5D board-level packaging structure formation method of this invention achieves a leapfrog transformation from traditional single-unit manufacturing to large-scale integrated manufacturing by employing panel-level fabrication processes. This process bonds several chip structures to several packaging units within the panel-level package, fully utilizing the size advantages of the panel-level package and overcoming the inherent limitations of wafer-level packaging in terms of area utilization and cost control. After bonding, the panel-level package is diced to form several packaging units, enabling multiple packaging structures to be processed in parallel on the same panel, significantly improving production efficiency and reducing unit manufacturing costs. Furthermore, the standardized fabrication of the panel-level package provides a standardized platform for the subsequent integration of diverse chips, facilitating high-density heterogeneous integration of chips with different functions and meeting the development needs of advanced packaging technology in system-level integration and multi-functional fusion.

[0025] Furthermore, the packaging unit includes an interposer layer, a first rewiring layer, a second rewiring layer, and a solder ball layer. The first and second rewiring layers are located on opposite sides of the interposer layer and are electrically connected to it. The wiring width and spacing in the second rewiring layer are greater than those in the first rewiring layer. The solder ball layer is electrically connected to the second rewiring layer. This double-sided rewiring layer design, with the wiring width and spacing in the second rewiring layer being greater than those in the first rewiring layer, enables the chip structure to achieve high-density I / O fan-out, meeting the fine interconnection requirements of advanced process chips. Meanwhile, the PCB board, with its ample line width and spacing, ensures reliable connection to external circuit boards, forming a smooth interconnection transition from chip to system level.

[0026] Furthermore, after forming the conductive plug, the method further includes: providing a plurality of embedded elements; bonding the embedded elements to the second conductive seed layer; and exposing the electrical pins of the embedded elements after grinding the first molding layer. By embedding the plurality of embedded elements, deep integration of the packaging architecture is achieved. Functional components that would otherwise require independent placement are embedded within the interposer layer, fully utilizing the three-dimensional space of the interposer layer itself, significantly reducing the surface mount area occupied, and leaving more space for subsequent wiring.

[0027] Furthermore, the embedded components include one or more of the following: bridging chips, passive devices, and heat dissipation devices. The bridging chips enable high-speed interconnection between chips, shortening signal transmission paths; the embedded passive devices optimize power distribution networks and reduce noise coupling; and the integrated heat dissipation devices construct efficient three-dimensional thermal management channels, allowing heat to be directly conducted from the heat source.

[0028] Furthermore, when the embedded element is the bridging chip or the passive device, the first molding compound covers the embedded element and exposes its electrical pins. The first redistribution layer is electrically connected to the exposed electrical pins of the embedded element. When the embedded element is a heat dissipation device, the first molding compound covers the heat dissipation device. By specifically designing for the functional differences of the embedded elements, a precise match between process and function is achieved. When the embedded element is the bridging chip or the passive device, it is essentially an electrical function carrier and must form a reliable interconnection with the subsequently formed first redistribution layer through its electrical pins to achieve complete signal transmission and circuit function. The first molding compound simultaneously covers these devices and exposes their pins, protecting the device body and providing a directly accessible electrical interface for subsequent electrical connections to the first redistribution layer, ensuring unobstructed electrical paths. When the embedded element is only a heat dissipation device, its core function is heat conduction rather than signal processing, requiring no electrical connection; therefore, the first molding compound completely covers it. The fully encapsulated structure allows for more thorough contact between the heat dissipation device and the first molding layer, enabling heat to be transferred evenly over a larger area. Furthermore, the complete encapsulation enhances the mechanical stability of the heat dissipation device, preventing displacement or damage during subsequent lamination or grinding processes. It also avoids the risk of short circuits that may be caused by accidental exposure of the metal heat sink, thereby improving overall reliability.

[0029] Furthermore, after bonding the chip structure and before dicing, the method further includes: filling the gap between the chip structure and the package unit after bonding with an underfill layer; forming a second molding compound layer, the second molding compound layer covering the chip structure. The underfill layer effectively reduces thermomechanical stress caused by differences in thermal expansion coefficients, enhances the mechanical strength and fatigue resistance of the bonding interface, prevents solder joints from cracking and failing under temperature changes, significantly improves the reliability of the package structure, and ensures the stable operation of the chip structure in complex environments.

[0030] Furthermore, the thermal expansion coefficient of the packaging unit is greater than that of the chip structure, and the thermal expansion coefficient of the packaging unit is less than that of the external PCB board of the packaging structure; the thermal expansion coefficient of the packaging unit ranges from 5ppm / ℃ to 10ppm / ℃. This range of 5ppm / ℃ to 10ppm / ℃ creates an ideal gradient transition from the chip structure (approximately 2.8ppm / ℃) to the PCB board (approximately 16ppm / ℃), effectively balancing the thermal stress distribution between different material layers, preventing interface failure due to stress concentration, significantly improving the reliability of the package during temperature cycling and long-term use, and extending the product lifecycle. Attached Figure Description

[0031] Figures 1 to 18This is a schematic diagram of the steps in the method for forming an advanced 2.5D board-level packaging structure in an embodiment of the present invention; Figures 19 to 26 This is a schematic diagram of the steps in the formation process of the panel-level package in another embodiment of the method for forming an advanced 2.5D board-level package structure. Detailed Implementation

[0032] As described in the background section, the formation process of the packaging structure in the prior art still has many problems. These will be explained in detail below.

[0033] Current packaging structure manufacturing primarily employs a single-unit fabrication model, which involves processing individual chips or packaging units sequentially. This manufacturing method has significant limitations in its process flow, making it impossible to achieve large-scale production at the panel level. While traditional wafer-level packaging can improve integration to some extent, its processing size is still limited by wafer specifications, making it difficult to overcome area bottlenecks to meet the needs of larger-scale packaging.

[0034] Building upon this foundation, the present invention provides an advanced 2.5D board-level packaging structure and its formation method. By employing panel-level fabrication processes, it achieves a leapfrog transformation of packaging structures from traditional single-unit fabrication to large-scale integrated manufacturing. This process bonds several chip structures to several packaging units within the panel-level package, fully leveraging the size advantages of the panel-level package and overcoming the inherent limitations of wafer-level packaging in terms of area utilization and cost control. After bonding, the panel-level package is diced to form several packaging units, enabling multiple packaging structures to be processed in parallel on the same panel, significantly improving production efficiency and reducing unit manufacturing costs. Furthermore, the standardized fabrication of the panel-level package provides a standardized platform for the subsequent integration of diverse chips, facilitating high-density heterogeneous integration of chips with different functions and meeting the development needs of advanced packaging technologies in system-level integration and multi-functional fusion.

[0035] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0036] Figures 1 to 18 This is a schematic diagram of the steps in the method for forming an advanced 2.5D board-level packaging structure in an embodiment of the present invention.

[0037] Several chip structures are formed, each chip structure having several bonding bumps. Please refer to [reference needed] for the specific formation process. Figures 1 to 6 .

[0038] Please refer to Figure 1 , providing 100 chip wafers.

[0039] In this embodiment, the chip wafer 100 is a complete wafer substrate formed through front-end processes in semiconductor manufacturing, with active devices and interconnect structures already formed on its surface. The chip wafer 100 will serve as the starting point for subsequent packaging processes. External electrical connections are achieved by forming bonding bumps on its surface, and the overall thickness is reduced through grinding and thinning to meet the size requirements of advanced packaging. Finally, it is diced to form independent chip structures, providing standardized chip units for panel-level packaging.

[0040] In this embodiment, after the chip wafer 100 is provided, the surface of the chip wafer 100 is cleaned using a plasma cleaning process.

[0041] After providing the chip wafer 100, a plurality of bonding bumps are formed on the surface of the chip wafer 100. For details of the formation process, please refer to [reference needed]. Figures 2 to 4 .

[0042] Please refer to Figure 2 A dielectric layer 101 is formed on the surface of the chip wafer 100, and the dielectric layer 101 has a plurality of first conductive vias 102.

[0043] In this embodiment, the method for forming the dielectric layer 101 includes: forming a photosensitive polyimide material (PSPI) on the surface of the chip wafer 100, and forming the desired patterned structure by exposing, developing, and curing the photosensitive polyimide material. Specifically, the exposure process uses ultraviolet light of a specific wavelength to selectively irradiate the thin film of the photosensitive polyimide material, causing a photochemical reaction in the exposed area and altering its solubility properties; the developing process uses an alkaline developer to remove unexposed or exposed areas (depending on the negative or positive type of the PSPI), forming a precise opening pattern; the curing process is carried out in a high-temperature nitrogen atmosphere, where the molecular chains of the photosensitive polyimide material are cross-linked and cured through a thermal polymerization reaction, ultimately forming a permanent dielectric layer structure with excellent thermal stability, mechanical strength, and insulating properties.

[0044] Please refer to Figure 3 A first conductive seed layer 103 is formed in the first conductive via 102 and on the dielectric layer 101; a photoresist layer 104 is formed on the first conductive seed layer 103, and the photoresist layer 104 has a plurality of second conductive vias 105, the plurality of second conductive vias 105 being respectively opposite to a plurality of first conductive vias 102.

[0045] In this embodiment, the first conductive seed layer 103 is typically formed into a titanium-copper composite structure using a sputtering process to enhance the adhesion between the subsequent electroplated metal and the dielectric layer 101 and to provide a conductive substrate. Subsequently, a photoresist material layer is coated on the surface of the first conductive seed layer 103. A photolithography process is then used to form a photoresist layer 104 containing the plurality of second conductive vias 105, with each second conductive via 105 precisely aligned with the underlying first conductive via 102 to form a continuous conductive channel. This double-layer via structure design ensures that the electroplated metal can fill from bottom to top and form bonding bumps with a predetermined morphology. Simultaneously, the photoresist layer 104 acts as an electroplating mold, defining the lateral dimensions of the bumps, laying the foundation for obtaining a highly consistent and precisely arranged array of bonding bumps.

[0046] Please refer to Figure 4 A conductive structure 106 is formed in the second conductive via 105. After the conductive structure 106 is formed, the photoresist layer 104 is removed, and the first conductive seed layer 103 is etched based on the conductive structure 106 until the surface of the chip wafer 100 is exposed, thereby forming a plurality of bonding bumps.

[0047] In this embodiment, copper metal is filled into the second conductive via 105 by electroplating to form the conductive structure 106. The conductive structure 106 is electrically connected to the first conductive seed layer 103 in the first conductive via 102, forming the main body of the bonding bump. After electroplating, the photoresist layer 104 is removed, exposing the unprotected area of ​​the first conductive seed layer 103. Subsequently, using the conductive structure 106 as a mask, the first conductive seed layer 103 is selectively etched to remove the portion of the first conductive seed layer 103 not covered by the conductive structure 106, thereby achieving electrical isolation between the bonding bumps.

[0048] Please refer to Figure 5 A wafer polishing film 107 is provided; the chip wafer 100 is attached to the wafer polishing film 107, with the bonding bumps facing the wafer polishing film 107; the side of the chip wafer 100 away from the wafer polishing film 107 is polished and thinned.

[0049] In this embodiment, the wafer polishing film 107, which has adhesive and buffering properties, is first provided. The chip wafer 100 is then adhered and fixed with the bonding bumps facing the wafer polishing film 107, allowing the bonding bumps to be embedded in the adhesive layer of the film for mechanical support and protection. Subsequently, the side of the chip wafer 100 facing away from the wafer polishing film 107 is polished and thinned. By mechanical polishing or chemical mechanical polishing, some of the silicon substrate material is removed, significantly reducing the overall thickness of the chip wafer 100.

[0050] Please refer to Figure 6 After the grinding and thinning process, the wafer grinding film 107 is removed and a wafer carrier (not shown) is provided; the chip wafer 100 is supported on the wafer carrier, with the thinned side of the chip wafer 100 facing the wafer carrier; the chip wafer 100 is cut to form the plurality of chip structures 108.

[0051] In this embodiment, after the grinding and thinning process is completed, the adhesion of the wafer grinding film 107 is released, the temporary protection of the bonding bumps is removed, and a wafer carrier with a flat supporting surface is provided. The chip wafer 100 is flipped over and supported on the wafer carrier, with the thinned back side facing the wafer carrier for stable support, while the front side with the bonding bumps is exposed upwards. This configuration facilitates the subsequent precise cutting of the chip wafer 100, which is divided into several independent chip structures 108 along a preset cutting path using blade cutting or laser cutting. The supporting function of the wafer carrier effectively prevents the thin wafer from warping or breaking during the cutting process, ensuring that each chip structure 108 maintains structural integrity and the positional accuracy of the bonding bumps during the individualization process.

[0052] At this point, the fabrication of the aforementioned chip structures 108 is complete.

[0053] After forming the plurality of chip structures 108, a panel-level package is formed, comprising a plurality of packaging units; wherein, each packaging unit includes an interposer layer, a first rewiring layer, a second rewiring layer, and a solder ball layer, the first rewiring layer and the second rewiring layer being located on opposite sides of the interposer layer and electrically connected to the interposer layer respectively, the wiring width and spacing in the second rewiring layer being greater than the wiring width and spacing in the first rewiring layer, and the solder ball layer being electrically connected to the second rewiring layer. For a detailed formation process, please refer to [reference needed]. Figures 7 to 15 .

[0054] Please refer to Figure 7 Provide the first carrier board 200.

[0055] In this embodiment, the first carrier board 200 serves as the basic support platform for subsequent panel-level packaging processes. Its surface flatness and thermal stability directly affect the forming accuracy of subsequent layer metal structures. The first carrier board 200 adopts a square panel, which can process dozens to hundreds of individual packaging structures in parallel in a single process cycle, significantly improving manufacturing efficiency and equipment capacity utilization.

[0056] In this embodiment, a release layer 201 is formed on the surface of the first carrier 200. The release layer 201 provides a controllable interface separation function during the bonding process. Under normal bonding conditions, the release layer 201 maintains structural stability, ensuring temporary fixation between the package and the first carrier 200. When debonding is required, its adhesion is weakened by laser irradiation or thermal action, achieving non-destructive separation of the package from the first carrier 200, thereby supporting the layer-by-layer construction of multi-layer structures and the cyclic use of the carrier.

[0057] In this embodiment, the first carrier plate 200 has a size of approximately 310 mm. 310mm.

[0058] Please refer to Figure 8 A second conductive seed layer 202 is formed on the first carrier plate 200.

[0059] In this embodiment, the second conductive seed layer 202 is specifically formed on the release layer 201, and the second conductive seed layer 202 is typically formed into a titanium-copper composite structure by sputtering process.

[0060] Please refer to Figure 9 A plurality of conductive plugs 203 are formed on the second conductive seed layer 202.

[0061] In this embodiment, the vertically interconnected conductive plugs 203 are formed on the second conductive seed layer 202 through electroplating or filling processes. The conductive plugs 203 penetrate the subsequently formed interposer layer, which will realize electrical conduction between the first redistribution layer and the second redistribution layer, forming the core vertical interconnect channel inside the packaging unit, and providing a high-density interlayer signal transmission path for the panel-level package.

[0062] Please continue to refer to this. Figure 9 After forming the conductive plug 203, a plurality of embedded elements 204 are provided; the embedded elements 204 are bonded to the second conductive seed layer 202.

[0063] By embedding the aforementioned embedded components 204, deep integration of the packaging architecture is achieved. Functional components that originally needed to be arranged independently are embedded inside the interposer layer, making full use of the three-dimensional space of the interposer layer itself, significantly reducing the occupation of the surface mount area, and leaving more room for subsequent wiring.

[0064] In this embodiment, the plurality of embedded elements 204 include one or more of the following: bridging chips, passive devices, and heat dissipation devices. The bridging chips can directly achieve high-speed interconnection between chips, shortening the signal transmission path; the embedding of the passive devices can optimize the power distribution network and reduce noise coupling; and the integration of the heat dissipation devices can construct an efficient three-dimensional thermal management channel, allowing heat to be directly conducted from the heat source.

[0065] Please refer to Figure 10 A first molding layer 205 is formed on the second conductive seed layer 202, and the first molding layer 205 exposes one end surface of the conductive plug 203.

[0066] In this embodiment, the first molding layer 205 covers the sidewalls and bottom area of ​​the conductive plug 203, while precisely controlling the molding thickness to expose one end surface of the conductive plug 203. This structural design allows the first molding layer 205 to provide mechanical support and insulation as the intermediary layer, while the exposed end face of the conductive plug 203 is used to achieve a reliable electrical connection with the subsequently formed redistribution layer, together forming the core interconnection foundation of the packaging unit.

[0067] In this embodiment, the first molding layer 205 is made of epoxy molding compound (EMC). Epoxy molding compound has excellent mechanical strength, thermal stability, and insulation properties.

[0068] Please refer to Figure 11 A second redistribution layer 206 is formed on the first molding layer 205, and the second redistribution layer 206 is electrically connected to the conductive plug 203.

[0069] In this embodiment, the second redistribution layer 206 is formed on the surface of the first molding layer 205 through thin film deposition, photolithography patterning, and electroplating processes. First, an adhesion layer and a seed layer are deposited on the first molding layer 205 and the exposed end face of the conductive plug 203. Then, photoresist is coated and exposed and developed to define the wiring pattern. After electroplating filler metal, the photoresist is removed and excess seed layer is etched, finally forming the second redistribution structure electrically connected to the conductive plug 203.

[0070] Please refer to Figure 12A second carrier 207 is provided; the second redistribution layer 206 is bonded to the second carrier 207 and the first carrier 200 is debonded; the second conductive seed layer 202 is etched away and the first molding layer 205 is polished so that the other end surface of the conductive plug 203 is exposed in the first molding layer 205.

[0071] In this embodiment, the process achieves flipping and double-sided processing of the packaging structure. First, a second carrier board 207 is provided, and the structure with the second redistribution layer 206 already formed is bonded to the second carrier board 207 using bonding adhesive to ensure stable support for the second redistribution layer 206. Then, the first carrier board 200 is debonded to release the temporary fixation to the second conductive seed layer 202, exposing the back side of the first molding layer 205 and the bottom area of ​​the conductive plug 203. Next, the second conductive seed layer 202 is etched away to eliminate the influence of residual metal layers on subsequent processes. Simultaneously, the first molding layer 205 is ground and thinned, with precise control over the amount of removal until the other end surface of the conductive plug 203 is exposed.

[0072] In this embodiment, after the first molding compound 205 is polished, the first molding compound 205 also exposes the electrical pins of the embedded element 204. Specifically, when the embedded element 204 is the bridge chip or the passive device, the first molding compound 205 covers the embedded element 204 and exposes its electrical pins, and the first redistribution layer is electrically connected to the exposed electrical pins of the embedded element 204; when the embedded element 204 is a heat dissipation device, the first molding compound 205 covers the heat dissipation device.

[0073] By specifically designing the embedded element 204 according to its functional attributes, a precise match between process and function is achieved. When the embedded element 204 is the bridge chip or the passive device, its essence is an electrical function carrier. It must form a reliable interconnection with the subsequently formed first wiring layer through electrical pins to achieve complete signal transmission and circuit function. The first molding compound 205 simultaneously covers these devices and exposes the pins, protecting the device body and providing a directly accessible electrical interface for subsequent electrical connections to the first wiring layer, ensuring a continuous and unobstructed electrical path. When the embedded element 204 is only the heat dissipation device, its core function is heat conduction rather than signal processing, requiring no electrical connection. Therefore, the first molding compound 205 completely covers it. The full-coverage structure allows for more sufficient contact between the heat dissipation device and the first molding compound 205, enabling heat to be transferred evenly over a larger area. Furthermore, the complete encapsulation enhances the mechanical stability of the heat dissipation device, preventing displacement or damage during subsequent lamination or grinding processes. It also avoids the risk of short circuits that may be caused by accidental exposure of the metal heat sink, improving overall reliability.

[0074] Please refer to Figure 13 A first redistribution layer 208 is formed on the first molding layer 205, and the first redistribution layer 208 is electrically connected to the conductive plug 203.

[0075] In this embodiment, the process employs thin-film deposition, photolithography patterning, and electroplating to form the first rewiring layer 208 on the exposed end face of the conductive plug 203 of the first molding layer 205. The first rewiring layer 208 has a fine wiring width and spacing, suitable for high-density signal interconnection, and achieves vertical electrical connection with the second rewiring layer 206 through the conductive plug 203.

[0076] In this embodiment, a double-sided redistribution layer design is adopted, and the wiring width and spacing in the second redistribution layer 206 are greater than those in the first redistribution layer 208. This enables the chip structure 108 to achieve high-density I / O fan-out, meeting the fine interconnection requirements of advanced process chips. Meanwhile, the PCB board ensures reliable connection with external circuit boards through its loose line width and spacing, forming a smooth interconnection transition from chip to system level.

[0077] Please refer to Figure 14 A third carrier board 209 is provided; the first redistribution layer 208 is bonded to the third carrier board 209 and the second carrier board 207 is debonded; the solder ball layer 210 is formed on the second redistribution layer 206 and the solder ball layer 210 is electrically connected to the second redistribution layer 206.

[0078] In this embodiment, the process involves flipping the package structure again and preparing solder balls. First, the third carrier board 209 is provided, and the structure with the first redistribution layer 208 already formed is bonded to the third carrier board 209 using bonding adhesive, providing stable support for the first redistribution layer 208. Then, the second carrier board 207 is debonded, exposing the surface of the second redistribution layer 206. Next, the solder ball layer 210 is formed on the second redistribution layer 206 using a ball-planting or electroplating process. The solder ball layer 210 is precisely aligned with the pad area of ​​the second redistribution layer 206 and electrically connected. The solder ball layer 210 serves as the terminal interface for external interconnection of the package unit, used for subsequent flip-chip bonding with the IC carrier board, completing the preparation of the bottom lead-out terminal of the panel-level package.

[0079] Please refer to Figure 15 A fourth carrier board 211 is provided; the solder ball layer 210 is bonded to the fourth carrier board 211, and the third carrier board 209 is debonded.

[0080] In this embodiment, this process completes the final carrier transfer of the panel-level package. The fourth carrier 211 is provided, and the structure with the solder ball layer 210 already formed is bonded to the fourth carrier 211 using bonding adhesive, providing stable support for the solder ball layer 210. Subsequently, the third carrier 209 is debonded, exposing the surface of the first redistribution layer 208. This flip configuration exposes the first redistribution layer 208 facing upwards, preparing it for subsequent bonding with the chip structure 108, while protecting the bottom solder ball layer 210 from damage, thus completing the manufacturable transfer of the panel-level package.

[0081] At this point, the fabrication of the panel-level package is complete.

[0082] Please refer to Figure 16 The plurality of chip structures 108 are correspondingly bonded and connected to the plurality of packaging units.

[0083] In this embodiment, this process achieves precise interconnection between the chip structure 108 and the packaging unit. The aforementioned prepared chip structures 108 are placed one by one on top of the corresponding packaging unit of the panel-level package, ensuring precise alignment between the bonding bumps on the surface of the chip structure 108 and the pad areas on the first redistribution layer 208 of the packaging unit. Through thermosetting bonding or reflow soldering processes, under the synergistic effect of process parameters such as temperature, pressure, and ultrasound, the bonding bumps and the first redistribution layer 208 form a metallurgical bond, achieving mechanical fixation and electrical conductivity between the chip structure 108 and the packaging unit.

[0084] In this embodiment, the chip structure 108 is bonded to the packaging unit based on the bonding bumps and the first redistribution layer 208.

[0085] In this embodiment, the coefficient of thermal expansion of the packaging unit is greater than that of the chip structure 108, and the coefficient of thermal expansion of the packaging unit is less than that of the external PCB board of the packaging structure; the coefficient of thermal expansion of the packaging unit ranges from 5ppm / ℃ to 10ppm / ℃. The range of the coefficient of thermal expansion of the packaging unit is limited to 5ppm / ℃ to 10ppm / ℃ to form an ideal gradient transition from the chip structure 108 (approximately 2.8ppm / ℃) to the PCB board (approximately 16ppm / ℃), effectively balancing the thermal stress distribution between the various material layers, preventing interface failure caused by stress concentration, significantly improving the reliability of the package during temperature cycling and long-term use, and extending the product lifecycle.

[0086] In this embodiment, the method further includes: providing a plurality of virtual chips (not shown); bonding the plurality of virtual chips to the packaging unit; providing a plurality of high-bandwidth memories 109; and bonding the plurality of high-bandwidth memories 109 to the packaging unit. First, the plurality of virtual chips are bonded to corresponding positions on the packaging unit. The virtual chips are used to balance the thermomechanical stress distribution of the packaging structure and provide structural support. Subsequently, the plurality of high-bandwidth memories 109 are bonded to the packaging unit to achieve the integration of storage function chips. This multi-chip configuration enables the packaging unit to simultaneously support logic chips, virtual chips, and storage chips, meeting the diverse functional requirements of advanced packaging in system-level integration and improving the integration and performance of the overall packaging structure.

[0087] Please continue to refer to this. Figure 16 An underfill layer 212 is filled into the gap between the chip structure 108 and the package unit after bonding; a second molding layer 213 is formed, which covers the chip structure 108.

[0088] In this embodiment, the method for forming the second molding compound 213 includes: forming a molding compound layer on the panel-level package, the molding compound layer covering the plurality of package units and the plurality of chip structures 108; and grinding the molding compound layer until the surface of the chip structure 108 is exposed to form the second molding compound 213. The underfill layer 212 effectively reduces thermomechanical stress caused by differences in thermal expansion coefficients, enhances the mechanical strength and fatigue resistance of the bonding interface, prevents solder joints from cracking and failing under temperature changes, significantly improves the reliability of the package structure, and ensures the stable operation of the chip structure 108106 in complex environments. The second molding compound 213 provides comprehensive mechanical protection and environmental isolation for the chip structure 108, effectively blocking moisture, dust, and chemical corrosion, while also providing electrical insulation and auxiliary heat dissipation functions, protecting the chip structure 108 from physical damage and environmental pollution, and ensuring its long-term stability and service life under various application conditions.

[0089] In this embodiment, the underfill layer 212 fills the micro-gap between the chip structure 108 and the first redistribution layer 208 after bonding. Its mechanism of action is to completely cover the micro-bump interconnect structure through capillary action or molding processes, forming a buffer protective layer. When the package undergoes temperature cycling, the underfill layer 212, with its moderate elastic modulus and coefficient of thermal expansion, effectively absorbs and disperses the shear stress caused by thermal mismatch, preventing stress concentration at brittle solder joints and significantly reducing the risk of solder joint fatigue cracking. Simultaneously, the underfill layer 212 enhances the mechanical strength of the bonding interface and improves resistance to moisture erosion and chemical corrosion, making it a key material for ensuring the long-term reliability of flip-chip packaging.

[0090] In this embodiment, the material of the second molding layer 213 is epoxy resin.

[0091] Please refer to Figure 17 After bonding, the panel-level package is cut to form several package units, each package unit including the package unit and a chip structure 108 bonded to the package unit.

[0092] By employing panel-level fabrication processes, a leapfrog transformation in packaging structure manufacturing is achieved, moving from traditional single-unit fabrication to large-scale integrated manufacturing. This process bonds the various chip structures 108 to the various packaging units within the panel-level package, fully leveraging the size advantages of the panel-level package and overcoming the inherent limitations of wafer-level packaging in terms of area utilization and cost control. After bonding, the panel-level package is diced to form the various packaging units, allowing multiple packaging structures to be processed in parallel on the same panel, significantly improving production efficiency and reducing unit manufacturing costs. Furthermore, the standardized fabrication of the panel-level package provides a standardized platform for the subsequent integration of diverse chips, facilitating high-density heterogeneous integration of chips with different functions and meeting the development needs of advanced packaging technologies in system-level integration and multi-functional fusion.

[0093] Please refer to Figure 18 After forming the packaged unit, an IC carrier board 300 is provided; the packaged unit is then bonded to the IC carrier board 300.

[0094] In this embodiment, this process completes the system-level integration of the packaged unit. After cutting to form the independent packaged unit, an IC carrier board 300 with multi-layer wiring is provided as a system-level interconnect substrate. The packaged unit is aligned with the corresponding pad area on the IC carrier board 300 through the bottom solder ball layer 210, and a reflow soldering process is used to achieve bonding, so that the packaged unit is fixed on the IC carrier board 300 and forms a reliable electrical path. This configuration integrates the packaged unit to a higher-level system platform, realizes extended interconnection of chip functions and external circuits, and meets the modular assembly requirements of complex electronic systems.

[0095] Figures 19 to 26 This is a schematic diagram of the steps in the formation process of the panel-level package in another embodiment of the method for forming an advanced 2.5D board-level package structure.

[0096] This embodiment further describes the formation method of the advanced 2.5D board-level packaging structure based on the above embodiments. The rest is the same as the above embodiments, except that the formation process of the panel-level package is different. For the specific formation process, please refer to [reference needed]. Figures 19 to 26 .

[0097] Please refer to Figure 19 Provide the first carrier board 400.

[0098] In this embodiment, the first carrier board 400 serves as the basic support platform for subsequent panel-level packaging processes. Its surface flatness and thermal stability directly affect the forming accuracy of subsequent layer metal structures. The first carrier board 400 adopts a square panel, which can process dozens to hundreds of individual packaging structures in parallel in a single process cycle, significantly improving manufacturing efficiency and equipment capacity utilization.

[0099] In this embodiment, a release layer 401 is formed on the surface of the first carrier 400. The release layer 401 provides a controllable interface separation function during the bonding process. Under normal bonding conditions, the release layer 401 maintains structural stability, ensuring temporary fixation between the package and the first carrier 400. When debonding is required, its adhesion is weakened by laser irradiation or thermal action, achieving non-destructive separation of the package from the first carrier 400, thereby supporting the layer-by-layer construction of multilayer structures and the cyclical use of the carrier.

[0100] In this embodiment, the first carrier plate 400 has a size of approximately 310 mm. 310mm.

[0101] Please refer to Figure 20 A second conductive seed layer 402 is formed on the first carrier plate 400.

[0102] In this embodiment, the second conductive seed layer 402 is specifically formed on the release layer 401, and the second conductive seed layer 402 is typically formed into a titanium-copper composite structure by sputtering process.

[0103] Please refer to Figure 21 A plurality of conductive plugs 403 are formed on the second conductive seed layer 402.

[0104] In this embodiment, the vertically interconnected conductive plugs 403 are formed on the second conductive seed layer 402 through electroplating or filling processes. The conductive plugs 403 penetrate the subsequently formed interposer layer, which will realize electrical conduction between the first rewiring layer and the second rewiring layer, forming the core vertical interconnect channel inside the packaging unit, and providing a high-density interlayer signal transmission path for the panel-level package.

[0105] Please continue to refer to this. Figure 21 After forming the conductive plug 403, a plurality of embedded elements 404 are provided; the embedded elements 404 are bonded to the second conductive seed layer 402.

[0106] By embedding the aforementioned embedded components 404, deep integration of the packaging architecture is achieved. Functional components that originally needed to be arranged independently are embedded inside the interposer layer, making full use of the three-dimensional space of the interposer layer itself, significantly reducing the occupation of the surface mount area, and leaving more leeway for subsequent wiring.

[0107] In this embodiment, the plurality of embedded elements 404 include one or more of the following: bridging chips, passive devices, and heat dissipation devices. The bridging chips can directly achieve high-speed interconnection between chips, shortening the signal transmission path; the embedding of the passive devices can optimize the power distribution network and reduce noise coupling; and the integration of the heat dissipation devices can construct an efficient three-dimensional thermal management channel, allowing heat to be directly conducted from the heat source.

[0108] Please refer to Figure 22 A first molding layer 405 is formed on the second conductive seed layer 402, and the first molding layer 405 exposes one end surface of the conductive plug 403.

[0109] In this embodiment, the first molding layer 405 covers the sidewalls and bottom area of ​​the conductive plug 403, while precisely controlling the molding thickness to expose one end surface of the conductive plug 403. This structural design allows the first molding layer 405 to provide mechanical support and insulation as the intermediary layer, while the exposed end face of the conductive plug 403 is used to achieve a reliable electrical connection with the subsequently formed redistribution layer, together forming the core interconnection foundation of the packaging unit.

[0110] In this embodiment, the first molding layer 405 is made of epoxy molding compound (EMC). Epoxy molding compound has excellent mechanical strength, thermal stability, and insulation properties.

[0111] Please refer to Figure 23 A second redistribution layer 406 is formed on the first molding layer 405, and the second redistribution layer 406 is electrically connected to the conductive plug 403.

[0112] In this embodiment, the second redistribution layer 406 is formed on the surface of the first molding layer 405 through thin film deposition, photolithography patterning, and electroplating processes. First, an adhesion layer and a seed layer are deposited on the first molding layer 405 and the exposed conductive plug 403 end face. Then, photoresist is coated and exposed and developed to define the wiring pattern. After electroplating filler metal, the photoresist is removed and excess seed layer is etched, finally forming the second redistribution structure electrically connected to the conductive plug 403.

[0113] Please refer to Figure 24 The solder ball layer 407 is formed on the second redistribution layer 406, and the solder ball layer 407 is electrically connected to the second redistribution layer 406.

[0114] In this embodiment, the solder ball layer 407 is formed on the second redistribution layer 406 through a ball-planting or electroplating process. The solder ball layer 407 is precisely aligned with the pad area of ​​the second redistribution layer 406 and electrically connected. The solder ball layer 407 serves as the terminal interface for external interconnection of the packaging unit and is used for subsequent flip-chip bonding with the IC carrier board 300 to complete the fabrication of the bottom lead-out terminal of the panel-level package.

[0115] Please refer to Figure 25 A second carrier plate 408 is provided; the solder ball layer 407 is bonded to the second carrier plate 408 and the first carrier plate 400 is debonded; the second conductive seed layer 402 is etched away and the first molding layer 405 is ground so that the other end surface of the conductive plug 403 is exposed in the first molding layer 405.

[0116] In this embodiment, the process achieves flipping and double-sided processing of the packaging structure. First, a second carrier board 408 is provided, and the structure with the solder ball layer 407 already formed is bonded to the second carrier board 408 using bonding adhesive to ensure stable support for the solder ball layer 407. Subsequently, the first carrier board 400 is debonded to release the temporary fixation to the second conductive seed layer 402, exposing the back side of the first molding layer 405 and the bottom area of ​​the conductive plug 403. Next, the second conductive seed layer 402 is etched away to eliminate the influence of the residual metal layer on subsequent processes. At the same time, the first molding layer 405 is ground and thinned, with precise control of the removal amount until the other end surface of the conductive plug 403 is exposed.

[0117] In this embodiment, after the first molding compound 405 is polished, the first molding compound 405 also exposes the electrical pins of the embedded element 404. Specifically, when the embedded element 404 is the bridge chip or the passive device, the first molding compound 405 covers the embedded element 404 and exposes its electrical pins, and the first redistribution layer 208 is electrically connected to the exposed electrical pins of the embedded element 404; when the embedded element 404 is a heat dissipation device, the first molding compound 405 covers the heat dissipation device.

[0118] By specifically designing the embedded element 404 according to its functional attributes, a precise match between process and function is achieved. When the embedded element 404 is the bridge chip or the passive device, its essence is an electrical function carrier. It must form a reliable interconnection with the subsequently formed first wiring layer 208 through electrical pins to achieve complete signal transmission and circuit function. The first molding layer 405 simultaneously covers these devices and exposes the pins, which not only protects the device body but also provides a directly accessible electrical interface for subsequent electrical connection to the first wiring layer 208, ensuring a continuous and unobstructed electrical path. When the embedded element 404 is only the heat dissipation device, its core function is heat conduction rather than signal processing, and no electrical connection is required. Therefore, the first molding layer 405 completely covers it. The fully encapsulated structure allows for more thorough contact between the heat dissipation device and the first molding layer 405, enabling heat to be transferred evenly over a larger area. Furthermore, the complete encapsulation enhances the mechanical stability of the heat dissipation device, preventing displacement or damage during subsequent lamination or grinding processes. It also avoids the risk of short circuits that may be caused by accidental exposure of the metal heat sink, thereby improving overall reliability.

[0119] Please refer to Figure 26 A first rewiring layer 409 is formed on the first molding layer 405, and the first rewiring layer 409 is electrically connected to the conductive plug 403.

[0120] In this embodiment, the process employs thin-film deposition, photolithography patterning, and electroplating to form the first rewiring layer 409 on the exposed end face of the conductive plug 403 of the first molding layer 405. The first rewiring layer 409 has a fine wiring width and spacing, suitable for high-density signal interconnection, and achieves vertical electrical connection with the second rewiring layer 406 through the conductive plug 403.

[0121] In this embodiment, a double-sided redistribution layer design is adopted, and the wiring width and spacing in the second redistribution layer 406 are greater than those in the first redistribution layer 409. This enables the chip structure 108 to achieve high-density I / O fan-out, meeting the fine interconnection requirements of advanced process chips. Meanwhile, the PCB board ensures reliable connection with external circuit boards through its loose line width and spacing, forming a smooth interconnection transition from chip to system level.

[0122] At this point, the fabrication of the panel-level package is complete.

[0123] Accordingly, this embodiment of the invention also provides an advanced 2.5D board-level packaging structure, which is formed using the forming method of any of the above embodiments.

[0124] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method of forming an advanced 2.5D package-on-board structure, comprising: include: Several chip structures are formed; A panel-level package is formed, the panel-level package comprising a plurality of package units; The plurality of chip structures are correspondingly bonded and connected to the plurality of packaging units; After bonding, the panel-level package is cut to form several package units, each package unit including the package unit and a chip structure bonded to the package unit.

2. The method for forming an advanced 2.5D board-level packaging structure as described in claim 1, characterized in that, The chip structure has several bonding bumps.

3. The method for forming an advanced 2.5D board-level packaging structure as described in claim 2, characterized in that, The packaging unit includes an interposer layer, a first rewiring layer, a second rewiring layer, and a solder ball layer. The first rewiring layer and the second rewiring layer are located on opposite sides of the interposer layer and are electrically connected to the interposer layer. The wiring width and spacing in the second rewiring layer are greater than those in the first rewiring layer. The solder ball layer is electrically connected to the second rewiring layer.

4. The method for forming an advanced 2.5D board-level packaging structure as described in claim 3, characterized in that, The chip structure is bonded to the packaging unit by bonding the bonding bumps to the first redistribution layer.

5. The method for forming an advanced 2.5D board-level packaging structure as described in claim 2, characterized in that, The method for forming the plurality of chip structures includes: providing a chip wafer; forming a plurality of bonding bumps on the surface of the chip wafer; providing a wafer polishing film; attaching the chip wafer to the wafer polishing film, with the bonding bumps facing the wafer polishing film; performing a polishing and thinning process on the side of the chip wafer away from the wafer polishing film; after the polishing and thinning process, removing the wafer polishing film and providing a wafer carrier; supporting the chip wafer on the wafer carrier, with the thinned side of the chip wafer facing the wafer carrier; and dicing the chip wafer to form the plurality of chip structures.

6. The method for forming an advanced 2.5D board-level packaging structure as described in claim 5, characterized in that, A method for forming a plurality of bonding bumps on the surface of a chip wafer includes: forming a dielectric layer on the surface of the chip wafer, the dielectric layer having a plurality of first conductive vias, the first conductive vias exposing the surface of the chip wafer; forming a first conductive seed layer in the first conductive vias and on the dielectric layer; forming a photoresist layer on the first conductive seed layer, the photoresist layer having a plurality of second conductive vias, the plurality of second conductive vias being respectively opposite to the plurality of first conductive vias; forming a conductive structure in the second conductive vias; after forming the conductive structure, removing the photoresist layer, and etching the first conductive seed layer based on the conductive structure until the surface of the chip wafer is exposed, thereby forming a plurality of bonding bumps.

7. The method for forming an advanced 2.5D board-level packaging structure as described in claim 3, characterized in that, The method for forming the panel-level package includes: providing a first carrier board; forming a second conductive seed layer on the first carrier board; forming a plurality of conductive plugs on the second conductive seed layer; forming a first molding compound on the second conductive seed layer, the first molding compound exposing one end surface of the conductive plugs; forming a second redistribution layer on the first molding compound, the second redistribution layer being electrically connected to the conductive plugs; providing a second carrier board; bonding the second redistribution layer to the second carrier board and debonding the first carrier board; etching away the second conductive seed layer and polishing the first molding compound to expose the other end surface of the conductive plugs; forming the first redistribution layer on the first molding compound, the first redistribution layer being electrically connected to the conductive plugs; providing a third carrier board; bonding the first redistribution layer to the third carrier board and debonding the second carrier board; forming the solder ball layer on the second redistribution layer, the solder ball layer being electrically connected to the second redistribution layer; providing a fourth carrier board; bonding the solder ball layer to the fourth carrier board and debonding the third carrier board.

8. The method for forming an advanced 2.5D board-level packaging structure as described in claim 3, characterized in that, The method for forming the panel-level package includes: providing a first carrier board; forming a second conductive seed layer on the first carrier board; forming a plurality of conductive plugs on the second conductive seed layer; forming a first molding compound on the second conductive seed layer, the first molding compound exposing one end surface of the conductive plugs; forming a second redistribution layer on the first molding compound, the second redistribution layer being electrically connected to the conductive plugs; forming a solder ball layer on the second redistribution layer, the solder ball layer being electrically connected to the second redistribution layer; providing a second carrier board; bonding the solder ball layer to the second carrier board and debonding the first carrier board; etching away the second conductive seed layer and grinding the first molding compound to expose the other end surface of the conductive plugs; forming the first redistribution layer on the first molding compound, the first redistribution layer being electrically connected to the conductive plugs.

9. The method for forming an advanced 2.5D board-level packaging structure as described in claim 7 or 8, characterized in that, After forming the conductive plug, the method further includes: providing a plurality of embedded elements; bonding the embedded elements to the second conductive seed layer; and exposing the electrical pins of the embedded elements after the first molding layer is polished.

10. The method for forming an advanced 2.5D board-level packaging structure as described in claim 9, characterized in that, The embedded components include one or more of the following: bridging chips, passive devices, and heat dissipation devices.

11. The method for forming an advanced 2.5D board-level packaging structure as described in claim 10, characterized in that, When the embedded element is the bridge chip or the passive device, the first molding layer covers the embedded element and exposes the electrical pins of the embedded element, and the first redistribution layer is electrically connected to the exposed electrical pins of the embedded element; when the embedded element is a heat dissipation device, the first molding layer covers the heat dissipation device.

12. The method for forming an advanced 2.5D board-level packaging structure as described in claim 1, characterized in that, After the chip structure is bonded and before the dicing process, the method further includes: filling the gap between the chip structure and the package unit after bonding; forming a second molding compound layer, the second molding compound layer covering the chip structure.

13. The method for forming an advanced 2.5D board-level packaging structure as described in claim 12, characterized in that, The method for forming the second molding compound includes: forming a molding compound layer on the panel-level package, the molding compound layer covering the plurality of package units and the plurality of chip structures; and grinding the molding compound layer until the surface of the chip structure is exposed to form the second molding compound layer.

14. The method for forming an advanced 2.5D board-level packaging structure as described in claim 1, characterized in that, After forming the packaged unit, the method further includes: providing an IC carrier board; and bonding the packaged unit to the IC carrier board.

15. The method for forming an advanced 2.5D board-level packaging structure as described in claim 1, characterized in that, The thermal expansion coefficient of the packaging unit is greater than that of the chip structure, and the thermal expansion coefficient of the packaging unit is less than that of the external PCB board of the packaging structure.

16. The method for forming an advanced 2.5D board-level packaging structure as described in claim 15, characterized in that, The thermal expansion coefficient of the packaging unit ranges from 5ppm / ℃ to 10ppm / ℃.

17. The method for forming an advanced 2.5D board-level packaging structure as described in claim 1, characterized in that, Before bonding the chip structure to the packaging unit, the method further includes: providing a plurality of virtual chips; bonding the plurality of virtual chips to the packaging unit; providing a plurality of high-bandwidth memories; and bonding the plurality of high-bandwidth memories to the packaging unit.

18. An advanced 2.5D board-level packaging structure, characterized in that, Formed by any one of the forming methods of claims 1 to 17.

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