Load current detection circuit, chip and electronic device of boost converter

Abstract

The disclosure provides a load current detection circuit, a chip and an electronic device of a Boost converter, comprising a sampling circuit composed of a transistor and a voltage-current conversion circuit composed of an operational amplifier and a transistor. Through the sampling circuit, the current flowing through the high-side transistor and the load current can be sampled respectively when the high-side transistor is turned on, and the target sampling voltage is obtained based on the sampling result. When the high-side transistor is turned off, the load current is sampled to obtain the target sampling voltage. Through the voltage-current conversion circuit, the average value of the target sampling voltage within one switching period of the Boost converter can be adjusted to the output voltage of the Boost converter, and the differential voltage between the target sampling voltage and the output voltage is converted into the target sampling current, so as to realize the detection of the load current. The load current detection circuit can improve the efficiency of the Boost converter, improve the detection accuracy of the load current, and reduce the chip area and power consumption cost.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more particularly to a load current detection circuit, chip, and electronic device for a Boost converter. Background Technology

[0002] Boost converters are one of the basic topologies of direct current (DC) to DC converters. The load current sensing function of Boost converters is widely required in power system monitoring and management. In system monitoring, the main processor can read real-time load current values ​​to monitor system power consumption, perform thermal management, and assess remaining battery life. It can also perform fault diagnosis and prediction, and record historical current data, which helps in analyzing abnormal operating conditions or predicting potential faults.

[0003] In existing technologies, load current can be sampled and detected based on the sampling resistor or the average inductor current. However, the former generates additional conduction losses, resulting in lower efficiency of the Boost converter, while the latter is greatly affected by process precision, resulting in lower detection accuracy. Therefore, there is an urgent need for a technical solution that can balance efficiency and detection accuracy. Summary of the Invention

[0004] This disclosure provides a load current detection circuit, chip, and electronic device for a Boost converter, which can improve the efficiency of the Boost converter, improve the detection accuracy of the load current, and reduce chip area and power consumption costs.

[0005] In a first aspect, this disclosure provides a load current detection circuit for a Boost converter. The Boost converter includes an inductor connected between a voltage input terminal and a switching node, a low-side transistor connected between the switching node and ground, and a high-side transistor connected between the switching node and a voltage output terminal. The load current detection circuit includes a sampling circuit composed of transistors and a voltage-to-current conversion circuit composed of transistors and operational amplifiers. The input terminal of the sampling circuit is connected to the switching node, the output terminal of the sampling circuit is connected to the non-inverting input terminal of the voltage-to-current conversion circuit, the inverting input terminal of the voltage-to-current conversion circuit is connected to the voltage output terminal, and the output terminal of the voltage-to-current conversion circuit is connected to the output terminal of the load current detection circuit.

[0006] The sampling circuit is configured to sample the current flowing through the high-side transistor and the load current when the high-side transistor is turned on, and determine the target sampling voltage based on the sampled inductor sampling voltage and load sampling voltage; when the high-side transistor is turned off, sample the load current to obtain the target sampling voltage.

[0007] The voltage-to-current conversion circuit is configured to adjust the average value of the target sampled voltage over one switching cycle of the Boost converter to the output voltage of the Boost converter, and to convert the difference between the target sampled voltage and the output voltage into a target sampled current.

[0008] In some embodiments of this disclosure, the sampling circuit includes a first transistor, a second transistor, and a third transistor. A first terminal of the first transistor is connected to the switching node. A second terminal of the first transistor is connected to the first terminals of the second transistor and the third transistor. A control terminal of the first transistor is connected to the control terminal of the high-side transistor. A second terminal of the second transistor is connected to the voltage output terminal. A second terminal of the third transistor is connected to the non-inverting input terminal of the voltage-to-current conversion circuit. The control terminals of the second transistor and the third transistor are connected to a sampling control signal.

[0009] Specifically, when the high-side transistor is turned on, the first transistor is turned on; when the high-side transistor is turned off, the first transistor is turned off.

[0010] In some embodiments of this disclosure, the second transistor and the third transistor operate in the linear region, and the aspect ratio of the second transistor is at least an order of magnitude larger than that of the third transistor.

[0011] In some embodiments of this disclosure, the first transistor operates in the linear region when it is turned on, the aspect ratio of the first transistor is equal to the aspect ratio of the second transistor, and the aspect ratio of the first transistor is at least one order of magnitude smaller than the aspect ratio of the high-side transistor.

[0012] In some embodiments of this disclosure, the inductor sampling voltage is equal to Vout + Ron_HS IL / 2, where Vout is the output voltage of the Boost converter, IL is the inductor current, and Ron_HS is the on-resistance of the high-side transistor.

[0013] In some embodiments of this disclosure, the target sampling voltage when the high-side transistor is turned on is equal to Vout + Ron_HS. IL / 2-Isns Ron_M3, where Isns is the target sampling current and Ron_M3 is the on-resistance voltage of the third transistor.

[0014] In some embodiments of this disclosure, the target sampling voltage when the high-side transistor is turned off is equal to Vout - Isns. Ron_M3, where Isns is the target sampling current and Ron_M3 is the on-resistance voltage of the third transistor.

[0015] In some embodiments of this disclosure, the voltage-to-current conversion circuit includes the operational amplifier and a fourth transistor. The non-inverting input terminal of the operational amplifier and the first terminal of the fourth transistor are connected to the output terminal of the sampling circuit. The inverting input terminal of the operational amplifier is connected to the voltage output terminal. The output terminal of the operational amplifier is connected to the control terminal of the fourth transistor. The second terminal of the fourth transistor is grounded.

[0016] In some embodiments of this disclosure, the high-side transistor and the third transistor are transistors of the same type.

[0017] Secondly, this disclosure provides a power management chip, including any of the load current detection circuits provided in the first aspect.

[0018] Thirdly, this disclosure provides an electronic device including any of the power management chips provided in the second aspect.

[0019] In the technical solution of this disclosure embodiment, the load current detection circuit of the Boost converter includes a sampling circuit composed of transistors and a voltage-to-current conversion circuit composed of operational amplifiers and transistors. The sampling circuit can sample the current flowing through the high-side transistor and the load current when the high-side transistor is turned on, and obtain the target sampling voltage based on the sampling results. When the high-side transistor is turned off, the load current is sampled to obtain the target sampling voltage. The voltage-to-current conversion circuit can adjust the average value of the target sampling voltage in one switching cycle of the Boost converter to the output voltage of the Boost converter, and convert the difference voltage between the target sampling voltage and the output voltage into the target sampling current to realize the detection of the load current.

[0020] The load current detection circuit provided in this disclosure has the following beneficial effects: First, the load current detection circuit provided in this disclosure does not require a sampling resistor, which can avoid additional conduction losses caused by the sampling resistor, thereby improving the efficiency of the Boost converter.

[0021] Secondly, the load current detection circuit provided in this disclosure does not require the setting of resistors and capacitors, which can avoid the sampling accuracy deviation caused by relying on the absolute value of passive components such as resistors and capacitors with large manufacturing deviations, thereby improving the detection accuracy of load current.

[0022] Third, the load current detection circuit provided in this disclosure eliminates the need for high-precision current detection amplifiers, voltage-to-current converters, and current multipliers, which consume significant chip area and power, thus reducing chip area and power consumption costs. Furthermore, it avoids systematic errors caused by voltage-to-current converters and current multipliers, thereby further improving the detection accuracy of the load current ILoad.

[0023] The above description is merely an overview of the technical solutions of the embodiments of this application. In order to better understand the technical means of the embodiments of this application and to implement them in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the embodiments of this application more obvious and understandable, specific implementation methods of this application are described below. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein: Figure 1 A schematic diagram of a Boost converter and its load current detection circuit provided for the prior art.

[0025] Figure 2 A schematic diagram of another Boost converter and its load current detection circuit provided by the prior art.

[0026] Figure 3 This is a schematic diagram of the structure of a Boost converter provided in an embodiment of this disclosure.

[0027] Figure 4 This is a schematic diagram of a load current detection circuit provided in an embodiment of the present disclosure.

[0028] Figure 5 This is a circuit diagram of a load current detection circuit provided in an embodiment of the present disclosure. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0030] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the relevant art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement “connecting” two or more parts together shall mean that the parts are joined directly together or joined through one or more intermediate components.

[0031] In this disclosure, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of the phrase "embodiment" in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this disclosure can be combined with other embodiments.

[0032] Furthermore, the terms "first," "second," etc., in the specification, claims, or the accompanying drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.

[0033] In this disclosure, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three possibilities: A exists, A and B exist simultaneously, and B exists. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0034] In the description of this disclosure, unless otherwise stated, "multiple" and "at least two" mean two or more (including two), and similarly, "multiple groups" and "at least two groups" mean two or more (including two groups).

[0035] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0036] Figure 1 A schematic diagram of a Boost converter and its load current detection circuit provided for the prior art is shown below. Figure 1As shown, the Boost converter 10 includes a high-side transistor HS, a low-side transistor LS, an inductor L, an output capacitor Cout, a voltage input terminal, a voltage output terminal, and a load current detection circuit 100. The voltage input terminal receives the input voltage Vin, the voltage output terminal provides the output voltage Vout, and the switching node is the connection point of the high-side transistor HS, the low-side transistor LS, and the inductor L.

[0037] Inductor L is connected between the voltage input terminal and the switching node. The first end of the high-side transistor HS is connected to the switching node, and the second end of the high-side transistor HS is connected to the voltage output terminal through the load current detection circuit 100. The low-side transistor LS is connected between the switching node and ground. The output capacitor Cout and the load are connected in parallel between the voltage output terminal and ground. The voltage output terminal is also used to provide load current ILoad to the load.

[0038] For example, the relationship between the load current ILoad and the average inductor current IL_avg of the Boost converter 10 is related to the duty cycle D, i.e., ILoad = IL_avg (1-D), where D=1-Vin / Vout. Since the duty cycle D changes with the input voltage Vin and the output voltage Vout, it is impossible to detect the load current ILoad by directly sampling the current flowing through the inductor L, the high-side transistor HS, or the low-side transistor LS.

[0039] In the prior art, the load current detection circuit 100 may include a sampling resistor RSNS, a high-precision current detection amplifier 110, and a voltage-to-current converter 120, such as Figure 1 As shown. The sampling resistor RSNS is connected between the second terminal of the high-side transistor HS and the voltage output terminal. The two input terminals of the high-precision current sensing amplifier 110 are respectively connected to the two ends of the sampling resistor RSNS. The output terminal of the high-precision current sensing amplifier 110 is connected to the output terminal of the load current sensing circuit 100 through the voltage-to-current converter 120.

[0040] Voltage difference across the sampling resistor RSNS =ILoad Rs, where Rs is the resistance of the sampling resistor RSNS. The high-precision current sensing amplifier 110 can detect the voltage difference across the sampling resistor RSNS. The sampled voltage Vsns is amplified and obtained. The voltage-current converter 120 can convert the sampled voltage Vsns into a load sampled current ILoad_sns that is linearly positively correlated with the load current ILoad.

[0041] Since the sampling resistor RSNS is connected in the power path of the Boost converter 10, the sampling resistor RSNS will cause additional conduction loss Ploss, and Ploss = ILoad.2 Rs is obviously better the smaller it is. However, the bias and noise of the high-precision current sense amplifier 110 itself determine the minimum input voltage it can resolve. Moreover, high-frequency voltage ringing and current spikes from the switching node can easily couple to the sampling signal line through parasitic capacitance. Therefore, the accuracy of the high-precision current sense amplifier 110 itself limits Rs to a relatively small value, resulting in higher conduction loss Ploss, i.e., lower efficiency of the Boost converter 10. In addition, the high-precision current sense amplifier 110 has high circuit complexity, requiring a large chip area and power consumption. The voltage-to-current converter 120 also requires additional chip area and power consumption, resulting in higher power consumption and area costs for the chips.

[0042] To improve the efficiency of the Boost converter 10, existing technologies have proposed another load current detection circuit 200, such as... Figure 2 As shown, Figure 2 A schematic diagram of another Boost converter and its load current detection circuit provided in the prior art is shown. The Boost converter 20 includes a high-side transistor HS, a low-side transistor LS, an inductor L, an output capacitor Cout, a voltage input terminal, a voltage output terminal, and a load current detection circuit 200.

[0043] The connection point of the high-side transistor HS, the low-side transistor LS, and the inductor L forms the switching node. Inductor L is connected between the voltage input terminal and the switching node. High-side transistor HS is connected between the switching node and the voltage output terminal. Low-side transistor LS is connected between the switching node and ground. The output capacitor Cout and the load are connected in parallel between the voltage output terminal and ground. The voltage input terminal receives the input voltage Vin, and the voltage output terminal provides the output voltage Vout and the load current ILoad to the load.

[0044] The load current detection circuit 200 includes a sampling network 210, a voltage-to-current conversion circuit 220, and a current multiplier 230. The sampling network 210 includes a sampling resistor RSNS and a sampling capacitor CSNS connected in series between the voltage input terminal and the switching node. The sampling resistor RSNS and the sampling capacitor CSNS are connected in series and then in parallel with the inductor L.

[0045] The voltage-to-current conversion circuit 220 includes a first voltage-to-current converter, a second voltage-to-current converter, and a third voltage-to-current converter. The two input terminals of the first voltage-to-current converter are respectively connected to the two ends of the sampling capacitor CSNS. The output terminal of the first voltage-to-current converter is connected to the first input terminal of the current multiplier 230. The input terminal of the second voltage-to-current converter is connected to the voltage input terminal. The output terminal of the second voltage-to-current converter is connected to the second input terminal of the current multiplier 230. The input terminal of the third voltage-to-current converter is connected to the voltage output terminal. The output terminal of the third voltage-to-current converter is connected to the third input terminal of the current multiplier 230. The output terminal of the current multiplier 230 is connected to the output terminal of the load current detection circuit 200.

[0046] The voltage difference across the sampling capacitors CSNS is VS=RL IL_avg [1+s(L' / RL)] / (1+s Rs Cs), where RL is the equivalent series resistance DCR of inductor L, Rs is the resistance of sampling resistor RSNS, Cs is the capacitance of sampling capacitor CSNS, s is the complex frequency variable, L' is the inductance of inductor L, and IL_avg is the average inductor current. L', RL, Rs, and Cs can be set as L' / RL = Rs Cs, then VS=RL IL_avg, the first voltage-to-current converter can convert VS into an inductor sampling current IL_sns that is linearly positively correlated with the average inductor current IL_avg.

[0047] The second voltage-to-current converter receives the input voltage Vin and converts it into a first current Iin that is linearly positively correlated with the input voltage Vin. The third voltage-to-current converter receives the output voltage Vout and converts it into a second current Iout that is linearly positively correlated with the output voltage Vout. The current multiplier 230 performs a multiplication operation on the inductor sampling current IL_sns, the first current Iin, and the second current Iout to multiply the inductor sampling current IL_sns by (1... D), thus obtaining the load sampling current ILoad_sns that is truly linearly positively correlated with the load current ILoad.

[0048] The above proportionality coefficient [1+s(L' / RL)] / (1+s Rs The elimination of Cs is highly dependent on the absolute values ​​of Rs and Cs. However, the process accuracy of the sampling resistor RSNS and the sampling capacitor CSNS deviates significantly from their design values. The mismatch caused by this deviation directly affects the sampling accuracy of the current. The voltage-to-current conversion circuit 220 and the current operation of the current multiplier 230 both introduce systematic errors, further reducing the sampling accuracy and resulting in lower detection accuracy of the load current ILoad. In addition, the inclusion of the voltage-to-current conversion circuit 220 and the current multiplier 230 contributes to a relatively high chip area and power consumption cost.

[0049] To address the aforementioned technical problems, this disclosure provides a load current detection circuit, including a sampling circuit composed of transistors and a voltage-to-current conversion circuit composed of operational amplifiers and transistors. The sampling circuit samples the current flowing through the high-side transistor and the load current when the high-side transistor is on, and obtains a target sampling voltage based on the sampling results. When the high-side transistor is off, the load current is sampled to obtain the target sampling voltage. The voltage-to-current conversion circuit adjusts the average value of the target sampling voltage over one switching cycle of the Boost converter to the output voltage of the Boost converter, and converts the difference between the target sampling voltage and the output voltage into a target sampling current, thereby achieving load current detection. The load current detection circuit provided by this disclosure has the following beneficial effects: First, the load current detection circuit provided in this disclosure does not require a sampling resistor, which can avoid additional conduction losses caused by the sampling resistor, thereby improving the efficiency of the Boost converter.

[0050] Secondly, the load current detection circuit provided in this disclosure does not require the setting of resistors and capacitors, which can avoid the sampling accuracy deviation caused by relying on the absolute value of passive components such as resistors and capacitors with large manufacturing deviations, thereby improving the detection accuracy of load current.

[0051] Third, the load current detection circuit provided in this disclosure eliminates the need for high-precision current detection amplifiers, voltage-to-current converters, and current multipliers, which require significant chip area and power consumption, thus reducing chip area and power costs. Furthermore, it avoids systematic errors caused by voltage-to-current converters and current multipliers, thereby further improving the detection accuracy of the load current.

[0052] The technical solutions provided in this disclosure are described in detail below with reference to several specific embodiments.

[0053] Figure 3 This is a schematic diagram of the structure of a Boost converter provided in an embodiment of this disclosure, as shown below. Figure 3As shown, the Boost converter 30 includes a high-side transistor HS, a low-side transistor LS, an inductor L, a voltage input terminal, a voltage output terminal, an output capacitor Cout, and a load current detection circuit 300. The connection point of the high-side transistor HS, the low-side transistor LS, and the inductor L is the switching node SW. The voltage input terminal receives the input voltage Vin, and the voltage output terminal provides the output voltage Vout and the load current ILoad to the load.

[0054] Inductor L is connected between the voltage input terminal and the switching node SW. High-side transistor HS is connected between the switching node SW and the voltage output terminal. Low-side transistor LS is connected between the switching node SW and ground. Output capacitor Cout and the load are connected in parallel between the voltage output terminal and ground. The control terminal of high-side transistor HS is connected to the high-side control signal PGATE, and the control terminal of low-side transistor LS is connected to the low-side control signal NGATE.

[0055] The first input terminal of the load current detection circuit 300 is connected to the switching node SW, the second input terminal is connected to the voltage output terminal, the first control terminal is connected to the control terminal of the high-side transistor HS to receive the high-side control signal PGATE, and the second control terminal is connected to the sampling control signal SNS_ctrl. Specifically, when the sampling control signal SNS_ctrl is at the first level, the load current detection circuit 300 is in the working state; when the sampling control signal SNS_ctrl is at the second level, the load current detection circuit 300 is in the stopped state. For example, the first level is high and the second level is low, or the first level is low and the second level is high.

[0056] Figure 4 A schematic diagram of a load current detection circuit provided in an embodiment of this disclosure is shown below. Figure 4 As shown, the load current detection circuit 300 includes a sampling circuit 310 composed of transistors and a voltage-to-current conversion circuit 320 composed of operational amplifiers and transistors. The input terminal of the sampling circuit 310 is connected to the switching node SW, the output terminal of the sampling circuit 310 is connected to the non-inverting input terminal of the voltage-to-current conversion circuit 320, the inverting input terminal of the voltage-to-current conversion circuit 320 is connected to the voltage output terminal to receive the output voltage Vout, the output terminal of the voltage-to-current conversion circuit 320 is connected to the output terminal of the load current detection circuit 300, the first control terminal of the sampling circuit 310 is connected to the control terminal of the high-side transistor HS to receive the high-side control signal PGATE, and the second control terminal of the sampling circuit 310 is connected to the sampling control signal SNS_ctrl.

[0057] The sampling circuit 310 is configured to sample the current flowing through the high-side transistor HS and the load current ILoad when the high-side transistor HS is turned on, and determine the target sampling voltage Vsns based on the sampled inductor sampling voltage VCS_L and load sampling voltage VCS_LOAD; when the high-side transistor HS is turned off, the load current ILoad is sampled to obtain the target sampling voltage Vsns.

[0058] The voltage-to-current conversion circuit 320 is configured to adjust the average value of the target sampling voltage Vsns over one switching cycle of the Boost converter 30 to the output voltage Vout of the Boost converter 30, and to convert the differential voltage between the target sampling voltage and the output voltage Vout into the target sampling current Isns.

[0059] For example, Figure 5 A circuit diagram of a load current detection circuit provided in an embodiment of this disclosure is shown below. Figure 5 As shown, the sampling circuit 310 includes a first transistor M1, a second transistor M2, and a third transistor M3. The first terminal of the first transistor M1 is connected to the switching node SW. The second terminal of the first transistor M1 is connected to the first terminal of the second transistor M2 and the first terminal of the third transistor M3. The control terminal of the first transistor M1 is connected to the control terminal of the high-side transistor HS to receive the high-side control signal PGATE.

[0060] Specifically, when the high-side control signal PGATE is on, the high-side transistor HS and the first transistor M1 are turned on; when the high-side control signal PGATE is off, the high-side transistor HS and the first transistor M1 are turned off. For example, the first transistor M1 is a P-type metal-oxide-semiconductor field-effect transistor (PMOS). When the high-side control signal PGATE is low, the high-side transistor HS and the first transistor M1 are turned on and operate in the linear region; when the high-side control signal PGATE is high, the high-side transistor HS and the first transistor M1 are turned off.

[0061] The second terminal of the second transistor M2 is connected to the voltage output terminal to receive the output voltage Vout. The second terminal of the third transistor M3 is connected to the positive input terminal of the voltage-current conversion circuit 320. The control terminals of the second transistor M2 and the third transistor M3 are connected to the sampling control signal SNS_ctrl. For example, the second transistor M2 and the third transistor M3 are PMOS transistors. When the sampling control signal SNS_ctrl is at a low level, the sampling circuit 310 is in the working state, and the second transistor M2 and the third transistor M3 are turned on and operate in the linear region. When the sampling control signal SNS_ctrl is at a high level, the sampling circuit 310 stops working, and the second transistor M2 and the third transistor M3 are turned off.

[0062] Since the on-resistance Ron of the MOS in the linear region is 1 / [μ(V GS -V TH )C OX W / L], where μ is the electron mobility, C OX is the gate oxide capacitance per unit area, V GS is the gate-source voltage, V TH is the threshold voltage, W is the channel width, and L is the channel length. Then W / L is the aspect ratio. Therefore, when μ, C OX , V GS and V TH are all determined, the on-resistance Ron is inversely proportional to the aspect ratio W / L.

[0063] Exemplarily, the aspect ratio (W / L) M2 of the second transistor M2 is at least one order of magnitude larger than the aspect ratio (W / L) M3 [[ID= of the third transistor M3. The aspect ratio (W / L) M1 of the first transistor M1 is equal to the aspect ratio (W / L) M2 of the second transistor M2. The aspect ratio (W / L) M1 of the first transistor M1 is at least one order of magnitude smaller than the aspect ratio (W / L) HS of the high-side transistor HS, that is, (W / L) HS >>(W / L) M1 =(W / L) M2 >>(W / L) M3 . Therefore, Ron_HS << Ron_M1 = Ron_M2 << Ron_M3. Here, Ron_HS is the on-resistance of the high-side transistor HS, Ron_M1 is the on-resistance of the first transistor M1, Ron_M2 is the on-resistance of the second transistor M2, and Ron_M3 is the on-resistance of the third transistor M3.

[0064] When the high-side transistor HS is turned on, the low-side transistor LS is turned off, and the first transistor M1, the second transistor M2, and the third transistor M3 are turned on. Since Ron_M2 << Ron_M3, the current flowing through the third transistor M3, that is, the target sampling current Isns, is much smaller than the current flowing through the second transistor M2. The target sampling current Isns can be regarded as a small-signal current and can be ignored in the large-signal analysis.

[0065] At this time, a large-signal analysis is performed on the high-side transistor HS, the first transistor M1, and the second transistor M2. Since the first transistor M1 and the second transistor M2 are connected in series and then in parallel with the high-side transistor HS, the following relationship exists: (1) where, I M1 is the current flowing through the first transistor M1, and IL is the inductor current, that is, the current flowing through the high-side transistor HS at this time.

[0066] Perform a large-signal analysis on the voltage at the connection point A of the first transistor M1, the second transistor M2, and the third transistor M3, that is, the inductor sampling voltage VA: (2) where, I M2 is the current flowing through the second transistor M2. Substituting formula (1) into formula (2) can obtain: (3) At this time, the voltage difference between the connection point B and the connection point A of the sampling circuit 310 and the voltage-current conversion circuit 320, that is, the first load sampling voltage VCS1, can be expressed as: (4) where, Isns is the target sampling current, that is, the current flowing through the third transistor M3.

[0067] Denote the target sampling voltage Vsns when the high-side transistor HS is turned on as the first target sampling voltage Vsns1. Then the first target sampling voltage Vsns1 can be expressed as: (5) When the high-side transistor HS is turned off, the first transistor M1 is turned off, and the low-side transistor LS, the second transistor M2, and the third transistor M3 are turned on. Since Ron_M2 << Ron_M3, the voltage across the third transistor M3 is much greater than the voltage across the second transistor M2. At this time, the voltage difference between the connection point B and the connection point A, that is, the second load sampling voltage VCS2, can be expressed as: (6) Let the target sampling voltage Vsns when the high-side transistor HS is turned off be denoted as the second target sampling voltage Vsns2. Then, the second target sampling voltage Vsns2 can be expressed as: (7) Since the conduction time of the low-side transistor LS is D The conduction time of Tsw, the high-side tube HS is (1-D). Tsw, where D is the duty cycle of Boost converter 30 and Tsw is the switching period of Boost converter 30, therefore the average value Vsns_avg of the target sampling voltage Vsns within one switching period Tsw can be expressed as: (8) Where Vsns1_avg is the average value of the first target sampling voltage Vsns1, and Vsns1_avg = Vout + IL_avg Ron_HS / 2-Isns Ron_M3, Vsns2_avg is the average value of the second target sampling voltage Vsns2, and Vsns2_avg=Vout-Isns Ron_M3 can simplify formula (8) to: (9) Because ILoad=IL_avg (1-D), therefore formula (9) can be simplified to: (10) See also Figure 5 The voltage-to-current conversion circuit 320 includes an operational amplifier AMP and a fourth transistor M4. The non-inverting input terminal of the operational amplifier AMP and the first terminal of the fourth transistor M4 are connected to the output terminal of the sampling circuit 310 to receive the target sampling voltage Vsns. The inverting input terminal of the operational amplifier AMP is connected to the voltage output terminal to receive the output voltage Vout. The output terminal of the operational amplifier AMP is connected to the control terminal of the fourth transistor M4, and the second terminal of the fourth transistor M4 is grounded.

[0068] The operational amplifier AMP exhibits a steady-state characteristic with a periodic average differential voltage of zero at its input. This phenomenon is an inevitable result of the combined effects of the negative feedback mechanism, system stability, and the periodic averaging property of the signal. The reason is that the negative feedback mechanism compares the output voltage Vout with the target sampling voltage and uses the error to drive the system, forcing the target sampling voltage to track the output voltage Vout. When the system reaches a "steady state" in an engineering sense, the average value of the output voltage of the operational amplifier AMP must remain constant within a switching cycle Tsw or the signal dominance cycle. At this point, the system has entered dynamic equilibrium, and the net rate of change of its macroscopic observable quantities is zero.

[0069] The output voltage of the operational amplifier (AMP) is determined by the product of the differential input voltage (the differential voltage between the target sampling voltage and the output voltage Vout) and the open-loop gain. If, in steady state, the differential input voltage (the differential voltage between the target sampling voltage and the output voltage Vout) has a non-zero periodic average component within one switching cycle Tsw, i.e., a continuous DC error, this error will be amplified by the almost infinite DC gain of the AMP, producing a continuously changing output voltage drive component. This changing component will disrupt the periodic average constancy of the AMP's output voltage, causing the system's operating point to drift. This contradicts the system's "steady state." To eliminate this contradiction, the average value of the differential input voltage within one switching cycle Tsw needs to be zero to establish the logical equivalence between "steady state" and "periodic average zero differential input."

[0070] However, it should be noted that the above conclusions do not preclude the existence of instantaneous differential input voltage. In high-frequency switching systems or AC-coupled systems, instantaneous differential input voltage may contain significant ripple or AC components. These AC components are an inevitable product of the loop's dynamic adjustment process. The key difference is that the integral (i.e., average value) of these AC components over one switching cycle Tsw is zero. They constitute periodic fluctuations around zero average value, which are the adjustment signals performed by the system to maintain steady-state equilibrium, but due to their symmetry, they do not contribute net DC drive.

[0071] As analyzed above, the average value of the differential input voltage of the operational amplifier AMP (the differential voltage between the non-inverting and inverting input voltages of the operational amplifier AMP) is zero within one switching cycle Tsw. Specifically, when the high-side transistor HS is turned on, the non-inverting input voltage of the operational amplifier AMP is the first target sampling voltage Vsns, and the differential input voltage is Vsns1 - Vout. When the high-side transistor HS is turned off, the non-inverting input voltage of the operational amplifier AMP is the second target sampling voltage Vsns2, and the differential input voltage is Vsns2 - Vout.

[0072] Therefore, the average value of the differential input voltage of the operational amplifier AMP (the differential voltage between the non-inverting and inverting input voltages of the operational amplifier AMP) within one switching cycle Tsw is zero, which can be expressed as: Vsns_avg - Vout_avg = Vsns_avg - Vout = 0, that is, Vsns_avg = Vout. Combining with formula (10), we can know that ILoad Ron_HS / 2=Isns Ron_M3, then Isns=ILoad Ron_HS / (2 Ron_M3).

[0073] Thus, the target sampling current Isns is proportional to the load current ILoad, and the scaling factor between them is Ron_HS / Ron_M3=(W / L). M3 / (W / L) HS This can be achieved through design (W / L) M3 and (W / L) HS The sampling coefficients are designed accordingly. Since the accuracy of relative values ​​of devices in a chip is much higher than that of absolute values, the high-side transistor HS and the third transistor M3 can be set to be the same type of transistor to achieve good matching on the chip layout. This ensures that the trends of the high-side transistor HS and the third transistor M3 with temperature, voltage and process angle changes are consistent, which can minimize the impact of process and environment on sampling accuracy, thereby improving the detection accuracy of load current ILoad.

[0074] In summary, the load current detection circuit 300 provided in this disclosure, through a sampling circuit 310 composed of transistors, can sample the current flowing through the high-side transistor HS and the load current ILoad respectively when the high-side transistor HS is turned on to obtain the target sampling voltage Vsns. When the high-side transistor HS is turned off, the load current ILoad is sampled to obtain the target sampling voltage Vsns. Through a voltage-to-current conversion circuit 320 composed of operational amplifiers and transistors, the average value of the target sampling voltage Vsns within one switching cycle Tsw of the Boost converter 30 can be adjusted to the output voltage Vout of the Boost converter 30, and the difference between the target sampling voltage and the output voltage Vout is converted into the target sampling current Isns, thereby realizing the detection of the load current ILoad. The load current detection circuit 300 provided in this disclosure has the following beneficial effects: First, the load current detection circuit 300 provided in this disclosure does not require a sampling resistor, which can avoid additional conduction losses caused by the sampling resistor, thereby improving the efficiency of the Boost converter 30.

[0075] Secondly, the load current detection circuit 300 provided in this disclosure does not require the setting of resistors and capacitors, which can avoid the sampling accuracy deviation caused by relying on the absolute value of passive components such as resistors and capacitors with large manufacturing deviations, thereby improving the detection accuracy of load current ILoad.

[0076] Third, the load current detection circuit 300 provided in this disclosure eliminates the need for high-precision current detection amplifiers, voltage-to-current converters, and current multipliers, which require significant chip area and power consumption, thus reducing chip area and power costs. Furthermore, it avoids systematic errors caused by voltage-to-current converters and current multipliers, thereby further improving the detection accuracy of the load current ILoad.

[0077] This disclosure also provides a power management chip, including the load current detection circuit 300 provided in any of the above embodiments, which has the functional modules and beneficial effects of the load current detection circuit 300, and will not be described in detail here.

[0078] This disclosure also provides an electronic device including the power management chip described above, specifically including the load current detection circuit 300 provided in any of the above embodiments, which has the functional modules and beneficial effects of the load current detection circuit 300, and will not be repeated here.

[0079] Electronic devices include, but are not limited to, smartphones, tablets, smart home devices, vehicles, and wearable devices.

[0080] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” are to be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” should be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, the “example” is merely exemplary and illustrative, and should not be considered exclusive or extensive.

[0081] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0082] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A load current detection circuit for a Boost converter, characterized in that, The Boost converter includes an inductor connected between the voltage input terminal and the switching node, a low-side transistor connected between the switching node and ground, and a high-side transistor connected between the switching node and the voltage output terminal. The load current detection circuit includes a sampling circuit composed of transistors and a voltage-to-current conversion circuit composed of transistors and operational amplifiers. The input terminal of the sampling circuit is connected to the switching node, the output terminal of the sampling circuit is connected to the non-inverting input terminal of the voltage-current conversion circuit, the inverting input terminal of the voltage-current conversion circuit is connected to the voltage output terminal, and the output terminal of the voltage-current conversion circuit is connected to the output terminal of the load current detection circuit. The sampling circuit is configured to, when the high-side transistor is turned on, sample the current flowing through the high-side transistor and the load current respectively, and determine the target sampling voltage based on the sampled inductor sampling voltage and load sampling voltage; when the high-side transistor is turned off, sample the load current to obtain the target sampling voltage. The voltage-to-current conversion circuit is configured to adjust the average value of the target sampled voltage over one switching cycle of the Boost converter to the output voltage of the Boost converter, and to convert the difference between the target sampled voltage and the output voltage into a target sampled current.

2. The load current detection circuit according to claim 1, characterized in that, The sampling circuit includes a first transistor, a second transistor, and a third transistor; The first terminal of the first transistor is connected to the switching node, the second terminal of the first transistor is connected to the first terminal of the second transistor and the first terminal of the third transistor, the control terminal of the first transistor is connected to the control terminal of the high-side transistor, the second terminal of the second transistor is connected to the voltage output terminal, the second terminal of the third transistor is connected to the non-inverting input terminal of the voltage-current conversion circuit, and the control terminals of the second transistor and the third transistor are connected to the sampling control signal. Specifically, when the high-side transistor is turned on, the first transistor is turned on; when the high-side transistor is turned off, the first transistor is turned off.

3. The load current detection circuit according to claim 2, characterized in that, The second transistor and the third transistor operate in the linear region, and the aspect ratio of the second transistor is at least one order of magnitude larger than that of the third transistor.

4. The load current detection circuit according to claim 3, characterized in that, When the first transistor is turned on, it operates in the linear region. The width-to-length ratio of the first transistor is equal to that of the second transistor. The width-to-length ratio of the first transistor is at least one order of magnitude smaller than that of the high-side transistor.

5. The load current detection circuit according to claim 4, characterized in that, The inductor sampling voltage is equal to Vout + Ron_HS IL / 2, where Vout is the output voltage of the Boost converter, IL is the inductor current, and Ron_HS is the on-resistance of the high-side transistor.

6. The load current detection circuit according to claim 5, characterized in that, The target sampling voltage when the high-side transistor is turned on is equal to Vout + Ron_HS. IL / 2-Isns Ron_M3, where Isns is the target sampling current and Ron_M3 is the on-resistance voltage of the third transistor.

7. The load current detection circuit according to claim 3, characterized in that, The target sampling voltage when the high-side transistor is turned off is equal to Vout - Isns. Ron_M3, where Isns is the target sampling current and Ron_M3 is the on-resistance voltage of the third transistor.

8. The load current detection circuit according to claim 2, characterized in that, The voltage-to-current conversion circuit includes the operational amplifier and the fourth transistor; The non-inverting input terminal of the operational amplifier and the first terminal of the fourth transistor are connected to the output terminal of the sampling circuit, the inverting input terminal of the operational amplifier is connected to the voltage output terminal, the output terminal of the operational amplifier is connected to the control terminal of the fourth transistor, and the second terminal of the fourth transistor is grounded.

9. The load current detection circuit according to claim 3, characterized in that, The high-side transistor and the third transistor are the same type of transistor.

10. A power management chip, characterized in that, Includes the load current detection circuit according to any one of claims 1-9.

11. An electronic device, characterized in that, Includes the power management chip as described in claim 10.

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