Abnormality detection circuit and method for differential signal, electronic device

Abstract

The application discloses an abnormality detection circuit and method of a differential signal and electronic equipment, relates to the technical field of signal detection, and comprises the following steps: a first sampling circuit collects a first peak voltage of a first single-ended differential signal; a second sampling circuit collects a second peak voltage of a second single-ended differential signal; an input end of a first comparison circuit is electrically connected with an output end of the first sampling circuit, and the first comparison circuit obtains a first level signal according to the first peak voltage; an input end of a second comparison circuit is connected with an output end of the second sampling circuit, and the second comparison circuit obtains a second level signal according to the second peak voltage; and input ends of a detection circuit are connected with an output end of the first comparison circuit and an output end of the second comparison circuit respectively, and the detection circuit determines a single-ended differential signal in an abnormal state according to the first level signal and the second level signal. Therefore, the problem that existing abnormality detection of a differential signal cannot separately identify single differential signal line abnormalities is solved.

Description

Technical Field

[0001] This invention relates to the field of signal detection technology, and in particular to an anomaly detection circuit and method for differential signals, and an electronic device. Background Technology

[0002] The detection method for link breaks or signal malfunctions in high-speed differential signals is to monitor and judge the amplitude difference of the overall differential signal. It cannot identify amplitude abnormalities in a single signal line, which is not conducive to the rapid troubleshooting of maintenance personnel. Summary of the Invention

[0003] This invention provides a differential signal anomaly detection circuit and method, and electronic equipment, which at least solves the problem that existing detection methods for differential signal link open circuits or signal malfunctions cannot monitor and judge the differential signal as a whole, and cannot identify the amplitude anomaly of a single signal line.

[0004] This invention provides an anomaly detection circuit for differential signals, comprising: a first sampling circuit, a second sampling circuit, a first comparison circuit, a second comparison circuit, and a detection circuit. The input terminal of the first sampling circuit is electrically connected to the first output terminal of the differential signal output circuit, and the first sampling circuit is configured to acquire a first single-ended differential signal output from the first output terminal of the differential signal output circuit and a first peak voltage of the first single-ended differential signal. The input terminal of the second sampling circuit is electrically connected to the second output terminal of the differential signal output circuit, and the second sampling circuit is configured to acquire a second single-ended differential signal output from the second output terminal of the differential signal output circuit and a second peak voltage of the second single-ended differential signal. The input terminal of the first comparison circuit is electrically connected to the output terminal of the first sampling circuit, and the first comparison circuit is configured to obtain a first level signal based on the first peak voltage. The input terminal of the second comparison circuit is electrically connected to the output terminal of the second sampling circuit, and the second comparison circuit is configured to obtain a second level signal based on the second peak voltage. The input terminal of the detection circuit is electrically connected to the output terminals of the first and second comparison circuits, respectively, and the detection circuit is configured to determine a target single-ended differential signal in an abnormal state based on the first level signal and the second level signal.

[0005] The present invention also provides an anomaly detection method for differential signals, comprising the following steps: in response to a signal detection request, acquiring a first single-ended differential signal and a first peak voltage of the first single-ended differential signal output from a first output terminal of the differential signal output circuit through a first sampling circuit; acquiring a second single-ended differential signal and a second peak voltage of the second single-ended differential signal output from a second output terminal of the differential signal output circuit through a second sampling circuit; obtaining a first level signal based on the first peak voltage; and obtaining a second level signal based on the second peak voltage; and determining a target single-ended differential signal in an abnormal state based on the first level signal and the second level signal.

[0006] The present invention also provides an electronic device including the above-described differential signal anomaly detection circuit.

[0007] This invention involves a first sampling circuit acquiring the first peak voltage of a first single-ended differential signal, a second sampling circuit acquiring the second peak voltage of a second single-ended differential signal, a first comparison circuit obtaining a first level signal based on the first peak voltage, a second comparison circuit obtaining a second level signal based on the second peak voltage, and a detection circuit determining whether a single-ended differential signal is in an abnormal state based on the first and second level signals. This solves the problem of existing methods for detecting open circuits or poor signal quality in differential signal links, which monitor and judge the differential signal as a whole but cannot identify individual signal line amplitude abnormalities. It enables online detection of the peak voltage of single-ended signal lines, allowing for timely identification of single-ended signal line abnormalities in the system. Attached Figure Description

[0008] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a schematic diagram of an anomaly detection circuit for a differential signal according to an embodiment of the present invention; Figure 2 This is a schematic diagram of a differential signal receiving circuit according to an embodiment of the present invention; Figure 3 This is a schematic diagram of a first single-ended signal peak sampling circuit according to an embodiment of the present invention; Figure 4 This is a schematic diagram of a second single-ended signal peak sampling circuit according to an embodiment of the present invention; Figure 5 This is a schematic diagram of a first comparison circuit and a second comparison circuit according to an embodiment of the present invention; Figure 6 A schematic diagram of the normal operating voltage of a single-ended differential signal according to an embodiment of the present invention; Figure 7 This is a schematic diagram illustrating the change of a normal to an abnormal operating voltage for a single-ended differential signal according to an embodiment of the present invention. Figure 8 This is a flowchart illustrating an anomaly detection method for differential signals according to an embodiment of the present invention. Detailed Implementation

[0010] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0011] It should be noted that, in the description of this invention, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., used in this invention are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0012] Differential transmission transmits signals on two lines. These two signals have the same amplitude but opposite phase. The signals transmitted on these two lines are called differential signals. The signal receiver compares the voltage difference between the two differential signals on the two lines to determine the logic state transmitted by the transmitter.

[0013] Existing technologies include the following methods for detecting link breaks or signal malfunctions in high-speed differential signals: 1) Receiver swing detection: The receiver has a built-in high-speed sampling circuit that collects the peak voltages of the positive terminal (Vin_P) and negative terminal (Vin_N) of the differential signal in real time, calculates the difference between the two (i.e., differential swing Vdiff = Vin_P_peak – Vin_N_peak), and compares it with the preset standard swing range.

[0014] 2) Receiver-side digital eye diagram detection: The receiver superimposes the continuously received high-speed data streams into the same time domain window according to the bit period to form a "digital eye diagram", which is then compared with a standard template.

[0015] 3) The PCIe detect function is mainly used to detect the presence of PCIe devices at the other end of the link and to determine available link resources. This is achieved through a receiver detection circuit integrated into the transmitter. The transmitter outputs a common-mode pulse signal. When the receiver at the other end is not present, the amplitude of the pulse signal detected by the transmitter is almost attenuated; however, when the receiver at the other end is present, the pulse signal needs to charge the coupling capacitor of the link, and the amplitude will be significantly reduced. The receiver presence detection circuit at the transmitting end determines the magnitude of the charging time constant by the pulse amplitude, and thus concludes whether the receiver at the other end is present.

[0016] Of the three methods for detecting high-speed serial signals mentioned above, methods one and two detect the differential signal as a whole. When a single-ended signal in the differential signal is broken, the signal amplitude and timing are distorted, reducing the eye diagram opening and the amplitude detected by the swing. The bit error rate of the link may also increase. However, the detection results of methods one and two do not return to zero, making them indistinguishable from scenarios with poor link signal quality. Therefore, it is impossible to accurately determine whether a single-ended signal line has failed based on the eye diagram detection or swing detection at this time.

[0017] The PCIe detect function in Method 3 is specifically designed for single-ended signal open circuits. However, this design requires sending a specific waveform and is only executed at the beginning of the PCIe link. It cannot be executed during the normal operation of the PCIe link and therefore cannot detect single-ended signal open circuit faults that occur during the operation of the high-speed serial bus.

[0018] In summary, existing methods for detecting open circuits or poor signal quality in differential signal links monitor and judge the differential signal as a whole, but cannot identify abnormal amplitude of a single signal line.

[0019] To address the aforementioned problems, embodiments of the present invention provide an anomaly detection circuit for differential signals.

[0020] like Figure 1 As shown, the anomaly detection circuit 10 of the differential signal includes: a first sampling circuit 100, a second sampling circuit 200, a first comparison circuit 300, a second comparison circuit 400, and a detection circuit 500.

[0021] The first sampling circuit 100 is electrically connected to the first output of the differential signal output circuit 600. The first sampling circuit 100 is configured to acquire the first single-ended differential signal and the first peak voltage of the first single-ended differential signal output from the first output of the differential signal output circuit 600. The second sampling circuit 200 is electrically connected to the second output of the differential signal output circuit 600. The second sampling circuit 200 is configured to acquire the second single-ended differential signal and the second peak voltage of the second single-ended differential signal output from the second output of the differential signal output circuit 600. The first comparison circuit 300... The input terminal of the first sampling circuit 100 is electrically connected to the output terminal of the second sampling circuit 200. The first comparison circuit 300 is configured to obtain a first level signal based on a first peak voltage. The input terminal of the second comparison circuit 400 is electrically connected to the output terminal of the second sampling circuit 200. The second comparison circuit 400 is configured to obtain a second level signal based on a second peak voltage. The input terminal of the detection circuit 500 is electrically connected to the output terminals of the first comparison circuit 300 and the second comparison circuit 400, respectively. The detection circuit 500 is configured to determine the target single-ended differential signal in an abnormal state based on the first level signal and the second level signal.

[0022] In some embodiments, the differential signal output circuit 600 includes: a fifth capacitor C5 and a seventh resistor R7. One end of the fifth capacitor C5 is electrically connected to a first signal input terminal; one end of the seventh resistor R7 is electrically connected to a ninth connection node between the other end of the fifth capacitor C5 and the input terminal of the first sampling circuit 100; a sixth capacitor C6, one end of which is electrically connected to a second signal input terminal; and an eighth resistor R8, one end of which is electrically connected to a tenth connection node between the other end of the sixth capacitor C6 and the input terminal of the second sampling circuit 200.

[0023] like Figure 2 As shown, the ninth connection node is the connection node between the other end of the fifth capacitor C5 and the input terminal of the first sampling circuit 100, the tenth connection node is the connection node between the other end of the sixth capacitor C6 and the input terminal of the second sampling circuit 200, the first output terminal of the differential signal output circuit 600 is the other end of the fifth capacitor C5, and the second output terminal of the differential signal output circuit 600 is the other end of the sixth capacitor C6.

[0024] In this embodiment of the invention, the differential signal output circuit 600 is as follows: Figure 2As shown, the first signal input terminal of the differential signal output circuit 600 is Vin_P, and the second signal input terminal of the differential signal output circuit 600 is Vin_N. The fifth capacitor C5, as a DC blocking capacitor, is connected in series between the first signal input terminal Vin_P and the input terminal of the first sampling circuit 100. The sixth capacitor C6, as a DC blocking capacitor, is connected in series between the second signal input terminal Vin_N and the input terminal of the second sampling circuit 200. The fifth capacitor C5 and the sixth capacitor C6 play a DC blocking role, allowing only the AC differential signal to pass through and blocking the DC component.

[0025] After passing through the DC blocking capacitor, the first single-ended differential signal Vin_P_C and the second single-ended differential signal Vin_N_C are connected to the common-mode voltage VICM through the end matching resistors (i.e., the seventh resistor R7 and the eighth resistor R8, which are generally around 50 ohms). This ensures that the common-mode level is stabilized within a suitable range before the first single-ended differential signal Vin_P_C enters the first sampling circuit 100 and before the second single-ended differential signal Vin_N_C enters the second sampling circuit 200.

[0026] Through the above technical solution, the fifth capacitor C5 and the sixth capacitor C6, as DC blocking capacitors, can effectively block the DC components mixed in the input single-ended differential signal Vin_P and the single-ended differential signal Vin_N, allowing only the AC differential signal to pass through and be transmitted to the sampling circuit, thus avoiding the interference of DC offset on the sampling circuit. The end matching resistor, together with the common-mode voltage VICM, can stabilize the common-mode level of the DC-blocked single-ended differential signal within a set reasonable range.

[0027] In some embodiments, the first sampling circuit 100 includes: a first diode D1, the anode of the first diode D1 being electrically connected to a first output terminal of the differential signal output circuit 600, and the cathode of the first diode D1 being electrically connected to an input terminal of the first comparator circuit 300; a first resistor R1, one end of the first resistor R1 being connected to a first connection node between the first diode D1 and the first comparator circuit 300; a first capacitor C1, one end of the first capacitor C1 being electrically connected to the other end of the first resistor R1, and the other end of the first capacitor C1 being electrically connected to a ground node; and a second resistor R2, one end of the second resistor R2 being electrically connected to a second connection node between the first connection node and the first comparator circuit 300, and the other end of the second resistor R2 being electrically connected to a ground node.

[0028] The structural diagram of the first sampling circuit 100 is shown below. Figure 3 As shown in Figure (a), the first connection node is the connection node between the cathode of the first diode D1 and the first comparator circuit 300, one end of the first resistor R1 is connected to the first connection node, the second connection node is the connection node between the first connection node and the first comparator circuit 300, and one end of the second resistor R2 is connected to the second connection node.

[0029] The first diode D1 is a low voltage drop diode. As a detection element, the first diode D1 can use its unidirectional conductivity to convert the first single-ended differential signal Vin_P_C output from the first output terminal of the differential signal output circuit 600 into a unidirectional detection signal and extract the envelope features of the first single-ended differential signal Vin_P_C.

[0030] The first resistor R1 and the first capacitor C1 form a filter circuit to smooth the detected signal, filter out high-frequency noise, and obtain a more stable DC signal. It is recommended that the resistance value of the first resistor R1 be more than 50 times that of the end matching resistor R7, so as to reduce the impact on the end matching impedance. The RC time constant of the first resistor R1 × the first capacitor C1 needs to be designed according to the frequency range of the first single-ended differential signal Vin_P_C. The RC time should not be greater than the rise time of the differential signal, so as to select the capacitance value of the first capacitor C1.

[0031] The second resistor R2 is a capacitor discharge resistor, used to discharge the charge of the first capacitor C1 when the first single-ended differential signal Vin_P_C has no amplitude for a long time, until the first single-ended differential signal Vin_P_C has an actual voltage value. The RC time constant of the first resistor R1 × the first capacitor C1 is more than 50 times greater than the frequency range of the first single-ended differential signal Vin_P_C, which is used to select the resistance value of the second resistor R2. The first sampling circuit 100 samples the peak voltage of the first single-ended differential signal Vin_P_C and outputs the first peak voltage VP_det.

[0032] Through the above technical solution, the first diode D1 utilizes its unidirectional conductivity to achieve the detection function, converting the first single-ended differential signal Vin_P_C into a unidirectional detection signal, which can efficiently extract the envelope features of the signal. R1 and C1 form a filter circuit, which can smooth the unidirectional detection signal after detection, effectively filter out high-frequency noise in the signal, and output a stable signal. The RC time constant of R1×C1 is not greater than the rise time of the differential signal, ensuring that peak sampling lag is avoided due to RC delay. When the first single-ended differential signal Vin_P_C has no amplitude for a long time, R2 discharges the charge stored in the first capacitor C1, ensuring the accuracy of the sampling results when detecting the signal. By designing the RC time constant of R1×C1 to be more than 50 times the signal frequency range to select the resistance value of R2, the capacitor charge can be quickly discharged when the single-ended differential signal has no amplitude.

[0033] In some embodiments, the second sampling circuit 200 includes: a second diode D2, the anode of which is electrically connected to the second output terminal of the differential signal output circuit 600, and the cathode of which is electrically connected to the input terminal of the second comparator circuit 400; a third resistor R3, one end of which is connected to a third connection node between the second diode D2 and the second comparator circuit 400; a second capacitor C2, one end of which is electrically connected to the other end of the third resistor R3, and the other end of which is electrically connected to a ground node; and a fourth resistor R4, one end of which is electrically connected to a fourth connection node between the third connection node and the second comparator circuit 400, and the other end of which is electrically connected to a ground node.

[0034] The structure of the second sampling circuit 200 is as follows: Figure 3 As shown in Figure (b), the third connection node is the connection node between the second diode D2 and the second comparator circuit 400, one end of the third resistor R3 is connected to the third connection node, the fourth connection node is the connection node between the third connection node and the second comparator circuit 400, and one end of the fourth resistor R4 is connected to the fourth connection node.

[0035] The second diode D2 is a low-voltage-drop diode. As a detection element, the second diode D2 uses its unidirectional conductivity to convert the second single-ended differential signal Vin_N_C output from the second output terminal of the differential signal output circuit 600 into a unidirectional detection signal and extract the envelope features of the signal.

[0036] The third resistor R3 and the second capacitor C2 form a filter circuit to smooth the detected signal, filter out high-frequency noise, and obtain a more stable DC signal. It is recommended that the resistance value of the third resistor R3 be more than 50 times that of the end matching resistor R8, so as to reduce the impact on the end matching impedance. The RC time constant of the third resistor R3 × the second capacitor C2 needs to be designed according to the frequency range of the second single-ended differential signal Vin_N_C. The RC time should not be greater than the rise time of the second single-ended differential signal Vin_N_C, so as to select the capacitance value of the second capacitor C2.

[0037] The fourth resistor R4 is a capacitor discharge resistor, used to discharge the charge of the second capacitor C2 when the second single-ended differential signal Vin_N_C has no amplitude for a long time, until the second single-ended differential signal Vin_N_C has an actual voltage value. The RC time constant of the third resistor R3×C2 is more than 50 times greater than the frequency range of the second single-ended differential signal Vin_N_C, so as to select the resistance value of the fourth resistor R4. The second sampling circuit 200 samples the peak voltage of the second single-ended differential signal Vin_N_C and outputs the second peak voltage VN_det.

[0038] Through the above technical solution, the second diode D2 utilizes its unidirectional conductivity to achieve the detection function, converting the second single-ended differential signal Vin_N_C into a unidirectional detection signal, which can efficiently extract the envelope features of the signal. R3 and C2 form a filter circuit, which can smooth the unidirectional detection signal after detection, effectively filter out high-frequency noise in the signal, and output a stable signal. The RC time constant of R3×C2 is not greater than the rise time of the differential signal, ensuring that peak sampling lag is avoided due to RC delay. When the second single-ended differential signal Vin_N_C has no amplitude for a long time, R4 discharges the charge stored in C2 to ensure the accuracy of the sampling results when detecting the signal and avoid false peaks. The resistance value of R4 is selected by designing the RC time constant of R3×C2 to be more than 50 times the signal frequency range, so that the charge is discharged when the single-ended differential signal disappears.

[0039] In some embodiments, the first sampling circuit 100 includes: a first amplifier A1, a third diode D3, a third capacitor C3, and a fifth resistor R5. The first amplifier A1 has its non-inverting input terminal electrically connected to the first output terminal of the differential signal output circuit 600, its inverting input terminal electrically connected to the fifth connection node between the third diode D3 and the first comparator circuit 300, and its output terminal electrically connected to the anode of the third diode D3. The cathode of the third diode D3 is electrically connected to the input terminal of the first comparator circuit 300. One end of the third capacitor C3 is electrically connected to the fifth connection node between the third diode D3 and the first comparator circuit 300, and the other end of the third capacitor C3 is electrically connected to a ground node. One end of the fifth resistor R5 is electrically connected to the sixth connection node between the fifth connection node and the first comparator circuit 300, and the other end of the fifth resistor R5 is electrically connected to a ground node.

[0040] Figure 4 Figure (a) shows another peak voltage sampling circuit for Vin_P_C and Vin_N_C signals. The fifth connection node is the connection between the cathode of the third diode D3 and the first comparator circuit 300. One end of the third capacitor C3 is electrically connected to the fifth connection node. The sixth connection node is the connection between the fifth connection node and the first comparator circuit 300. One end of the fifth resistor R5 is electrically connected to the sixth connection node.

[0041] The first sampling circuit 100 uses a first amplifier A1 (i.e., an operational amplifier). The non-inverting input of the first amplifier A1 is electrically connected to the first output of the differential signal output circuit 600 to receive the first single-ended differential signal Vin_P_C. The inverting input of the first amplifier A1 is connected to the output to form a voltage buffer, which plays the role of impedance transformation and signal buffering, ensuring that the first single-ended differential signal Vin_P_C can be stably transmitted to the subsequent circuit, isolating the impedance influence between the preceding and following stages, and eliminating the voltage drop effect of the diode.

[0042] The third diode D3 serves as a detector element, utilizing its unidirectional conductivity to detect the buffered signal and extract the amplitude component of the first single-ended differential signal Vin_P_C. The third capacitor C3 is a filter capacitor used to smooth the detected signal, filter out high-frequency noise, and obtain a stable detector output.

[0043] The fifth resistor R5 is a capacitor discharge resistor, used to discharge the charge of the third capacitor C3 when the first single-ended differential signal Vin_P_C has no amplitude for a long time. The RC time constant of the fifth resistor R5 × the third capacitor C3 is more than 50 times greater than the frequency range of the first single-ended differential signal Vin_P_C. After the first sampling circuit 100 passes through the first single-ended differential signal Vin_P_C, the first peak voltage VP_det of the first single-ended differential signal Vin_P_C is output.

[0044] Through the above technical solution, the operational amplifier is configured as a voltage buffer to achieve impedance matching and isolation between the preceding and following stages, ensuring the stability of the transmission of the first single-ended differential signal Vin_P_C. The third diode D3 uses its unidirectional conductivity to detect the buffered signal, accurately separating the amplitude component of the first single-ended differential signal Vin_P_C, providing an effective signal basis for peak sampling. The third capacitor C3 acts as a filter capacitor, smoothing the unidirectional detected signal, filtering out high-frequency noise, and converting the unidirectional detected signal into a stable signal. When the first single-ended differential signal Vin_P_C has no amplitude for a long time, the fifth resistor R5 releases the charge stored in the third capacitor C3, ensuring the accuracy of the signal sampling results. By designing the RC time constant of R5×C3 to be more than 50 times the signal frequency range, the charge can be quickly discharged when the signal has no amplitude, thereby improving the sampling accuracy.

[0045] In some embodiments, the second sampling circuit 200 includes: a second amplifier A2, a fourth diode D4, a fourth capacitor C4, and a sixth resistor R6. The non-inverting input of the second amplifier A2 is electrically connected to the second output of the differential signal output circuit 600; the inverting input of the second amplifier A2 is electrically connected to the seventh connection node between the fourth diode D4 and the second comparator circuit 400; the output of the second amplifier A2 is electrically connected to the anode of the fourth diode D4; the cathode of the fourth diode D4 is electrically connected to the input of the second comparator circuit 400; one end of the fourth capacitor C4 is electrically connected to the seventh connection node between the fourth diode D4 and the second comparator circuit 400, and the other end of the fourth capacitor C4 is electrically connected to a ground node; one end of the sixth resistor R6 is electrically connected to the eighth connection node between the seventh connection node and the second comparator circuit 400, and the other end of the sixth resistor R6 is electrically connected to a ground node.

[0046] Another structure of the second sampling circuit 200 is as follows: Figure 4 As shown in Figure (b).

[0047] The second sampling circuit 200 uses a second amplifier A2 (i.e., an operational amplifier). The non-inverting input of the second amplifier A2 is electrically connected to the second output of the differential signal output circuit 600 to receive the second single-ended differential signal Vin_N_C. The inverting input of the second amplifier A2 is connected to the output to form a voltage buffer, which plays the role of impedance transformation and signal buffering, ensuring that the second single-ended differential signal Vin_N_C can be stably transmitted to the subsequent circuit, isolating the impedance influence between the preceding and following stages, and eliminating the voltage drop effect of the diode.

[0048] The fourth diode D4 serves as a detector element, utilizing its unidirectional conductivity to detect the buffered signal and extract the amplitude component of the second single-ended differential signal Vin_N_C. The fourth capacitor C4 is a filter capacitor, used to smooth the detected signal, filter out high-frequency noise, and obtain a stable detector output.

[0049] The sixth resistor R6 is a capacitor discharge resistor, used to discharge the charge of the fourth capacitor C4 when the second single-ended differential signal Vin_N_C has no amplitude for a long time. It is recommended that the RC time constant of the sixth resistor R6 × the fourth capacitor C4 be more than 50 times greater than the frequency range of the second single-ended differential signal Vin_N_C. After the second sampling circuit 200 passes through the second single-ended differential signal Vin_N_C, the second peak voltage VN_det of the second single-ended differential signal Vin_N_C is output.

[0050] Through the above technical solution, the amplifier is configured as a voltage buffer to achieve impedance matching and isolation between the preceding and following stages, ensuring the stability of the second single-ended differential signal Vin_N_C transmission. The fourth diode D4 uses its unidirectional conductivity to detect the buffered signal, accurately separating the amplitude component of the second single-ended differential signal Vin_N_C, providing an effective signal basis for peak sampling. The fourth capacitor C4 acts as a filter capacitor, smoothing the unidirectional detected signal, effectively filtering out high-frequency noise in the signal, and converting the unidirectional detected signal into a stable signal. When the second single-ended differential signal Vin_N_C has no amplitude for a long time, the sixth resistor R6 releases the charge stored in the fourth capacitor C4, ensuring the accuracy of the signal sampling results. By designing the RC time constant of R6×C4 to be more than 50 times the signal frequency range, the charge can be quickly discharged when the signal has no amplitude, thereby improving the sampling accuracy.

[0051] In some embodiments, the first comparison circuit 300 includes: a first comparator A3 and a potentiometer RP, wherein the non-inverting input terminal of the first comparator A3 is electrically connected to the output terminal of the first sampling circuit 100, the inverting input terminal of the first comparator A3 is connected to the first terminal of the potentiometer RP, and the output terminal of the first comparator A3 is electrically connected to the input terminal of the detection circuit 500; the second terminal of the potentiometer RP is electrically connected to the power supply node VCC, and the third terminal of the potentiometer RP is electrically connected to the ground node GND.

[0052] The structure of the first comparator circuit 300 is as follows: Figure 5 As shown in Figure (a), the non-inverting input of the first comparator A3 is electrically connected to the output of the first sampling circuit 100, and is used to receive the first peak voltage VP_det of the first single-ended differential signal transmitted by the first sampling circuit 100. The inverting input of the first comparator A3 is connected to the potentiometer RP. The potentiometer RP divides the voltage from the power supply VCC to obtain the threshold voltage Vth, which can realize the adjustment of the threshold and adapt to the detection requirements of different signal amplitudes.

[0053] The first comparator A3 compares the input first peak voltage VP_det with the threshold voltage Vth. The first comparator A3 outputs a first level signal VP_OK, which is either high or low, to indicate whether the peak voltage of the first single-ended differential signal exceeds the threshold voltage Vth.

[0054] If the peak voltage of the first single-ended differential signal is greater than or equal to the threshold voltage Vth, then the first level signal VP_OK output by the first comparator circuit 300 is high.

[0055] If the peak voltage of the first single-ended differential signal is less than the threshold voltage Vth, then the first level signal VP_OK output by the first comparator circuit 300 is low.

[0056] The detection circuit 500 receives the first level signal sent by the first comparison circuit 300. If the first level signal VP_OK is high, the detection circuit 500 outputs the detection result that the swing of the first single-ended differential signal is normal. If the first level signal VP_OK is low, the detection circuit 500 outputs the detection result of the target single-ended differential signal in an abnormal state as the detection result of the first single-ended differential signal.

[0057] Through the above technical solution, the potentiometer RP generates a threshold voltage Vth by dividing the power supply VCC. By adjusting the resistance of the potentiometer, the value of Vth can be flexibly changed, enabling the first comparison circuit to adapt to the detection requirements of differential signals with different amplitude ranges, thereby improving the versatility and scenario adaptability of the circuit. The first comparison unit A3 compares the first peak voltage VP_det with the threshold voltage Vth in real time, and provides intuitive feedback on whether the swing of the first single-ended differential signal is normal through high / low levels, thereby achieving rapid judgment of the signal state.

[0058] In some embodiments, the second comparison circuit 400 includes: a second comparison element A4, the non-inverting input terminal of the second comparison element A4 being electrically connected to the output terminal of the second sampling circuit 200, the inverting input terminal of the second comparison element A4 being electrically connected to the first terminal of the potentiometer Rp, and the output terminal of the second comparison element A4 being electrically connected to the input terminal of the detection circuit 500.

[0059] The structure of the second comparator circuit 400 is as follows: Figure 5 As shown in Figure (b), the non-inverting input of the second comparator A4 is electrically connected to the output of the second sampling circuit 200 to receive the second peak voltage VN_det of the second single-ended differential signal transmitted by the second sampling circuit 200. The inverting input of the second comparator A4 is connected to the first terminal of the potentiometer. The voltage at the first terminal of the potentiometer Rp is the threshold voltage Vth. The threshold voltage Vth is obtained by voltage division from the power supply VCC by the potentiometer Rp, which can realize the adjustment of the threshold and adapt to the detection requirements of different signal amplitudes.

[0060] The second comparator A4 compares the input second peak voltage VN_det with the threshold voltage Vth. The second comparator A4 outputs a second level signal VN_OK, which is either high or low, to indicate whether the peak voltage of the second single-ended differential signal exceeds the threshold voltage Vth.

[0061] If the peak voltage of the second single-ended differential signal is greater than or equal to the threshold voltage Vth, then the second level signal VN_OK output by the second comparator circuit 400 is high.

[0062] If the peak voltage of the second single-ended differential signal is less than the threshold voltage Vth, then the second level signal VN_OK output by the second comparator circuit 400 is low.

[0063] The detection circuit 500 receives the second level signal sent by the second comparison circuit 400. If the second level signal VN_OK is high, the detection circuit 500 outputs the detection result that the swing of the second single-ended differential signal is normal. If the second level signal VN_OK is low, the detection circuit 500 outputs the detection result of the target single-ended differential signal in an abnormal state as the second single-ended differential signal.

[0064] Through the above technical solution, the inverting input terminal of the second comparator is connected to a potentiometer Rp. By adjusting the resistance value of the potentiometer, the magnitude of Vth can be flexibly changed, enabling the second comparator circuit to adapt to the detection requirements of differential signals with different amplitude ranges, thereby improving the versatility and scenario adaptability of the circuit. The second comparator compares the second peak voltage VN_det with the threshold voltage Vth in real time, and provides intuitive feedback on whether the swing of the second single-ended differential signal is normal through high / low levels, thereby achieving rapid judgment of the signal state.

[0065] Figure 6 This is a waveform diagram comparing a single-ended serial signal with a threshold level under normal conditions. The first single-ended differential signal Vin_P_C is the positive terminal waveform of the original differential signal after DC blocking (the Vin_P_C waveform is similar), exhibiting a fixed frequency of high and low level code pattern changes. VP_det is the detection signal waveform after processing such as detection, and its envelope reflects the amplitude characteristics of the first single-ended differential signal. The VICM common-mode voltage is the common-mode level reference of the first single-ended differential signal Vin_P_C.

[0066] Figure 7 This is a waveform diagram comparing a single-ended serial signal with a threshold level under abnormal conditions. When the first single-ended differential signal Vin_P stops flipping abnormally (similar to Vin_N), the Vin_P_C signal after DC blocking will remain near the common-mode level VICM. The first capacitor C1 will discharge through the second resistor R2, or the third capacitor C3 will discharge through the fifth resistor R5, and VP_det will continue to drop to near VICM.

[0067] According to the differential signal anomaly detection circuit proposed in this embodiment, a first sampling circuit acquires the first peak voltage of a first single-ended differential signal, a second sampling circuit acquires the second peak voltage of a second single-ended differential signal, a first comparison circuit obtains a first level signal based on the first peak voltage, a second comparison circuit obtains a second level signal based on the second peak voltage, and a detection circuit determines the single-ended differential signal in an abnormal state based on the first and second level signals. This solves the problem that existing methods for detecting open circuits or poor signals in differential signal links monitor and judge the entire differential signal, failing to identify individual signal line amplitude anomalies. By using a single-ended signal line peak sampling circuit, the peak voltage of a single signal line is sampled in real time and compared with a threshold voltage, enabling online detection of the single-ended signal line amplitude. This allows for timely identification of abnormal single-ended signal lines, facilitating maintenance personnel in quickly diagnosing contact problems and open circuits in such high-speed differential signal systems. The circuit structure is simple, using common diodes, operational amplifiers, resistors, capacitors, and other components, reducing hardware design and manufacturing costs.

[0068] Next, with reference to the accompanying drawings, the anomaly detection method for differential signals proposed according to an embodiment of the present invention is described.

[0069] Figure 8 This is a schematic diagram of an anomaly detection method for differential signals according to an embodiment of the present invention.

[0070] like Figure 8 As shown, the anomaly detection method for differential signals is applied to... Figure 1 The differential signal anomaly detection circuit shown in the embodiment includes the following steps: Step S801: In response to the signal detection request, the first single-ended differential signal and the first peak voltage of the first single-ended differential signal output from the first output terminal of the differential signal output circuit are acquired through the first sampling circuit, and the second single-ended differential signal and the second peak voltage of the second single-ended differential signal output from the second output terminal of the differential signal output circuit are acquired through the second sampling circuit.

[0071] The signal detection request is a request to detect whether the first single-ended differential signal and the second single-ended differential signal are abnormal.

[0072] Step S802: Obtain a first level signal based on the first peak voltage, and obtain a second level signal based on the second peak voltage.

[0073] Step S803: Determine the target single-ended differential signal in an abnormal state based on the first level signal and the second level signal.

[0074] It should be noted that the description of the features of the differential signal anomaly detection circuit in the corresponding embodiment can be found in the relevant description of the differential signal anomaly detection method in the above embodiment, and will not be repeated here.

[0075] According to the differential signal anomaly detection method proposed in this embodiment of the invention, in response to a signal detection request, a first sampling circuit acquires a first single-ended differential signal and a first peak voltage of the first single-ended differential signal output from a first output terminal of a differential signal output circuit; a second sampling circuit acquires a second single-ended differential signal and a second peak voltage of the second single-ended differential signal output from a second output terminal of the differential signal output circuit; a first level signal is obtained based on the first peak voltage, and a second level signal is obtained based on the second peak voltage; the target single-ended differential signal in an abnormal state is determined based on the first level signal and the second level signal. This solves the problem that existing methods for detecting differential signal link breaks or signal malfunctions monitor and judge the entire differential signal, failing to identify individual signal line amplitude anomalies. It enables online detection of single-ended signal line amplitudes, allowing for timely identification of abnormal single-ended signal lines.

[0076] This invention also provides an electronic device, including the above-described differential signal anomaly detection circuit.

[0077] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0078] The above provides a detailed description of the differential signal anomaly detection circuit, method, and electronic device provided by this invention. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of these embodiments are only intended to aid in understanding the method and core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims of this invention.

Claims

1. An anomaly detection circuit for differential signals, characterized in that, include: The circuit comprises a first sampling circuit, a second sampling circuit, a first comparison circuit, a second comparison circuit, and a detection circuit, wherein... The input terminal of the first sampling circuit is electrically connected to the first output terminal of the differential signal output circuit. The first sampling circuit is configured to acquire the first single-ended differential signal output from the first output terminal of the differential signal output circuit and the first peak voltage of the first single-ended differential signal. The input terminal of the second sampling circuit is electrically connected to the second output terminal of the differential signal output circuit. The second sampling circuit is configured to acquire the second single-ended differential signal output from the second output terminal of the differential signal output circuit and the second peak voltage of the second single-ended differential signal. The input terminal of the first comparison circuit is electrically connected to the output terminal of the first sampling circuit, and the first comparison circuit is configured to obtain a first level signal based on the first peak voltage; The input terminal of the second comparison circuit is electrically connected to the output terminal of the second sampling circuit, and the second comparison circuit is configured to obtain a second level signal based on the second peak voltage; The input terminal of the detection circuit is electrically connected to the output terminal of the first comparison circuit and the output terminal of the second comparison circuit, respectively. The detection circuit is configured to determine the target single-ended differential signal in an abnormal state based on the first level signal and the second level signal. The first sampling circuit includes: a first diode, the anode of which is electrically connected to a first output terminal of the differential signal output circuit, and the cathode of which is electrically connected to an input terminal of the first comparator circuit; a first resistor, one end of which is connected to a first connection node between the first diode and the first comparator circuit; a first capacitor, one end of which is electrically connected to the other end of the first resistor, and the other end of which is electrically connected to a ground node; and a second resistor, one end of which is electrically connected to a second connection node between the first connection node and the first comparator circuit, and the other end of which is electrically connected to the ground node.

2. The anomaly detection circuit for differential signals according to claim 1, characterized in that, The second sampling circuit includes: The second diode has its anode electrically connected to the second output terminal of the differential signal output circuit, and its cathode electrically connected to the input terminal of the second comparator circuit. A third resistor, one end of which is connected to a third connection node between the second diode and the second comparator circuit; The second capacitor has one end electrically connected to the other end of the third resistor, and the other end of the second capacitor is electrically connected to the grounding node. A fourth resistor, one end of which is electrically connected to the fourth connection node between the third connection node and the second comparison circuit, and the other end of which is electrically connected to the ground node.

3. The anomaly detection circuit for differential signals according to claim 1, characterized in that, The first sampling circuit includes: a first amplifier, a third diode, a third capacitor, and a fifth resistor, wherein, The first amplification element has its non-inverting input terminal electrically connected to the first output terminal of the differential signal output circuit, its inverting input terminal electrically connected to the fifth connection node between the third diode and the first comparator circuit, and its output terminal electrically connected to the anode of the third diode. The cathode of the third diode is electrically connected to the input terminal of the first comparator circuit; One end of the third capacitor is electrically connected to the fifth connection node between the third diode and the first comparator circuit, and the other end of the third capacitor is electrically connected to the ground node. One end of the fifth resistor is electrically connected to the sixth connection node between the fifth connection node and the first comparator circuit, and the other end of the fifth resistor is electrically connected to the ground node.

4. The anomaly detection circuit for differential signals according to claim 3, characterized in that, The second sampling circuit includes: The second amplifier, the fourth diode, the fourth capacitor, and the sixth resistor, among which, The second amplifier has its non-inverting input terminal electrically connected to the second output terminal of the differential signal output circuit, its inverting input terminal electrically connected to the seventh connection node between the fourth diode and the second comparator circuit, and its output terminal electrically connected to the anode of the fourth diode. The cathode of the fourth diode is electrically connected to the input terminal of the second comparator circuit; One end of the fourth capacitor is electrically connected to the seventh connection node between the fourth diode and the second comparator circuit, and the other end of the fourth capacitor is electrically connected to the ground node. One end of the sixth resistor is electrically connected to the eighth connection node between the seventh connection node and the second comparison circuit, and the other end of the sixth resistor is electrically connected to the ground node.

5. The anomaly detection circuit for differential signals according to claim 1, characterized in that, The first comparator circuit includes: The first comparator and the potentiometer, wherein... The non-inverting input terminal of the first comparator is electrically connected to the output terminal of the first sampling circuit, the inverting input terminal of the first comparator is connected to the first terminal of the potentiometer, and the output terminal of the first comparator is electrically connected to the input terminal of the detection circuit. The second terminal of the potentiometer is electrically connected to the power supply node, and the third terminal of the potentiometer is electrically connected to the ground node.

6. The anomaly detection circuit for differential signals according to claim 5, characterized in that, The second comparator circuit includes: The second comparator has its non-inverting input terminal electrically connected to the output terminal of the second sampling circuit, its inverting input terminal electrically connected to the first terminal of the potentiometer, and its output terminal electrically connected to the input terminal of the detection circuit.

7. The anomaly detection circuit for differential signals according to claim 6, characterized in that, The differential signal output circuit includes: The fifth capacitor, one end of which is electrically connected to the first signal input terminal; The seventh resistor, one end of which is electrically connected to the ninth connection node between the other end of the fifth capacitor and the input terminal of the first sampling circuit; The sixth capacitor, one end of which is electrically connected to the second signal input terminal; The eighth resistor has one end electrically connected to the tenth connection node between the other end of the sixth capacitor and the input terminal of the second sampling circuit.

8. An electronic device, characterized in that, An anomaly detection circuit for differential signals as described in any one of claims 1-7.

9. A method for anomaly detection in differential signals, characterized in that, An anomaly detection circuit applied to a differential signal as described in any one of claims 1-7, wherein the method comprises: In response to a signal detection request, the first sampling circuit acquires the first single-ended differential signal and the first peak voltage of the first single-ended differential signal output from the first output terminal of the differential signal output circuit, and the second sampling circuit acquires the second single-ended differential signal and the second peak voltage of the second single-ended differential signal output from the second output terminal of the differential signal output circuit. The first level signal is obtained based on the first peak voltage, and the second level signal is obtained based on the second peak voltage; The target single-ended differential signal in an abnormal state is determined based on the first level signal and the second level signal.

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