A non-uniform partition thermal network modeling method based on temperature gradient prior information

Abstract

The application relates to a non-uniform partition thermal network modeling method based on temperature gradient prior information, comprising the following steps: acquiring prior temperature gradient information of a power device chip surface; based on the prior temperature gradient information, a plurality of physical partitions with non-uniform areas are obtained by partitioning the power device chip surface; a non-uniform partition thermal network topology is constructed in combination with the number of parallel power device chips; an overload compensation electro-thermal coupling iterative power correction model is constructed, and the output is a partition iterative correction loss power; temperature field data of the power device chip is iteratively solved based on the partition iterative correction loss power, and the transient temperature distribution and the highest junction temperature of the power device chip are obtained based on the temperature field data. Through the construction of the overload compensation electro-thermal coupling iterative power correction model, the output is the partition iterative correction loss power; the power loss change under different load conditions can be dynamically adapted, and the temperature prediction deviation problem caused by the fixed partition and static parameters of the traditional modeling can be effectively solved.

Description

Technical Field

[0001] This application relates to the field of thermal modeling technology for power electronic devices, specifically to a non-uniform partitioned thermal network modeling method based on prior information of temperature gradient. Background Technology

[0002] Insulated Gate Bipolar Transistor (IGBT) power devices, as core power devices in power electronic systems, are widely used in renewable energy power generation, electric vehicles, rail transportation, and industrial drives. During operation, these devices continuously endure complex electrothermal stresses, and their junction temperature is a key indicator determining their reliability and service life. Statistics show that over half of power device failures originate from thermal failures. Therefore, accurately acquiring the temperature distribution of IGBT chips, identifying local hotspots, and achieving high-precision junction temperature prediction under all operating conditions are crucial for optimizing device thermal management, lifespan assessment, and over-temperature protection. Due to limitations in module packaging structure, the internal temperature of the chip cannot be directly measured, making online accurate junction temperature monitoring a key challenge for the industry.

[0003] Current mainstream junction temperature detection methods include infrared measurement, physical contact, thermistor parameter methods, and thermal network modeling. Among these, thermal network modeling, with its advantages of online computation and engineering applicability, has become a core research direction for real-time junction temperature monitoring. However, existing traditional thermal network modeling techniques have many inherent technical defects, making it difficult to balance high accuracy and real-time performance requirements. First, there is an irreconcilable contradiction between model computing power and modeling accuracy. Traditional one-dimensional thermal network models have fast computation speeds but completely ignore the lateral temperature gradient characteristics of the chip, only outputting the average junction temperature and failing to identify local hot spots. Three-dimensional uniform partitioned thermal network models, in order to improve accuracy, have a large number of nodes, high equation orders, and serious computational redundancy, failing to meet the needs of online real-time monitoring. Second, existing modeling methods do not utilize prior information about the chip's temperature gradient and generally use fixed uniform grid partitioning, which does not adapt to the actual temperature distribution characteristics of IGBT chips. The actual temperature field of IGBT chips exhibits a non-uniform distribution characteristic of high temperature and high gradient at the center and low temperature and low gradient at the edges. Uniform partitioning leads to wasted computing power in low-temperature, flat areas and insufficient partitioning accuracy in core hot spot areas, making it impossible to accurately capture steep temperature gradients and resulting in poor hot spot prediction accuracy. Furthermore, traditional thermal network models often rely on the average junction temperature of the chip as the output, while device thermal failures are mostly caused by extreme temperatures of local hot spots. Especially under overload conditions, the difference between the average junction temperature and the highest junction temperature can reach more than 10K, which easily leads to underestimation of thermal stress, protection hysteresis, and sudden device failure. At the same time, existing parameter identification methods use independent fitting modes for steady-state and transient parameters, lacking parameter compatibility verification and unified constraints. This easily leads to physical mismatches in thermal resistance and thermal capacity matrices, resulting in problems where the model achieves steady-state accuracy but distorts dynamic response. In addition, traditional modeling lacks quantitative optimization mechanisms and operating condition adaptive capabilities. The number of partitions depends entirely on manual experience, which is highly subjective and random. It cannot dynamically balance modeling accuracy, temperature field reproduction, and computing power based on real-time temperature gradients. Moreover, it does not consider the electrothermal coupling characteristics of IGBTs and the iterative divergence problem under large gradient overload conditions. Under extreme conditions, the model prediction accuracy collapses significantly, making it difficult to adapt to mass production operation scenarios with multiple operating conditions and high overloads. In summary, there is an urgent need for a high-precision thermal network modeling method based on prior information of temperature gradient, non-uniform adaptive partitioning, quantifiable optimization, and adaptability to all operating conditions, in order to solve many of the shortcomings of existing technologies.

[0004] Therefore, this invention proposes a non-uniform partitioned thermal network modeling method based on prior information of temperature gradient. Summary of the Invention

[0005] To overcome the shortcomings of the prior art, this application provides a non-uniform partitioned thermal network modeling method based on temperature gradient prior information, specifically adopting the following technical solution.

[0006] A method for modeling non-uniform partitioned thermal networks based on prior information of temperature gradient includes the following steps.

[0007] The prior temperature gradient information of the power device chip surface is obtained; the real-time on-current and real-time on-voltage drop of the power device are collected; based on the prior temperature gradient information, the surface of the power device chip is divided into multiple non-uniform physical partitions.

[0008] Each physical partition is defined as a thermal network node, and a non-uniform partition thermal network topology is constructed by combining the number of power device chips connected in parallel.

[0009] Based on the aforementioned thermal network topology, an overload compensation electrothermal coupling iterative power correction model is constructed. The inputs of the overload compensation electrothermal coupling iterative power correction model are the real-time on-state current and real-time on-state voltage drop of the power device, and the output is the partitioned iterative correction loss power. Based on the partitioned iterative correction loss power, the temperature field data of the power device chip is iteratively solved, and the transient temperature distribution and maximum junction temperature of the power device chip are obtained based on the temperature field data.

[0010] The above technical solution divides the surface of the power device chip into multiple non-uniform physical partitions based on prior temperature gradient information, breaking the limitations of the traditional uniform partitioning mode and adapting to the real non-uniform temperature distribution characteristics of the chip. Each physical partition is defined as a thermal network node, and a non-uniform partition thermal network topology is constructed by combining the number of parallel power device chips. This topology can match the heat transfer characteristics of multi-chip parallel operation and improve the physical realism of the topology. An overload compensation electrothermal coupling iterative power correction model is constructed based on the thermal network topology, which can dynamically correct the actual power loss of each partition and fit the electrothermal coupling characteristics of IGBT. Based on the partition iterative correction of power loss, the temperature field data of the power device chip is iteratively solved to obtain the transient temperature distribution and the highest junction temperature of the power device chip. This solves the problem that the traditional model can only predict the average junction temperature and cannot accurately capture the hot spot extreme value, thus improving the accuracy of junction temperature prediction under all operating conditions.

[0011] As an optional embodiment of the present invention, a temperature gradient saturation compensation factor is configured in the calculation process of the partitioned iterative correction of power loss. The temperature gradient saturation compensation factor is used to suppress the over-correction of electrothermal iteration under extreme operating conditions.

[0012] The above technical solution effectively addresses the problems of iterative divergence, model overfitting, and temperature prediction accuracy collapse that are prone to occur in traditional electrothermal coupling iteration under extreme conditions of large gradient overload by using a temperature gradient saturation compensation factor to specifically suppress excessive correction of electrothermal iteration under extreme conditions. This improves the operational stability and prediction reliability of the model under overload and variable operating conditions, and avoids the problem of modeling failure under extreme conditions.

[0013] As an optional solution of the present invention, the continuous temperature field distribution of the power device chip is extracted based on the prior temperature gradient information, the maximum gradient magnitude of the power device chip is calculated based on the continuous temperature field distribution, and the corresponding temperature gradient saturation compensation factor is calculated based on the maximum gradient magnitude.

[0014] The above technical solution extracts the continuous temperature field distribution of the power device chip based on prior temperature gradient information, calculates the maximum gradient amplitude of the power device chip based on the continuous temperature field distribution, and then calculates the corresponding temperature gradient saturation compensation factor based on the maximum gradient amplitude. The compensation parameters are generated based on the chip's real global temperature gradient characteristics, so that the temperature gradient saturation compensation factor matches the chip's real-time thermal distribution state, ensuring the working condition adaptability and physical authenticity of the compensation mechanism, and improving the accuracy of iterative correction under all working conditions.

[0015] As an optional solution of the present invention, the temperature gradient saturation compensation factor adopts a segmented adaptive value selection mechanism, and the compensation weight under different operating conditions is matched according to the relative relationship between the real-time maximum gradient amplitude of the power device chip and the reference gradient amplitude under rated operating conditions.

[0016] Through the above technical solution, the temperature gradient saturation compensation factor of the present invention adopts a segmented value mechanism. Based on the relative relationship between the real-time maximum gradient amplitude of the power device chip and the reference gradient amplitude under rated operating conditions, the compensation weight under different operating conditions is matched. It can achieve full-scenario adjustment with accurate fidelity under normal operating conditions, smooth adaptation under medium gradient operating conditions, and fallback anti-divergence under ultra-large gradient overload operating conditions. There is no blind spot in operating condition adaptation and no parameter mutation problem. It can effectively adapt to all operating conditions of power devices, such as light load, rated, and overload.

[0017] As an optional embodiment of the present invention, the overload compensation electrothermal coupling iterative power correction model is as follows.

[0018] ; .

[0019] .

[0020] In the formula, Iterative correction of power loss for partitioning; This represents the total area of ​​the power device chip. This represents the total real-time power loss of the power device. This is the loss-temperature sensitivity coefficient; For the first Partition number Next iteration temperature; For the entire chip domain Average temperature over the next iteration; This represents the number of iteration steps. This is the temperature gradient saturation compensation factor. Provides real-time on-current for power devices; For real-time on-state voltage drop of power devices; Let i be the area of ​​the i-th non-uniform sub-region; This represents the real-time maximum gradient magnitude of the power device chip. This is the reference gradient amplitude under rated operating conditions.

[0021] Through the above technical solution, this invention constructs an overload compensation electrothermal coupling iterative power correction model. By calculating the real-time total power loss of the device through the real-time on-current and real-time on-voltage drop of the power device, and combining the total chip area, sub-region area, loss-temperature sensitivity coefficient, iterative temperature, and piecewise adaptive temperature gradient saturation compensation factor, the partition iterative correction power loss is solved. This quantitatively realizes the organic combination of IGBT electrothermal coupling effect and large gradient saturation compensation mechanism, which can correct the partition loss deviation under different temperature gradient conditions and solve the problems of loss calculation distortion and low hot spot temperature prediction caused by ignoring the partition temperature difference in traditional models.

[0022] As an optional solution of the present invention, based on the continuous temperature field distribution of the power device chip and with the maximum gradient amplitude as a reference, multiple temperature gradient threshold intervals are divided. The boundary thresholds of each temperature gradient threshold interval are generated by solving the Gaussian second derivative extreme value inflection point criterion. With the isothermal contour line as the physical boundary, non-uniform physical partitions are generated for each temperature gradient threshold interval.

[0023] Through the above technical solution, this invention is based on the continuous temperature field distribution of power device chips. It divides multi-level temperature gradient threshold intervals based on the maximum gradient amplitude. The boundary thresholds of each temperature gradient threshold interval are generated by solving the Gaussian second derivative extreme value inflection point criterion. There is no need to manually preset fixed thresholds. It can adapt to the changes in chip temperature gradient distribution under different operating conditions and avoid the defects of strong subjectivity, fixed parameters, and poor adaptability of manual partitioning. The non-uniform physical partitions of each temperature gradient threshold interval are generated with isothermal contour lines as physical boundaries. It strictly follows the chip temperature gradient distribution law and achieves differentiated partitioning effect of dense partitioning in high gradient regions and sparse partitioning in low gradient regions. It solves the problems of insufficient hot spot accuracy and redundant computing power in low temperature regions in traditional uniform partitioning.

[0024] As an optional solution of the present invention, based on the non-uniform physical partitioning of the temperature gradient threshold range, a hot spot refinement triggering rule is preset. When the gradient amplitude of a local area of ​​the power device chip is greater than 0.7 times the maximum gradient amplitude of the power device chip, it is determined to be a hot spot area and a secondary nested subdivision is initiated.

[0025] Through the above technical solution, the present invention, based on the non-uniform physical partitioning of the temperature gradient threshold range, presets hot spot refinement triggering rules. When the gradient amplitude of a local area of ​​the power device chip is greater than 0.7 times the maximum gradient amplitude of the power device chip, it is determined to be a hot spot area and a secondary nested subdivision is initiated. This can locate the high temperature and high gradient area of ​​the chip core and complete ultra-fine subdivision, which greatly improves the temperature gradient capture accuracy and temperature field reproduction of the hot spot area. At the same time, redundant subdivision is not performed on the medium and low temperature stable areas. While ensuring high accuracy of hot spot modeling, it effectively controls the overall computational overhead and achieves the optimal matching between modeling accuracy and computing power.

[0026] As an optional solution of the present invention, a multi-chip lateral thermal coupling coefficient model is constructed based on the thermal network topology. The asymmetric thermal interference between the parallel power device chips is quantitatively evaluated through the multi-chip lateral thermal coupling coefficient model. The multi-chip lateral thermal coupling coefficient model is as follows.

[0027] .

[0028] In the formula, Let be the lateral thermal coupling coefficient between the p-th power device chip and the q-th power device chip; The reference coupled thermal conductivity constant; These represent the maximum gradient magnitudes of the p-th and q-th power device chips, respectively. This represents the maximum gradient extremum for all power device chips.

[0029] Through the above technical solution, this invention constructs a multi-chip lateral thermal coupling coefficient model based on the thermal network topology. The multi-chip lateral thermal coupling coefficient model is used to quantitatively evaluate the asymmetric thermal interference between parallel power device chips. Based on the defined model formula and combined with the maximum gradient amplitude of each chip and the reference coupling thermal conductivity constant, the differentiated and asymmetric lateral thermal coupling strength between parallel chips can be quantified. This solves the technical problem that traditional thermal network models only consider longitudinal heat transfer and ignore the lateral thermal interference of multi-chips, restores the real heat transfer characteristics under the parallel operation of multi-chips, and greatly improves the overall accuracy of temperature prediction for parallel power devices.

[0030] As an optional embodiment of the present invention, after the step of constructing the non-uniformly partitioned hot network topology, a multi-objective quantization optimization step is further included to solve for the optimal number of partitions, specifically including the following steps.

[0031] Construct a multi-dimensional comprehensive performance evaluation criterion and establish a three-dimensional quantitative performance index system that includes hotspot extreme value prediction accuracy, global temperature field fitting similarity, and model online computation overhead.

[0032] Perform dynamic weight configuration driven by temperature gradient.

[0033] By eliminating pseudo-optimal solutions through multiple constraint checks, the number of globally optimal partitions is obtained, and an optimal hot network topology model is constructed based on the number of globally optimal partitions.

[0034] Through the above technical solutions, a three-dimensional quantitative index system is established by constructing a multi-dimensional comprehensive performance evaluation criterion, which includes the accuracy of hotspot extreme value prediction, the similarity of global temperature field fitting, and the online computational cost of the model. This system comprehensively quantifies modeling performance from three dimensions: accuracy, global fidelity, and real-time computing power. Dynamic weight configuration driven by temperature gradients is used to adapt to different evaluation emphases under different working conditions. By eliminating pseudo-optimal solutions through multiple constraint verifications, the globally optimal number of partitions is selected and the optimal thermal network topology model is constructed. This completely replaces the traditional manual experience-based value selection method, eliminates the randomness and uncertainty of manual modeling, and stably achieves a quantitative optimal balance between model accuracy, temperature fidelity, and computational complexity.

[0035] As an optional solution of the present invention, in the dynamic weight configuration step driven by temperature gradient, the weight coefficients corresponding to the hotspot extreme value prediction accuracy, the weight coefficients corresponding to the global temperature field fitting similarity, and the weight coefficients corresponding to the online computation cost of the model are calculated based on the maximum gradient magnitude of the power device chip; the sum of the weight coefficients of the hotspot extreme value prediction accuracy, the weight coefficients of the global temperature field fitting similarity, and the weight coefficients of the online computation cost of the model is 1.

[0036] Through the above technical solution, the present invention achieves weight normalization configuration, which can dynamically and adaptively adjust the weight ratio of each evaluation dimension according to the real-time temperature gradient of the chip. The large gradient condition focuses on the accuracy of hot spot prediction, while the uniform low temperature condition focuses on reducing computing power consumption. The weight adjustment is continuous and smooth, without manual intervention and without blind spots in the condition switching, further ensuring the objectivity, accuracy and condition adaptability of the optimal partition number solution.

[0037] The technical solution of this application has achieved the following beneficial effects.

[0038] 1. This invention achieves non-uniform physical partitioning based on prior information about chip temperature gradients, matching the actual temperature distribution of the chip. The high-temperature, large-gradient region is partitioned finely, while the low-temperature, small-gradient region is partitioned sparsely. This solves the problems of insufficient accuracy in hotspot areas and redundant computing power in low-temperature regions in uniform partitioning modeling. At the same time, it constructs a dedicated thermal network topology based on the number of parallel chips, fully restoring the heat transfer characteristics under multi-chip parallel operation. Combined with an overload compensation electrothermal coupling iterative power correction model with real-time conduction current and conduction voltage drop as inputs, it dynamically corrects the actual power loss of each partition, characterizing the electrothermal coupling relationship between chip temperature and power loss. This solves the problems of traditional modeling ignoring partition temperature differences and large junction temperature prediction deviations and low transient temperature restoration caused by uniform power loss distribution. It significantly improves the prediction accuracy of transient temperature distribution and maximum junction temperature of power device chips.

[0039] 2. By setting a temperature gradient saturation compensation factor in the electrothermal coupling iterative power correction process, the technical problems of traditional electrothermal iterative algorithms, such as infinite amplification of power correction, model overfitting, iteration divergence, and collapse of temperature prediction accuracy, are specifically addressed under extreme conditions of large gradient overload and high load. Through the constraint and regulation of the compensation factor, the excessive correction behavior of electrothermal iteration under extreme conditions is effectively suppressed, ensuring the stability and convergence of iterative calculation, and improving the adaptability and robustness of the thermal network model under power device overload conditions.

[0040] 3. A quantitative and reproducible overload compensation electrothermal coupling iterative power correction model is used to achieve accurate iterative correction of partitioned power loss. By combining multi-dimensional parameters such as loss-temperature sensitivity coefficient, partition area, and global average temperature, the model characterizes the differential distribution characteristics of power loss in different temperature regions. This model closely matches the real physical characteristics of the positive temperature coefficient of the on-state voltage drop of power device chips, enabling quantitative and controllable compensation effect. This solves the problems of strong randomness, poor reproducibility, and inability to quantify accuracy in traditional empirical correction methods. Attached Figure Description

[0041] Figure 1 This is a flowchart illustrating the non-uniform partitioned thermal network modeling method based on temperature gradient prior information in the embodiments of this application.

[0042] Figure 2 This is a topology diagram of the thermal network model based on the non-uniform partitioned thermal network modeling method using temperature gradient prior information in the embodiments of this application.

[0043] The diagram is labeled as follows: 1-1, First current source; 1-2, Second current source; 1-3, Third current source; 1-N, Nth current source; 2-1-1, First self-heating impedance; 2-2-2, Second self-heating impedance; 2-NN, Nth self-heating impedance; 2-1-2, Equivalent thermal resistance between the first and second nodes; 2-2-3, Equivalent thermal resistance between the second and third nodes; 2-N1-N, Equivalent thermal resistance between the (N-1)th and Nth nodes; 2-1-N, Equivalent thermal resistance between the first and Nth nodes; 2-2-N, Equivalent thermal resistance between the second and Nth nodes; 3-1-1, First section. 3-2-2, Self-heating capacity of the second node; 3-NN, Self-heating capacity of the Nth node; 3-1-2, Heat capacity connecting the first and second nodes; 3-1-3, Heat capacity connecting the first and third nodes; 3-1-N, Heat capacity connecting the first and Nth nodes; 3-2-N, Heat capacity connecting the second and Nth nodes; 3-2-3, Heat capacity connecting the second and third nodes; 3-N1-N, Heat capacity connecting the (N-1)th and Nth nodes; 4-1, Temperature of the first node; 4-2, Temperature of the second node; 4-N, Temperature of the Nth node; 5, Zero reference point. Detailed Implementation

[0044] The present application will now be further described with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present application and should not be construed as limiting the scope of protection of the present application. It should be noted that the following detailed descriptions are exemplary and intended to provide further explanation of the present application.

[0045] like Figure 1 As shown, this invention discloses a method for modeling non-uniform partitioned thermal networks based on prior information of temperature gradients, including the following steps.

[0046] Step S1: Obtain prior temperature gradient information on the chip surface and quantify gradient parameters: Obtain high-precision temperature field and gradient data.

[0047] Step S2: Perform adaptive non-uniform partitioning based on gradient prior information: Based on the temperature gradient field, implement gradient adaptive non-uniform partitioning. Through multi-scale partitioning, local hotspot refinement, and multi-chip collaborative partitioning, the computing resources are accurately matched with the thermal gradient distribution, thus resolving the contradiction between computing power and accuracy.

[0048] Step S3: Construct a non-uniform partitioned thermal network topology: Based on the non-uniform partitioning results, construct an RC thermal network topology with gradient adaptation, multi-dimensional coupling, and accurate physical mechanism. Use heat flow-driven node connection rules to restore the three-dimensional heat transfer and multi-chip asymmetric coupling effect.

[0049] Step S4: Multi-objective quantization optimization to find the optimal number of partitions: After the non-uniform partition topology is formed, the optimal number of partitions is selected by multi-objective global traversal and quantization, replacing manual experience-based values, balancing accuracy, restoration degree and computing power, and solving the problem of randomness in experience-based modeling.

[0050] Step S5, Steady-state and transient coupling parameter identification, compatibility verification and electrothermal coupling iterative correction: Based on the optimal topology model, complete the parameter identification for all operating conditions, and use parameter compatibility quantification criteria, residual constraints and upper limit of iteration number to solve the problems of poor parameter adaptability, lack of constraints and iteration runaway.

[0051] Example 1.

[0052] This embodiment 1 discloses a non-uniform partitioned thermal network modeling method based on temperature gradient prior information, wherein step S1 includes the following steps.

[0053] S11. Constructing a 3D Finite Element Thermal Model: A 3D finite element thermal model of the full-package structure of the target IGBT power device is established. The model completely reproduces the device's hierarchical structure, accurately including the IGBT chip, chip solder layer, DBC direct copper-clad ceramic substrate, DBC solder layer, copper substrate, thermal grease, and heat sink base—a complete layered packaging structure from top to bottom. The core thermophysical parameters of each layer are precisely assigned values ​​based on the device material handbook and industry standard test data. Segmented fitting values ​​are used for different temperature conditions to eliminate the global adaptation error of a single parameter. Boundary conditions are set according to the actual application scenario of the device. The default ambient temperature is set to 25℃, a fixed convection heat transfer coefficient is applied to the bottom of the heat sink, and adiabatic boundaries are set for the remaining non-heat dissipation surfaces, perfectly matching the actual heat dissipation conditions. Core thermophysical parameters include density, specific heat capacity, and thermal conductivity.

[0054] S12. Prior Temperature Field Data Acquisition: Prior temperature gradient information is a global temperature field and gradient feature dataset used for modeling. The original temperature field data is acquired through two independent paths: simulation and actual measurement. Then, the gradient features are calculated uniformly. Single-path or dual-path joint calibration can be selected as needed to ensure the authenticity and reliability of the data: First, the simulation path conducts multi-condition steady-state heat transfer simulation on the built high-precision finite element model, covering rated conditions, light-load conditions, and overload typical conditions, and extracts the continuous temperature distribution function T(x,y) on the chip surface; Second, the experimental measurement path conducts temperature rise tests on the same type of unpackaged IGBT chip using an infrared thermal imager to calibrate the accuracy of the simulation model and obtain the real chip temperature field distribution data.

[0055] S13. Global Temperature Gradient Quantization Calculation: Based on the continuous temperature field distribution T(x,y), solve for the chip surface temperature gradient vector and the maximum gradient magnitude G, providing quantization input for all adaptive mechanisms.

[0056] The formula for calculating the chip surface temperature gradient vector is: .

[0057] In the formula, Chip coordinates Temperature gradient vector at the location; It is a two-dimensional continuous temperature field distribution function; These are the x and y coordinates of the chip plane.

[0058] Maximum gradient magnitude Calculate according to the following formula: .

[0059] In the formula, This represents the chip's maximum gradient amplitude, expressed in °C / mm.

[0060] In this technical solution, the temperature gradient features are fully quantized by solving the temperature gradient vector on the chip surface and the maximum gradient magnitude over the entire domain. This provides reusable, quantifiable, and high-precision prior data support for subsequent adaptive partitioning, weight adjustment, and compensation correction.

[0061] Example 2.

[0062] This embodiment 2 discloses a method for modeling non-uniform partitioned thermal networks based on prior information of temperature gradient, wherein step S2 includes the following steps.

[0063] S21. Temperature Gradient Interval Quantification and Classification: Based on the chip's global temperature gradient distribution field, and using the maximum gradient amplitude G as a normalization benchmark, three levels of temperature gradient threshold intervals—low gradient, medium gradient, and high gradient—are defined. The boundary thresholds for each gradient interval are adaptively generated using the Gaussian second derivative extreme value inflection point criterion, eliminating the need for manually preset fixed thresholds and possessing adaptive characteristics under operating conditions. This criterion is an adaptive boundary identification method adapted to the chip's temperature gradient distribution characteristics. The specific implementation logic is as follows: First, the continuous temperature gradient distribution curve across the chip's global domain is processed by Gaussian smoothing filtering to remove random noise interference during simulation or actual measurement, ensuring the smoothness and effectiveness of the gradient distribution curve. Next, the second derivative of the processed gradient distribution curve is solved, and the positive and negative extreme value inflection points of the second derivative are used as characteristic locations of drastic temperature gradient changes. These inflection points correspond to the physical boundaries of abrupt changes in the chip's thermal conductivity. Based on these two sets of extreme value inflection points, three levels of gradient intervals—high, medium, and low—can be adaptively divided. The interval boundary thresholds can be automatically updated and dynamically adapted according to the real-time operating conditions and temperature gradient distribution status of the IGBT device. This application strictly follows the matching rule that gradient interval level is negatively correlated with partition density and partition area. That is, the greater the temperature gradient, the higher the partition density of the corresponding region and the smaller the partition area of ​​a single region, so as to achieve accurate matching between partition structure and real heat distribution characteristics.

[0064] S22. Non-uniform physical partitioning of isothermal profiles: Using isothermal profiles obtained from finite element simulation or infrared measurements as physical boundaries, physical regions corresponding one-to-one with each temperature gradient interval are generated on the chip surface. This results in a non-uniform distribution characteristic where the higher the temperature, the greater the gradient, the smaller the partition area, and the higher the partition density, perfectly matching the actual heat transfer law of the device. The finite element simulation is performed using Comsol software.

[0065] S23. Secondary nested refinement of high-temperature hotspot areas: Set a hotspot refinement trigger threshold: When the gradient magnitude of a local area is greater than 0.7G, it is determined to be a core hotspot area, and secondary nested refinement is initiated. The number of refinement layers is fixed at 2, so as to achieve ultra-fine hotspot modeling; medium and low temperature areas are not refined to avoid computing power redundancy.

[0066] This technical solution adaptively divides multi-level gradient intervals based on the chip's actual temperature gradient field and the Gaussian second derivative extreme value inflection point criterion. It eliminates the need for manually preset fixed thresholds and dynamically updates partition boundaries according to device operating conditions, solving the problems of fixed thresholds, strong subjectivity, and inability to adapt to fluctuations in operating conditions inherent in traditional manual partitioning. Non-uniform physical partitions are generated using isothermal contour lines as physical boundaries, strictly adhering to the heat transfer law of a negative correlation between gradient and partition density, achieving a close-fitting partitioning effect with denser areas in hot regions and sparser areas in low-temperature regions. Simultaneously, a double-layer nested subdivision mechanism is set up for core hotspot regions with gradient amplitudes greater than 0.7G, while avoiding redundant subdivision in mid-to-low temperature regions. This significantly reduces unnecessary computation while capturing the chip's localized heat concentration and temperature abrupt changes, solving the problems of insufficient accuracy in hotspot modeling and redundant computational power in traditional uniform partitioning, achieving a preliminary optimal match between accuracy and computational power.

[0067] Example 3.

[0068] This embodiment 3 discloses a non-uniform partitioned thermal network modeling method based on temperature gradient prior information, wherein step S3 includes the following steps.

[0069] S31. Define thermal network nodes: Each non-uniform physical partition defined in step S2 is independently defined as a thermal network calculation node. The node temperature is strictly taken as the area-weighted average of the temperatures of all finite element mesh elements within the corresponding partition. The total number of thermal network nodes N is calculated using the following formula: In the formula, This represents the total number of nodes. This refers to the number of chips connected in parallel. This represents the number of partitions per chip.

[0070] The construction of a hot network topology follows these rules.

[0071] (1) The nodes are connected by equivalent thermal resistance Connections are used to describe the thermal conduction coupling between nodes. The connection relationship is determined based on the direction of heat transfer in the prior temperature field: high-temperature nodes are connected to nearby low-temperature nodes by thermal resistance, and the partitions of corresponding temperature levels between adjacent chips are also connected by equivalent thermal resistance. The connection is designed to reflect the thermal coupling effect between parallel chips.

[0072] (2) Each node is connected by an equivalent heat capacity Connected to the environmental reference ground, it characterizes the thermal inertia of the partition.

[0073] (3) Each node is connected to an equivalent heat flow source. This represents the heat injected into the node from the environment. The size of the heat source is related to the power loss and convective heat transfer of the corresponding zone of the node.

[0074] Reference Figure 2 The chip surface is divided into N nodes according to the isotherms, where N is a predetermined value.

[0075] In the construction of the thermal network model topology, the average value of each chip region is used as the region feature value to characterize the temperature characteristics within that region, with the temperature of the first node being 4-1, the temperature of the second node being 4-2, and the temperature of the Nth node being 4-N; that is, T1, T2…T N The nodes are connected by equivalent thermal resistance and thermal capacity, i.e., R. i,j C i,j In addition, each node is connected to the reference node via its self-thermal capacity and self-thermal resistance, i.e., R i,i C i,i .

[0076] Heat capacity can be divided into two categories. The spatial coupling heat capacity between any two nodes i and j is: (i≠j), its corresponding heat capacity matrix C Non-diagonal elements in the array, such as the first node connecting to the second node with heat capacity 3-1-2, the first node connecting to the third node with heat capacity 3-1-3, the first node connecting to the Nth node with heat capacity 3-1-N, the second node connecting to the Nth node with heat capacity 3-2-N, the second node connecting to the third node with heat capacity 3-2-3, and the (N-1)th node connecting to the Nth node with heat capacity 3-N1-N;

[0077] The heat capacity between the node and the reference node is the self-heating capacity C. i,i Corresponding heat capacity matrix C The diagonal elements in the array include the self-heating capacity of the first node (3-1-1), the self-heating capacity of the second node (3-2-2), and the self-heating capacity of the Nth node (3-NN).

[0078] Thermal resistance can be divided into two categories. The equivalent thermal resistance between any two nodes i and j is: (i≠j), which corresponds to the off-diagonal elements in the equivalent thermal resistance matrix, such as the equivalent thermal resistance of the first node and the second node 2-1-2, the equivalent thermal resistance of the second node and the third node 2-2-3, the equivalent thermal resistance of the (N-1)th node and the Nth node 2-N1-N, the equivalent thermal resistance of the first node and the Nth node 2-1-N, and the equivalent thermal resistance of the second node and the Nth node 2-2-N; The thermal resistance between the node and the reference node is the self-heating resistance. , corresponding to the diagonal elements in the heat capacity matrix, such as the first self-heating resistance 2-1-1, the second self-heating resistance 2-2-2, and the Nth self-heating resistance 2-NN; A current source is set at each node to apply power loss, such as the first current source 1-1, the second current source 1-2, the third current source 1-3, and the Nth current source 1-N. A ground is also provided, with the ground being the zero-point reference point 5.

[0079] The non-uniform partitioned thermal network model constructed in this way shows that the node distribution density is positively correlated with the magnitude of the temperature gradient on the chip surface: the node density is high in high-temperature regions with large temperature gradients, and low in low-temperature regions with small temperature gradients.

[0080] S32. Multi-chip asymmetric thermal coupling quantization: Construct a multi-chip lateral thermal coupling coefficient model to quantify the asymmetric thermal interference of parallel chips, solving the problem of non-coupling quantization models in existing technologies.

[0081] The multi-chip lateral thermal coupling coefficient model is as follows: .

[0082] In the formula, Let be the lateral thermal coupling coefficient between the p-th power device chip and the q-th power device chip; The reference coupling thermal conductivity constant ranges from 0.8 to 1.2 W / (K·m), with 1.0 W / (K·m) being preferred. It is determined based on the chip packaging structure, spacing, and material specifications. These are the maximum gradient magnitudes of the p-th and q-th power device chips, respectively; The maximum gradient extremum of all chips is represented; the thermal coupling strength between intermediate and edge chips is quantified by the multi-chip lateral thermal coupling coefficient model, which characterizes the asymmetric thermal coupling characteristics under multi-chip parallel operation. The calibration is performed based on the packaging material, structural dimensions, chip spacing, and substrate thermal conductivity of the power device chip. It serves as a fixed reference constant to characterize the inherent basic thermal conductivity between parallel chips. In this scheme, its value ranges from 0.8 to 1.2 W / (K·m), with a preferred typical value of 1.0 W / (K·m).

[0083] S33, Layered Coupling Topology Connection: Establish a three-dimensional connection system for vertical heat transfer within the chip, horizontal coupling of parallel chips, and heat dissipation to the ground in the global environment, ensuring the physical authenticity of heat transfer and eliminating false cross-level connections.

[0084] In this technical solution, non-uniform physical partitions are used as independent thermal network nodes. An area-weighted average method is employed to accurately define the temperature of each node, closely reflecting the actual thermal state of each partition, unlike traditional methods that rely on single-point values ​​and coarsely assigned averages. Based on the actual heat transfer direction, a topological connection relationship is established between nodes based on thermal resistance, thermal capacity, and heat flow sources, fully replicating the three-dimensional heat transfer mechanism of the chip and avoiding false cross-level connections, ensuring the authenticity of the topological physics. Simultaneously, a multi-chip lateral thermal coupling coefficient model is constructed, which can quantify the intensity of asymmetric thermal interference between parallel chips. This solves the problems of multi-chip coupling distortion and large temperature prediction deviations caused by traditional multi-chip modeling that ignores lateral coupling and only considers longitudinal heat transfer. It restores the differentiated heat transfer characteristics under multi-chip parallel operation conditions, significantly improving the scenario adaptability and physical accuracy of thermal modeling for parallel power devices.

[0085] Example 4.

[0086] This embodiment 4 discloses a non-uniform partitioned thermal network modeling method based on temperature gradient prior information, wherein step S4 includes the following steps.

[0087] S41. Construct a multi-dimensional comprehensive performance evaluation criterion, and the multi-objective comprehensive evaluation function is as follows.

[0088] .

[0089] In the formula, The number of partitions per chip is The smaller the value of the model's overall performance evaluation function, the better the overall performance. The number of non-uniform partitions on the surface of a single chip; For temperature gradient adaptive accuracy weighting coefficients; The adaptive weighting coefficients for temperature field fidelity; To optimize computational complexity, adaptive weighting coefficients are used. This represents the maximum gradient magnitude on the chip surface. This is an indicator of the prediction error of hotspot extreme values; This is an index for the accuracy of temperature field reproduction. Calculate the complexity index for the model; constraints. Ensure effective weight normalization. The independent variable *n* represents the number of non-uniform partitions in a single chip, taking values ​​across the entire range of 1 to 20; hotspot extreme value prediction error index. Temperature field reproduction error index Model computational complexity index The temperature gradient adaptive weighting coefficients are automatically calculated using the corresponding hotspot extreme value dynamic error quantization model, temperature field restoration degree integral model, and computing power complexity quantization model of this invention, respectively. , , The dynamic weighted adaptive mapping model is adaptively solved by inputting the real-time maximum temperature gradient magnitude G. There is no manual subjective assignment throughout the process, and the weight normalization constraint α+β+γ=1 is automatically satisfied, ensuring that the multi-objective evaluation results are objective, reproducible, and adaptable to the operating conditions.

[0090] S42, Temperature gradient driven dynamic weight adaptive configuration, constructs dynamic weight adaptive mapping model, realizes smooth adaptive adjustment under all operating conditions, without sudden changes or blind spots caused by manual switching.

[0091] The dynamic weight adaptive mapping model is as follows: .

[0092] In the formula, The reference gradient amplitude under rated operating conditions is fixed at 8℃ / mm in this embodiment; It is a hyperbolic tangent mapping function, achieving continuous, smooth, and adaptive weighting without sudden changes in operating conditions or blind spots caused by manual switching. The chip temperature is uniform and without gradients. , The model prioritizes ensuring real-time computation; when Ultra-large gradient overload conditions, , The model fully guarantees the accuracy of hotspot predictions, and the entire process is quantified and controllable.

[0093] S43. Establish a three-dimensional performance quantification index system: Construct a dynamic error quantification model for hotspot extreme values, an integral model for the fidelity of temperature field in non-uniform partitions, and a quantification model for the computational complexity of non-uniform partitions; quantify the modeling performance under different numbers of partitions from three dimensions: hotspot extreme value prediction accuracy, global temperature field fitting similarity, and online computational cost of the model. This solves the problem that traditional partition modeling lacks a unified evaluation standard and relies entirely on human experience. It provides a complete and reproducible mathematical evaluation basis for subsequent gradient dynamic weight multi-objective optimization to solve for the globally optimal number of partitions, achieving the optimal balance between model accuracy, fidelity, and real-time performance.

[0094] The dynamic error quantization model for hotspot extreme values ​​is as follows: .

[0095] In the formula, The highest real-time junction temperature of the chip obtained from finite element simulation; The number of partitions is Thermal network models predict real-time maximum junction temperatures; For modeling runtime; The total simulation time is used for modeling; the dynamic error quantification model of hotspot extreme values ​​represents the maximum absolute error of the hotspot temperature in the model under the full time series.

[0096] The integral model for the degree of reduction of the non-uniform temperature field is as follows.

[0097] .

[0098] In the formula, This represents the total effective heat dissipation area of ​​a single chip. For the first The area of ​​a non-uniform sub-region; This is the sub-partition number; IGBT chip coordinates Temperature at the point of finite element simulation; The coordinates of the IGBT chip surface are two-dimensional plane coordinates. For the first The area-weighted average temperature of each sub-region; the integral model for the temperature field reconstruction accuracy of non-uniform regions quantifies the accuracy of the model's temperature field reconstruction through global integral variance. Area-weighted average temperature The area integral average of the temperature of all finite element meshes within the corresponding sub-partition can accurately characterize the overall thermal state of each non-uniform sub-partition, closely matching the actual temperature distribution characteristics of the chip.

[0099] The computational power complexity quantification model for non-uniform partitioning is as follows: .

[0100] In the formula, To normalize the computational complexity, this embodiment uses a three-parallel chip and a single-chip third-order state modeling dimension, with the state matrix dimension being... The computational cost is positively correlated with the square of the matrix dimension. After normalization, the coefficient is fixed at 9. The computational cost quantification model for non-uniform partitioning has its own theoretical basis and is not based on empirical values.

[0101] S44. Model Robustness Screening and Global Optimal Solution: Traversing all values ​​from n=1 to 20, the comprehensive performance evaluation function J(n) for each number of partitions is calculated. The n corresponding to the minimum J(n) is selected as the globally optimal number of partitions. Simultaneously, triple constraints of accuracy lower limit, time delay upper limit, and parameter stability are verified to eliminate pseudo-optimal solutions. Specifically, the accuracy lower limit constraint limits the maximum allowable deviation range of hotspot prediction error and temperature field reconstruction error, ensuring the basic simulation accuracy of the model meets the standards; the time delay upper limit constraint restricts the online computation and iterative solution time of the model, meeting the computing power requirements for real-time simulation and online monitoring; the parameter stability constraint verifies the fluctuation range of model output parameters and temperature prediction error during dynamic switching of multiple operating conditions, eliminating unstable partition schemes prone to oscillation and with weak adaptability. After joint verification and screening by triple constraints, the optimal number of partitions n=3 is determined globally. The final optimal topology model is constructed from the non-uniform partition structure corresponding to this optimal number of partitions, providing a precise model foundation for subsequent parameter identification and electrothermal iterative correction.

[0102] This technical solution constructs a three-dimensional quantitative evaluation system encompassing hotspot extreme value error, temperature field fidelity, and computational complexity. A dynamic weighted adaptive mapping model is introduced, employing a hyperbolic tangent function to achieve continuous and smooth weight adjustment. This eliminates sudden changes in operating conditions and blind spots caused by manual switching. It can adaptively prioritize either accuracy or computational power based on the chip's real-time gradient state: prioritizing reduced computational overhead under low-temperature uniform operating conditions and ensuring hotspot prediction accuracy under large gradient overload conditions. By solving for the optimal number of partitions through a global traversal and superimposing triple constraints on accuracy, latency, and parameter stability to eliminate pseudo-optimal solutions, the optimal topology structure is ultimately obtained, balancing high temperature field fidelity, high hotspot prediction accuracy, and low computational overhead. This achieves optimal quantitative balancing of model performance, adapting to both online real-time simulation and high-precision offline modeling scenarios.

[0103] Example 5.

[0104] This embodiment discloses a method for modeling non-uniform partitioned thermal networks based on prior information of temperature gradient, wherein step S5 includes the following steps.

[0105] S51. Constructing the state-space equations and identifying parameters of the thermal network.

[0106] Based on the topology of the thermal network model, the complete state-space equation of the system is:

[0107] .

[0108] In the formula, for The order heat capacity matrix represents the magnitude of thermal inertia of each partition node; for A real-time temperature vector for each node, where each element represents the area-weighted average temperature of the corresponding partition; for The order thermal conductivity matrix, whose off-diagonal elements and inter-node thermal resistance Relatedly, the diagonal elements are the sum of the thermal conductivities of all elements connected to the node, representing the heat conduction capacity between nodes; for 3D partitioned power loss input vector; For environmental convection heat transfer, 3D environmental convection heat transfer compensation vector; This represents the total number of nodes in the heat network. t represents time.

[0109] The total number of nodes N is a fixed constant determined by the optimal topology of the model; the heat capacity matrix C, the thermal conductivity matrix K, and the environmental convection heat transfer compensation vector F are all inherent parameters of the model, obtained through steady-state and transient dual-condition parameter identification and fitting, and the parameters remain unchanged after modeling; the node temperature vector The state variables for real-time model solving are obtained by iterative calculation of the state space equation; the partitioned power loss input vector P is the operating condition adaptive variable, which is obtained dynamically based on the real-time electrical loss parameters of the device and through the electrothermal coupling iterative correction formula and temperature gradient saturation compensation mechanism of this invention.

[0110] Using the established three-dimensional finite element model, steady-state and transient temperature data under different power loss conditions are extracted, and a two-step method is used to uniformly identify the thermal network parameters.

[0111] (1) Steady-state parameter identification: Under steady-state conditions, the temperature no longer changes, the first term in the original state equation becomes 0, and the equation becomes: .

[0112] Using the steady-state temperature data obtained from finite element analysis at different power Ps, K and F can be uniquely determined using the least squares method.

[0113] (2) Transient parameter identification: Based on the known K and F, the C matrix in the equation needs to be identified. The transient temperature response curves T(t) of each node under different power are extracted from the finite element simulation. The heat capacity matrix C is derived by curve fitting method to make the dynamic response of the model best match the finite element results. The least squares method is used to fit the transient temperature response curves to identify the time constant of each partition of the thermal network and complete the inverse solution of the heat capacity matrix C.

[0114] S52. Steady-state multi-condition fitting and residual constraints: Establish a steady-state fitting residual constraint model, adopt multi-condition least squares fitting, and introduce steady-state fitting residual constraint model criteria to ensure optimal parameters.

[0115] The steady-state fitting residual constraint model is as follows: .

[0116] In the formula, It is the steady-state fitting residual value, which characterizes the overall deviation between the theoretically calculated temperature of the model and the actual physical input under steady-state conditions. The smaller the residual value, the higher the accuracy of the steady-state parameter fitting and the more closely the steady-state heat transfer characteristics of the model fit the actual conditions. It is the first-order thermal conductivity matrix, which is the core parameter to be solved for steady-state identification and characterizes the heat conduction capacity between each thermal network node. is a 2D node steady-state temperature vector, representing the true steady-state temperature of each partition obtained from finite element simulation / measurement. T is an N-dimensional global vector containing temperature information of all non-uniform partitions, used for global fitting of the steady-state matrix equation to identify the core parameters of the thermal network; This is an area-weighted average temperature scalar corresponding to a single sub-region, used only for quantization calculations of local temperature field reconstruction accuracy. The elements of vector T are related to each sub-region. One-to-one correspondence.

[0117] This is the acceptable threshold for steady-state fitting residuals, and the present invention uses a fixed value. When the global steady-state residual is less than this threshold, it is determined that the steady-state parameters such as thermal conductivity matrix and environmental compensation vector are converged, globally optimal, and physically effective.

[0118] S53. Parameter compatibility quantitative verification: Construct a steady-state-transient parameter compatibility index model to solve the problems of parameter mismatch and local optima.

[0119] The steady-state-transient parameter compatibility index model is as follows: .

[0120] In the formula, This refers to parameter compatibility error; The transient fitting heat capacity matrix; The steady-state equivalent heat capacity matrix; threshold A value less than 5% is considered as valid parameter compatibility, thus avoiding parameter drift and global mismatch issues.

[0121] S54. Iterative Correction of Electrothermal Coupling with Overload Saturation Compensation: Considering that the on-state voltage drop of IGBT chips has a positive temperature coefficient, i.e., the higher the temperature, the greater the on-state voltage drop under the same current, the actual power loss generated in each zone is not strictly proportional to the area, but also related to the zone temperature. To characterize this electrothermal coupling effect, this invention constructs an overload-compensated electrothermal coupling iterative power correction model, and performs iterative correction in parameter extraction and online application.

[0122] The overload compensation electrothermal coupling iterative power correction model is as follows.

[0123] .

[0124] .

[0125] In the formula, To iteratively correct the power loss in the partition, for the first... Partition number Power loss after subsequent iteration correction; This refers to the total area of ​​a single chip. This represents the real-time total power loss of the IGBT power device. This is the loss-temperature sensitivity coefficient, which physically represents the relative rate of change in power loss per unit temperature increase (relative to the average temperature of the entire chip). It is calibrated to a fixed value of 0.002 across the entire range. ; For the first Partition number Next iteration temperature; For the entire chip domain Average temperature over the next iteration; This represents the number of iteration steps. This is the temperature gradient saturation compensation factor. It is based on the real-time measured conduction current. and conduction voltage drop Calculate total power loss . Provides real-time on-state current for IGBT power devices; This refers to the real-time on-state voltage drop of IGBT power devices. Let be the area of ​​the i-th non-uniform sub-region.

[0126] The area-weighted average temperature of all finite element meshes within the corresponding non-uniform sub-partition is calculated and obtained according to the partition node temperature definition in step S31. The global average temperature, obtained by weighting the partition areas of all non-uniform partitions of a single chip, is calculated using the following formula: This belongs to the well-known calculation method for thermal network modeling.

[0127] The gradient saturation compensation factor piecewise adaptive model is as follows.

[0128] .

[0129] In the formula, It is the temperature gradient saturation compensation factor, a dimensionless adaptive correction coefficient used to suppress the problem of excessive correction of electrothermal iteration under large gradient overload conditions. This represents the chip's real-time maximum gradient magnitude. The reference gradient amplitude under rated operating conditions; 0.5 The critical threshold for low-gradient operating conditions; 1.2 The threshold value is 0.2, representing the critical threshold for ultra-large gradient overload. The coefficient 0.2 represents the linear decay ratio, and the constant value 0.88 represents the overload saturation locking coefficient. Mechanism Explanation: The piecewise adaptive model of the gradient saturation compensation factor is a constraint mechanism for the iterative divergence problem under large gradient overload conditions, used to adaptively suppress the overcorrection problem of electrothermal iteration under extreme conditions. Under normal low gradient conditions, the compensation factor is always 1.0, without interfering with normal iterative calculations. When the gradient is in the medium range, the compensation weight decreases linearly and gradually with the increase of the temperature gradient. When entering the ultra-large gradient overload range, the compensation factor is saturated and locked to 0.88, avoiding model overfitting and temperature prediction distortion caused by the infinite amplification of power correction. This completely solves the accuracy collapse defect of traditional electrothermal coupling iteration under extreme overload conditions, and is the core fallback quantization mechanism of this invention for achieving ultra-high prediction accuracy under high load conditions.

[0130] The segmented adaptive model of gradient saturation compensation factor is constructed. Its function is to use the real-time global temperature gradient of the chip as the driving basis to achieve full-condition adaptive correction with fidelity under normal operating conditions, smoothness under medium operating conditions, and anti-divergence under overload conditions. It is the core guarantee mechanism for achieving ultra-high prediction accuracy of 0.5K level under 750A+ overload conditions in this invention.

[0131] S55. Iterative dual convergence constraint: Construct a hotspot convergence criterion model, which is as follows.

[0132] .

[0133] In the formula, It is the highest global temperature value among all partition nodes of the IGBT chip after the k-th electrothermal coupling iteration, representing the extreme temperature of the chip hotspot in the current iteration step. This represents the highest node temperature across the entire chip region after the (k+1)th iteration correction, characterizing the hotspot extreme temperature after the iterative update. k is the iteration number of the electrothermal coupling iteration, an integer iteration counter variable. ε is a preset threshold, set to 0.1K in this embodiment. Convergence is typically achieved in 2-3 iterations. Under a 750A overload condition, the initial allocation differs from the predicted highest junction temperature after the first correction by 4.2K. After the second correction, the difference shrinks to 0.5K, and after the third correction, the change is less than 0.1K, indicating convergence. This correction strategy enables the model to accurately reflect the actual higher power loss density in high-temperature regions under large temperature gradients, thereby improving the accuracy of the highest junction temperature prediction.

[0134] This technical solution employs a two-step parameter identification strategy, combining steady-state and transient methods. It uses the least squares method to accurately fit the thermal conductivity matrix, thermal capacity matrix, and environmental compensation vector, along with a steady-state residual constraint criterion, ensuring globally optimal steady-state parameter fitting and controllable residuals. A steady-state-transient parameter compatibility quantification verification mechanism is introduced to control parameter matching errors within 5%, addressing the problems of local optima, parameter drift, and poor steady-state-transient adaptability in traditional parameter identification. Simultaneously, an overload electrothermal coupling iterative correction model with gradient saturation compensation is constructed, closely aligning with the physical characteristics of the positive temperature coefficient of IGBT on-state voltage drop. A piecewise adaptive compensation factor suppresses the defects of excessive iterative correction, model divergence, and accuracy collapse under large gradient overload conditions, ensuring fidelity under normal operating conditions and providing a fallback against failure under extreme conditions. With the dual convergence constraint mechanism of hot spot temperature, the prediction accuracy can be improved under high overload conditions. The iterative convergence speed is fast and the stability is strong. It solves the problems of unconstrained traditional electrothermal iteration, easy divergence, and accuracy failure under extreme conditions, and improves the robustness and prediction accuracy of the thermal network model under all operating conditions and multiple aging states.

[0135] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A method for modeling non-uniform partitioned thermal networks based on prior information of temperature gradient, characterized in that, Includes the following steps: Acquire prior temperature gradient information on the surface of the power device chip; collect real-time on-current and real-time on-voltage drop of the power device; based on the prior temperature gradient information, divide the surface of the power device chip into multiple non-uniform physical partitions. Each physical partition is defined as a thermal network node, and a non-uniform partition thermal network topology is constructed by combining the number of power device chips connected in parallel. Based on the aforementioned thermal network topology, an overload compensation electrothermal coupling iterative power correction model is constructed. The inputs to the overload compensation electrothermal coupling iterative power correction model are the real-time on-state current and real-time on-state voltage drop of the power device, and the result is the partitioned iterative correction of power loss. The temperature field data of the power device chip is iteratively solved based on the partitioned iterative correction of power loss, and the transient temperature distribution and maximum junction temperature of the power device chip are obtained based on the temperature field data.

2. The non-uniform partitioned thermal network modeling method based on temperature gradient prior information according to claim 1, characterized in that... In the calculation process of the partitioned iterative correction of power loss, a temperature gradient saturation compensation factor is configured, which is used to suppress the over-correction of electrothermal iteration under extreme operating conditions.

3. The non-uniform partitioned thermal network modeling method based on temperature gradient prior information according to claim 2, characterized in that... Based on the prior temperature gradient information, the continuous temperature field distribution of the power device chip is extracted. The maximum gradient amplitude of the power device chip is calculated based on the continuous temperature field distribution. The corresponding temperature gradient saturation compensation factor is calculated based on the maximum gradient amplitude.

4. The non-uniform partitioned thermal network modeling method based on temperature gradient prior information according to claim 3, characterized in that... The temperature gradient saturation compensation factor adopts a piecewise adaptive value selection mechanism, which matches the compensation weight under different operating conditions based on the relative relationship between the real-time maximum gradient amplitude of the power device chip and the rated operating condition reference gradient amplitude.

5. The non-uniform partitioned thermal network modeling method based on temperature gradient prior information according to claim 1, characterized in that... The overload compensation electrothermal coupling iterative power correction model is as follows: ； ； ； In the formula, Iterative correction of power loss for partitioning; This represents the total area of ​​the power device chip. This represents the real-time total power loss of the power device. This is the loss-temperature sensitivity coefficient; For the first Partition number Next iteration temperature; For the entire chip domain Average temperature over the next iteration; This represents the number of iteration steps. This is the temperature gradient saturation compensation factor. Provides real-time on-current for power devices; For real-time on-state voltage drop of power devices; Let i be the area of ​​the i-th non-uniform sub-region; This represents the real-time maximum gradient magnitude of the power device chip. This is the reference gradient amplitude under rated operating conditions.

6. The non-uniform partitioned thermal network modeling method based on temperature gradient prior information according to claim 3, characterized in that... Based on the continuous temperature field distribution of the power device chip, and using the maximum gradient amplitude as a benchmark, multiple temperature gradient threshold intervals are divided. The boundary thresholds of each temperature gradient threshold interval are generated by solving the Gaussian second derivative extreme value inflection point criterion. Using the isothermal contour line as the physical boundary, non-uniform physical partitions are generated for each temperature gradient threshold interval.

7. The non-uniform partitioned thermal network modeling method based on temperature gradient prior information according to claim 6, characterized in that... Based on the non-uniform physical partitioning of the temperature gradient threshold range, a hotspot refinement triggering rule is preset. When the gradient amplitude of a local area of ​​the power device chip is greater than 0.7 times the maximum gradient amplitude of the power device chip, it is determined to be a hotspot area and a secondary nested subdivision is initiated.

8. The method for modeling non-uniform partitioned thermal networks based on prior information of temperature gradient according to claim 1, characterized in that... Based on the aforementioned thermal network topology, a multi-chip lateral thermal coupling coefficient model is constructed. This model is used to quantify and evaluate the asymmetric thermal interference between the parallel power device chips. The multi-chip lateral thermal coupling coefficient model is as follows: ； In the formula, Let be the lateral thermal coupling coefficient between the p-th power device chip and the q-th power device chip; The reference coupled thermal conductivity constant; These represent the maximum gradient magnitudes of the p-th and q-th power device chips, respectively. This represents the maximum gradient extremum for all power device chips.

9. The method for modeling non-uniform partitioned thermal networks based on prior information of temperature gradient according to claim 1, characterized in that... Following the step of constructing the non-uniformly partitioned hot network topology, the process also includes a multi-objective quantization optimization step to solve for the optimal number of partitions, specifically including the following steps: Construct a multi-dimensional comprehensive performance evaluation criterion and establish a three-dimensional quantitative performance index system that includes hotspot extreme value prediction accuracy, global temperature field fitting similarity, and online model computational overhead. Perform dynamic weight configuration driven by temperature gradient; By eliminating pseudo-optimal solutions through multiple constraint checks, the number of globally optimal partitions is obtained, and an optimal hot network topology model is constructed based on the number of globally optimal partitions.

10. The method for modeling non-uniform partitioned thermal networks based on prior information of temperature gradient according to claim 9, characterized in that... In the dynamic weight configuration step driven by temperature gradient, based on the maximum gradient magnitude of the power device chip, the weight coefficients corresponding to the hotspot extreme value prediction accuracy, the global temperature field fitting similarity, and the model online computation overhead are calculated; the sum of the weight coefficients of the hotspot extreme value prediction accuracy, the global temperature field fitting similarity, and the model online computation overhead is 1.

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