Bitcell and integrated circuit device including the same

Abstract

A bitcell including a read port and a write port, the bitcell comprising: a plurality of active regions spaced apart parallel to each other in a first direction and extending in a second direction perpendicular to the first direction; and a plurality of gates spaced apart parallel to each other in the second direction, extending in the first direction, and arranged in at least one of the active regions to each form a transistor. The read port includes a read pass transistor and a read pull-down transistor. The write port includes a first pass transistor, a second pass transistor, a first pull-down transistor, a second pull-down transistor, a first pull-up transistor, and a second pull-up transistor. The read pass transistor, the read pull-down transistor, the first pass transistor, and the first pull-down transistor share one active region.

Description

Technical Field

[0001] The present invention relates to bit cells and integrated circuit devices including the same, and more specifically, to dual-port static random access memory (SRAM) cells and integrated circuit devices including the same. Background Technology

[0002] Driven by strong demand from semiconductor users and the continued efforts of semiconductor manufacturers, technologies related to semiconductor devices are experiencing significant growth and sustained development globally. Furthermore, semiconductor manufacturers are striving to make semiconductor devices smaller, more integrated, and larger, while simultaneously promoting research and development to achieve more stable, smoother operation and faster speeds. These efforts have led to advancements in fine process technology, ultra-small component technology, and circuit design technology, which have already yielded significant results in semiconductor memory cell technologies such as Dynamic Random Access Memory (DRAM) and SRAM.

[0003] In the case of dual-port SRAM, high-speed read and write operations can be performed compared to conventional single-port SRAM. However, in the case of dual-port SRAM, the area of ​​a single memory cell can increase as the number of transistors included in a single memory cell increases compared to conventional single-port SRAM. Summary of the Invention

[0004] The present invention provides a bit cell with excellent operating characteristics and improved integration, as well as an integrated circuit device including the bit cell.

[0005] The inventive concept is not limited to those mentioned above, and those skilled in the art will clearly understand from the following description other inventive concepts not mentioned.

[0006] According to one aspect of the present invention, a bit cell including a read port and a write port is provided. The bit cell includes: a plurality of active regions spaced parallel to each other in a first direction and extending in a second direction perpendicular to the first direction; and a plurality of gates spaced parallel to each other in the second direction, extending in the first direction, and disposed in at least one of the plurality of active regions to each form a transistor. The read port includes a read transfer transistor and a read pull-down transistor, and the write port includes a first transfer transistor, a second transfer transistor, a first pull-down transistor, a second pull-down transistor, a first pull-up transistor, and a second pull-up transistor, wherein the read transfer transistor, the read pull-down transistor, the first transfer transistor, and the first pull-down transistor share a single active region.

[0007] According to another aspect of the present invention, a bit cell including a read port and a write port is provided. The read port includes a read transfer transistor and a read pull-down transistor, and the write port includes a first transfer transistor, a second transfer transistor, a first pull-down transistor, a second pull-down transistor, a first pull-up transistor, and a second pull-up transistor, wherein the read transfer transistor, the read pull-down transistor, the first transfer transistor, and the first pull-down transistor share an active region.

[0008] According to another aspect of the present invention, an integrated circuit device is provided, the integrated circuit device including a bit cell, the bit cell including a read port and a write port, wherein the bit cell includes: a plurality of active regions, the plurality of active regions including a first active region, a second active region, a third active region and a fourth active region, the first active region, the second active region, the third active region and the fourth active region being spaced parallel to each other in a first direction and extending in a second direction perpendicular to the first direction; and a plurality of gates, the plurality of gates including a first gate, a second gate, a third gate and a fourth gate, the first gate, the second gate, the third gate and the fourth gate being spaced parallel to each other in the second direction, extending in the first direction, and arranged in at least one of the plurality of active regions to each form a transistor, wherein the read port includes a read transfer transistor and a read pull-down transistor, the write port includes a first transfer transistor, a second transfer transistor, a first pull-down transistor, a second pull-down transistor, a first pull-up transistor and a second pull-up transistor, and the read transfer transistor, the read pull-down transistor, the first transfer transistor and the first pull-down transistor share an active region. Attached Figure Description

[0009] The various embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a block diagram of an integrated circuit device according to an embodiment; Figure 2 These are circuit diagrams of bit cells according to some embodiments; Figures 3 to 6 This is a layout diagram of bit cells according to some embodiments; Figure 7 These are cross-sectional views of an integrated circuit device according to some embodiments; and Figures 8 to 12 It is according to the embodiment along Figure 6 The image shows a cross-sectional view of a portion of an integrated circuit device taken by line Y1-Y1' to illustrate a method for manufacturing integrated circuit devices according to process sequence. Detailed Implementation

[0010] The embodiments are described in detail below with reference to the accompanying drawings. The same reference numerals are used for the same elements in the drawings, and repeated descriptions are omitted.

[0011] Figure 1 This is a block diagram of an integrated circuit device 10 according to an embodiment.

[0012] refer to Figure 1 The integrated circuit device 10 can receive commands CMD, address ADDR, clock CLK, and write data DATA_IN. For example, the integrated circuit device 10 can receive commands CMD (which may be referred to as write commands), address ADDR (which may be referred to as write addresses), and write data DATA_IN, and can store the write data DATA_IN in the area corresponding to address ADDR in the memory cell block 11. Furthermore, the integrated circuit device 10 can receive commands CMD (which may be referred to as read commands) and address ADDR (which may be referred to as read addresses), and can output the read data DATA_OUT stored in the area corresponding to address ADDR in the memory cell block 11 to the outside.

[0013] The storage cell block 11 may include a plurality of bit cells 12. The plurality of bit cells 12 may be spaced apart from each other at regular intervals. The plurality of bit cells 12 may be arranged at the intersection of word line WL and bit line BL. That is, each bit cell in the plurality of bit cells 12 may be connected to at least one word line WL and may be connected to at least one bit line BL.

[0014] Each of the plurality of bit cells 12 may include a memory cell. For example, each of the plurality of bit cells 12 may include static random access memory (SRAM), or may include volatile memory cells, such as dynamic random access memory (DRAM). In particular, each of the plurality of bit cells 12 may include a dual-port SRAM (TPSRAM) cell with separate write and read ports. In some embodiments, the plurality of bit cells 12 may include non-volatile memory cells, such as flash memory or resistive random access memory (RRAM). Embodiments are described primarily with reference to TPSRAM cells, but the inventive concept is not limited thereto.

[0015] Column driver 13 can be connected to memory cell block 11 via bit line BL. Column driver 13 can select at least one bit line BL based on column address COL. For example, column driver 13 can select the first bit line (e.g., ...). Figure 2 The first write bit line (WBL) and the second bit line (e.g., Figure 2The second write bit line (WBLB) is complementary to the first write bit line. The first and second bit lines can be connected to any one of the multiple bit cells 12. As the column driver 13 selects the first and second write bit lines, the multiple bit cells 12 connected to either the first or second write bit line can be selected.

[0016] Column driver 13 can perform read or write operations based on control signal CTR. Column driver 13 can detect current and / or voltage received through bit line BL to determine the value stored in the bit cell connected to the active word line among the plurality of bit cells 12, and output read data DATA_OUT based on the determined value. Column driver 13 can apply current and / or voltage to bit line BL based on write data DATA_IN, and can write the value to the bit cell connected to the active word line among the plurality of bit cells 12. According to an embodiment, column driver 13 may include read circuitry for performing read operations and write circuitry for performing write operations. Although not shown, column driver 13 may include bit line precharge circuitry for precharging bit line BL.

[0017] Row driver 14 can be connected to memory cell block 11 via word line WL. Row driver 14 can activate at least one word line WL based on row address ROW. That is, row driver 14 can select at least one word line WL based on row address ROW. Therefore, bit cells connected to the activated word line can be selected from a plurality of bit cells 12.

[0018] Control block 15 can receive commands CMD, address ADDR, and clock CLK, and can generate row address ROW, column address COL, and control signal CTR. For example, control block 15 can determine a read command by decoding command CMD, and can generate row address ROW, column address COL, and control signal CTR to read data DATA_OUT from memory cell block 11. Furthermore, control block 15 can determine a write command by decoding command CMD, and can generate row address ROW, column address COL, and control signal CTR to write write data DATA_IN to memory cell block 11.

[0019] Figure 2 This is a circuit diagram of a bit cell according to an embodiment.

[0020] refer to Figure 2 The bit unit BC may include a first transmission transistor PG1, a second transmission transistor PG2, a read transmission transistor RPG, a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, a second pull-down transistor PD2, and a read pull-down transistor RPD.

[0021] In some embodiments, the bit cell BC may include a TPSRAM cell. The bit cell BC includes a write port WP and a read port RP, wherein the write port WP can operate in parallel with the read port RP. The write port WP may include a first transfer transistor PG1, a second transfer transistor PG2, a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, and a second pull-down transistor PD2. The first pull-up transistor PU1 and the second pull-up transistor PU2 may include P-type transistors, and the first transfer transistor PG1, the second transfer transistor PG2, the first pull-down transistor PD1, and the second pull-down transistor PD2 may include N-type transistors. For example, the first pull-up transistor PU1 and the second pull-up transistor PU2 may include a P-channel metal-oxide-semiconductor field-effect transistor (MOSFET) (PFET), and the first transfer transistor PG1, the second transfer transistor PG2, the first pull-down transistor PD1, and the second pull-down transistor PD2 may include an N-channel MOSFET (NFET).

[0022] In some embodiments, the first pull-up transistor PU1 and the first pull-down transistor PD1 can form a first inverter, and the second pull-up transistor PU2 and the second pull-down transistor PD2 can form a second inverter.

[0023] Specifically, the drain of the first pull-up transistor PU1 can be connected to the drain of the first pull-down transistor PD1, and the gate of the first pull-up transistor PU1 can be electrically connected to the gate of the first pull-down transistor PD1. A power supply voltage VDD can be applied to the source of the first pull-up transistor PU1, and a ground voltage VSS can be applied to the source of the first pull-down transistor PD1. Therefore, the first pull-up transistor PU1 and the first pull-down transistor PD1 can constitute a first inverter.

[0024] Similarly, the drain of the second pull-up transistor PU2 can be connected to the drain of the second pull-down transistor PD2, and the gate of the second pull-up transistor PU2 can be electrically connected to the gate of the second pull-down transistor PD2. The power supply voltage VDD can be applied to the source of the second pull-up transistor PU2, and the ground voltage VSS can be applied to the source of the second pull-down transistor PD2. Therefore, the second pull-up transistor PU2 and the second pull-down transistor PD2 can constitute a second inverter.

[0025] In some embodiments, the first transfer transistor PG1 and the second transfer transistor PG2 can control access to a memory cell (e.g., a bit cell BC) including the first inverter and the second inverter during read and write operations.

[0026] The gates of the first pull-up transistor PU1 and the first pull-down transistor PD1, which are connected to each other, can correspond to the input terminal of the first inverter, and the first node N1, which is connected to the drain terminal of the first pull-up transistor PU1 and the drain terminal of the first pull-down transistor PD1, can correspond to the output terminal of the first inverter.

[0027] The gates of the second pull-up transistor PU2 and the second pull-down transistor PD2, which are connected to each other, can correspond to the input terminal of the second inverter, and the second node N2, which is connected to the drain terminal of the second pull-up transistor PU2 and the drain terminal of the second pull-down transistor PD2, can correspond to the output terminal of the second inverter.

[0028] The first inverter and the second inverter can be coupled to each other in a latching structure. That is, the gates of the first pull-up transistor PU1 and the first pull-down transistor PD1 can be connected to the second node N2, and the gates of the second pull-up transistor PU2 and the second pull-down transistor PD2 can be connected to the first node N1. The first node N1 and the second node N2 can refer to complementary nodes at opposite logic levels (logic high or logic low).

[0029] The first node N1 can be connected to the first write bit line WBL of the write port WP via the first transfer transistor PG1, and the second node N2 can be connected to the second write bit line WBLB of the write port WP via the second transfer transistor PG2. The second write bit line WBLB can refer to a bit line complementary to the first write bit line WBL. For example, the drain terminal of the first transfer transistor PG1 can be connected to the first node N1. The source terminal of the first transfer transistor PG1 can be connected to the first write bit line WBL. The drain terminal of the second transfer transistor PG2 can be connected to the second node N2. The source terminal of the second transfer transistor PG2 can be connected to the second write bit line WBLB. The gates of the first transfer transistor PG1 and the second transfer transistor PG2 can be connected to the write word line WWL of the write port WP.

[0030] In some embodiments, the read port RP of bit cell BC may include a read transfer transistor RPG and a read pull-down transistor RPD. The gate of the read transfer transistor RPG may be connected to the read word line RWL of the read port RP. The gate of the read pull-down transistor RPD may be connected to the second node N2. The read transfer transistor RPG and the read pull-down transistor RPD may be connected between the read bit line RBL of the read port RP and the ground voltage RVSS. For example, the drain terminal of the read transfer transistor RPG may be connected to the read bit line RBL of the read port RP, and the ground voltage RVSS may be applied to the source terminal of the read pull-down transistor RPD.

[0031] Figures 3 to 6This is a layout diagram of bit cells according to an embodiment.

[0032] Specifically, Figure 3 This is a layout diagram of bit cell BC according to some embodiments, which schematically shows only a plurality of gates 160 and first to fourth active regions AP1, AP2, AP3 and AP4. Figure 4 This involves adding multiple source / drain contacts CA and multiple gate contacts CB. Figure 3 The layout diagram of bit cell BC in the layout diagram. Figure 5 It is to add the first wiring layer M1 to Figure 4 The layout diagram of bit cell BC in the layout diagram. Figure 6 It is to add the second wiring layer M2 to Figure 5 The layout diagram of bit cell BC in the layout diagram.

[0033] refer to Figure 3 and Figure 6 A bit cell BC may include a TPSRAM cell having a write port WP and a read port RP. The bit cell BC may include first to fourth active regions AP1, AP2, AP3, and AP4 that are spaced parallel to each other in a first direction (X direction) and extend in a second direction (Y direction) perpendicular to the first direction (X direction). In this inventive concept, a bit cell BC may include four active regions, for example, a first active region AP1, a second active region AP2, a third active region AP3, and a fourth active region AP4.

[0034] In some embodiments, each of the first active region AP1, the second active region AP2, the third active region AP3, and the fourth active region AP4 may include a P-type active pattern forming an N-type transistor or an N-type active pattern forming a P-type transistor. For example, the first active region AP1 and the fourth active region AP4 may include P-type active patterns, and the second active region AP2 and the third active region AP3 may include N-type active patterns.

[0035] The first active region AP1, the second active region AP2, the third active region AP3, and the fourth active region AP4 may have different widths in the first direction (X direction). For example, the widths of the first active region AP1 and the fourth active region AP4 in the first direction (X direction) may be greater than the widths of the second active region AP2 and the third active region AP3 in the first direction (X direction), but the inventive concept is not limited thereto.

[0036] Multiple transistors can be formed in a first active region AP1, a second active region AP2, a third active region AP3, and a fourth active region AP4. These multiple transistors can include, but are not limited to: a fin field-effect FET (FinFET) formed by a gate electrode and an active pattern extending in a fin shape; a gate-all-around FET (GAAFET) formed by a gate electrode and multiple nanowires extending parallel to each other; or a multi-bridge channel FET (MBCFET) formed by a gate electrode and multiple nanosheets extending parallel to each other.

[0037] In some embodiments, the bit cell BC may include a plurality of gates 160 spaced parallel to each other in a second direction (Y direction) and extending in a first direction (X direction). The plurality of gates 160 may partially overlap with one or more active regions AP1, AP2, AP3, and AP4. The plurality of gates 160 may include structures corresponding to the gate terminals of transistors formed in the first to fourth active regions AP1, AP2, AP3, and AP4. That is, the plurality of gates 160 and the first to fourth active regions AP1, AP2, AP3, and AP4 may form transistors.

[0038] In some embodiments, a first gate 161, a second gate 162, a third gate 163, and a fourth gate 164 may be formed on a first active region AP1. The first gate 161, second gate 162, third gate 163, and fourth gate 164 may be spaced parallel to each other on the first active region AP1 along a second direction (Y direction) and may extend along a first direction (X direction). Some gates (e.g., the third gate 163) may include partially discontinuous portions.

[0039] In some embodiments, the first active region AP1 and the first gate 161 can form a read transfer transistor RPG. The first active region AP1 and the second gate 162 can form a read pull-down transistor RPD. The first active region AP1 and the third gate 163 can form a first pull-down transistor PD1. The first active region AP1 and the fourth gate 164 can form a first transfer transistor PG1.

[0040] In some embodiments, a portion of the first active area AP1 may be located in the read port RP, and a portion of the first active area AP1 may be located in the write port WP. That is, the first active area AP1 may be shared by the read port RP and the write port WP.

[0041] The read port RP and the write port WP can share the first active region AP1, allowing the read transfer transistor RPG, the read pull-down transistor RPD, the first transfer transistor PG1, and the first pull-down transistor PD1 to share the first active region AP1. Since the first active region AP1 is a P-type active pattern, the read transfer transistor RPG, the read pull-down transistor RPD, the first transfer transistor PG1, and the first pull-down transistor PD1 can all include N-type transistors.

[0042] In the write port WP, the second active region AP2, the third active region AP3, and the fourth active region AP4 can be spaced parallel to each other in a first direction (X direction) and can extend in a second direction (Y direction). A third gate 163 can be disposed on the second active region AP2, and the third gate 163 and the second active region AP2 can form a first pull-up transistor PU1. A second gate 162 can be disposed on the third active region AP3, and the second gate 162 and the third active region AP3 can form a second pull-up transistor PU2. A second gate 162 can be disposed on the fourth active region AP4, and the second gate 162 and the fourth active region AP4 can form a second pull-down transistor PD2. A third gate 163 can be disposed on the fourth active region AP4, and the third gate 163 and the fourth active region AP4 can form a second transfer transistor PG2.

[0043] In some embodiments, the bit cell BC of this invention may include four active regions (i.e., first, second, third, and fourth active regions AP1, AP2, AP3, and AP4) and four gates (i.e., first, second, third, and fourth gates 161, 162, 163, and 164). The read transfer transistor RPG and read pull-down transistor RPD of the read port RP and the first transfer transistor PG1 and first pull-down transistor PD1 of the write port WP may share the first active region AP1. Therefore, compared to a comparative example where the read transfer transistor RPG and read pull-down transistor RPD of the read port RP and the first transfer transistor PG1 and first pull-down transistor PD1 of the write port WP are arranged on different active regions, the area of ​​the bit cell BC can be reduced. For example, compared to a comparative example including five active regions and two gates, the area of ​​the bit cell BC can be reduced by about 10%.

[0044] Furthermore, since the read transfer transistor RPG, the read pull-down transistor RPD, the first transfer transistor PG1, and the first pull-down transistor PD1 share the first active region AP1, the pattern loading effect generated during the process can also be reduced. The pattern loading effect refers to the phenomenon of non-uniform pattern density and size formation during etching and deposition processes. Therefore, the electrical performance of the bit cell BC of the present invention can be improved.

[0045] refer to Figure 4 and Figure 5 A voltage can be applied to multiple gates 160 through multiple gate contacts CB. The multiple gates 160 may include a conductive material. For example, the multiple gates 160 may include at least one of a semiconductor material (e.g., doped silicon (Si), doped germanium (Ge), or doped silicon-germanium (SeGe)), a metal (e.g., tungsten (W) or aluminum (Al)), a metal compound (e.g., a metal silicide), a conductive metal nitride (e.g., titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN)), or a transition metal (e.g., titanium (Ti) or tantalum (Ta)).

[0046] Multiple source / drain contacts CA can be formed on the first to fourth active regions AP1, AP2, AP3, and AP4. The multiple source / drain contacts CA can extend in a first direction (X direction). The multiple source / drain contacts CA can provide voltage to the source and drain regions of the transistor.

[0047] Multiple gate contacts CB and multiple source / drain contacts CA can be electrically connected to the first wiring layer M1. The first wiring layer M1 can be spaced apart from multiple gates 160 and the first to fourth active regions AP1, AP2, AP3, and AP4 in the vertical direction (Z direction). The multiple gate contacts CB can electrically connect the multiple gates 160 to the first wiring layer M1, and the multiple source / drain contacts CA can electrically connect the first to fourth active regions AP1, AP2, AP3, and AP4 to the first wiring layer M1. The sum of the heights of the gates 160 and the gate contacts CB can be equal to the height of the source / drain contacts CA, but the inventive concept is not limited thereto.

[0048] The first routing layers M1 may be spaced parallel to each other in a first direction (X direction) and may extend in a second direction (Y direction). The first routing layer M1 may include multiple metal lines. For example, the first routing layer M1 may include a read ground voltage line RVSS, a write ground voltage line VSS, a read word line RWL, a write word line WWL, a write power supply voltage line VDD, a read bit line pad RBL_P, and a first write bit line pad WBL_P and a second write bit line pad WBLB_P.

[0049] In some embodiments, the read ground voltage line RVSS can be connected to the source terminal of the read pull-down transistor RPD of the read port RP via the source / drain contact CA. The write ground voltage line VSS can be connected to the source terminals of the first pull-down transistor PD1 and the second pull-down transistor PD2 of the write port WP via the source / drain contact CA. The write power supply voltage line VDD can be connected to the source terminals of the first pull-up transistor PU1 and the second pull-up transistor PU2 of the write port WP via the source / drain contact CA. The read bit line pad RBL_P can be connected to the drain terminal of the read transfer transistor RPG of the read port RP via the source / drain contact CA. The first write bit line pad WBL_P and the second write bit line pad WBLB_P can be connected to the source terminals of the first transfer transistor PG1 and the second transfer transistor PG2, respectively, via the source / drain contact CA.

[0050] In some embodiments, the read word line RWL can be connected via gate contact CB to the gate of the read transfer transistor RPG of the read port RP (e.g., first gate 161). The write word line WWL can be connected via gate contact CB to the gate of the first transfer transistor PG1 and the second transfer transistor PG2 of the write port WP (e.g., fourth gate 164 and third gate 163).

[0051] In some embodiments, the read word line RWL and the write word line WWL may extend in a second direction (Y direction). That is, the read word line RWL and the write word line WWL may extend in a direction parallel to the first to fourth active regions AP1, AP2, AP3 and AP4 and perpendicular to the plurality of gates 160.

[0052] In some embodiments, the lengths of the read bit line pad RBL_P, the first write bit line pad WBL_P, and the second write bit line pad WBLB_P in the second direction (Y direction) may be less than the lengths of other metal lines in the first wiring layer M1. For example, the lengths of the read bit line pad RBL_P, the first write bit line pad WBL_P, and the second write bit line pad WBLB_P in the second direction (Y direction) may be less than the lengths of the read word line RWL and the write word line WWL.

[0053] refer to Figure 6A second wiring layer M2 can be disposed on the first wiring layer M1. That is, the vertical height of the second wiring layer M2 can be greater than the vertical height of the first wiring layer M1. The second wiring layers M2 can be spaced parallel to each other in the second direction (Y direction) and can extend in the first direction (X direction). The first wiring layer M1 can be electrically connected to the second wiring layer M2 through a connection path V1. That is, the first wiring layer M1 and the second wiring layer M2 can be spaced apart from each other in the vertical direction (Z direction), and the connection path V1 is located between the first wiring layer M1 and the second wiring layer M2.

[0054] In some embodiments, the second routing layer M2 may include multiple metal lines. For example, the second routing layer M2 may include a read bit line RBL, a first write bit line WBL, and a second write bit line WBLB. The second write bit line WBLB may refer to a bit line complementary to the first write bit line WBL. The read bit line RBL is electrically connected to the read bit line pad RBL_P via a connection path V1. The first write bit line WBL is electrically connected to the first write bit line pad WBL_P via a connection path V1. The second write bit line WBLB is electrically connected to the second write bit line pad WBLB_P via a connection path V1.

[0055] In some embodiments, the read bit line RBL, the first write bit line WBL, and the second write bit line WBLB can extend in a first direction (X direction). That is, the read bit line RBL, the first write bit line WBL, and the second write bit line WBLB can extend in a direction parallel to the plurality of gates 160 and perpendicular to the first to fourth active regions AP1, AP2, AP3, and AP4.

[0056] In some embodiments, the thickness of the read bit line RBL, the first write bit line WBL, and the second write bit line WBLB in the second direction (Y direction) may be greater than the thickness of other metal lines in the first wiring layer M1. For example, the thickness of the read bit line RBL, the first write bit line WBL, and the second write bit line WBLB in the second direction (Y direction) may be greater than the thickness of the read word line RWL and the write word line WWL in the first direction (X direction).

[0057] In some embodiments, since the second wiring layer M2 located on the first wiring layer M1 includes a read bit line RBL, a first write bit line WBL, and a second write bit line WBLB, the read bit line RBL, the first write bit line WBL, and the second write bit line WBLB can be designed to be thicker. As the thickness of the read bit line RBL, the first write bit line WBL, and the second write bit line WBLB increases in the second direction (Y direction), the bit line capacitance can be reduced. Therefore, the electrical performance of the bit cell BC of the present invention can be improved.

[0058] Figure 7This is a cross-sectional view of an integrated circuit device 100 according to some embodiments. Specifically, Figure 7 It is along Figure 6 The cross-sectional view taken from line Y1-Y1' in the diagram.

[0059] refer to Figure 7 The integrated circuit device 100 may include a finned active region FA protruding from a substrate 102 and extending in a second direction (Y direction). The substrate 102 may include a conductive region, such as a doped well or a doped structure. The finned active region FA can be coupled with… Figure 6 This corresponds to the first active region AP1 in the middle.

[0060] Multiple nanosheet stacks of NSS can be disposed on the front surface FF of the finned active region FA. Each NSS stack can include at least one nanosheet. As used herein, the term "nanosheet" refers to a conductive structure having a cross-section substantially perpendicular to the direction of current flow. It should be understood that nanosheets include nanowires.

[0061] Although a structure comprising a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3 has been shown herein, the number of nanosheets included in each nanosheet stack of a multi-nanosheet NSS can be varied in various ways. For example, each multi-nanosheet NSS may include at least one or at least two nanosheets, and the number of nanosheets constituting the multi-nanosheet NSS is not particularly limited. The first to third nanosheets N1, N2, and N3 may all have channel regions. In some embodiments, the first to third nanosheets N1, N2, and N3 included in the multi-nanosheet NSS may all include a Si layer, a SiGe layer, or a combination thereof.

[0062] In some embodiments, the first to third nanosheets N1, N2, and N3 may each have a vertical thickness selected from the range of about 4 nm to about 6 nm. In some embodiments, the first to third nanosheets N1, N2, and N3 may have substantially the same thickness. The first to third nanosheets N1, N2, and N3 may comprise the same material.

[0063] The integrated circuit device 100 may include a plurality of source / drain regions 130A. Each of the plurality of source / drain regions 130A may be disposed on both sides of each nanosheet stack in a second direction (Y direction) in a plurality of nanosheet stacks NSS, adjacent to the plurality of nanosheet stacks NSS. The plurality of source / drain regions 130A disposed on a finned active region FA may be spaced apart from each other in the second direction (Y direction). Each of the plurality of source / drain regions 130A may contact the first to third nanosheets N1, N2, and N3 included in adjacent nanosheet stacks NSS. Hereinafter, each of the plurality of source / drain regions 130A may be referred to as an N-type semiconductor region.

[0064] In some embodiments, the plurality of source / drain regions 130A may each be composed of a Si layer doped with an N-type dopant or a silicon carbide (SiC) layer doped with an N-type dopant. The N-type dopant may be selected from phosphorus (P), arsenic (As), and antimony (Sb).

[0065] The integrated circuit device 100 may include a plurality of gates 160. Each of the plurality of gates 160 may cover the finned active region FA. The plurality of gates 160 may have a reference [feature / feature]. Figures 3 to 6 The described multiple gates 160 have substantially the same structure. The multiple gates 160 may be spaced apart from each other in a second direction (Y direction) and extend longitudinally in a first direction (X direction). The multiple gates 160 may be wrapped in first to third nanosheets N1, N2 and N3 included in a nanosheet stack NSS that overlaps with the multiple gates 160 in the vertical direction (Z direction).

[0066] Each of the plurality of gates 160 may comprise a metal, a metal nitride, a metal carbide, or a combination thereof. The metal may be selected from Ti, W, ruthenium (Ru), niobium (Nb), molybdenum (Mo), hafnium (Hf), nickel (Ni), cobalt (Co), platinum (Pt), ytterbium (Yb), terbium (Tb), dysprosium (Dy), erbium (Er), and palladium (Pd). The metal nitride may be selected from TiN and TaN. The metal carbide may be TiAlC. However, the materials constituting the plurality of gates 160 are not limited to the above.

[0067] Each of the multiple gates 160 may include a main gate portion 160M and multiple sub-gate portions 160S. The main gate portion 160M covers the top surface of the nanosheet stack NSS and extends in a first direction (X direction). The multiple sub-gate portions 160S are integrally connected to the main gate portion 160M and are arranged in the space between each of the first to third nanosheets N1, N2, and N3 and in the space between the front surface FF and the first nanosheet N1. In the vertical direction (Z direction), the thickness of each of the multiple sub-gate portions 160S may be less than the thickness of the main gate portion 160M. Among the first to third nanosheets N1, N2, and N3, the second nanosheet N2 and the third nanosheet N3, other than the first nanosheet N1, may have a gate-all-around (GAA) structure completely surrounded by the gates 160.

[0068] A gate dielectric film 152 may be disposed between the nanosheet stack NSS and the gate 160. The gate dielectric film 152 may be a stacked structure of an interface dielectric film and a high-k film. The interface dielectric film may include a low-k material film having a dielectric constant of about 9 or less, such as a silicon oxide film, a silicon oxynitride film, or a combination thereof. In some embodiments, the interface dielectric film may be omitted. The high-k film may include a material with a dielectric constant greater than that of the silicon oxide film. For example, the high-k film may have a dielectric constant of about 10 to about 25. The high-k film may include, but is not limited to, hafnium oxide.

[0069] Two sidewalls of each of the plurality of sub-gate portions 160S included in the plurality of gates 160 may be spaced apart from the source / drain region 130A, and a gate dielectric film 152 is located between the two sidewalls and the source / drain region 130A. The gate dielectric film 152 may be disposed between the sub-gate portions 160S included in the gate 160 and each of the first to third nanosheets N1, N2 and N3, and between the sub-gate portions 160S included in the gate 160 and the source / drain region 130A. The plurality of gates 160, the plurality of nanosheet stacks NSS and the source / drain region 130A may constitute a plurality of nanosheet transistors.

[0070] The two sidewalls of the gate 160 may be covered with a plurality of insulating spacers 118. Each of the plurality of insulating spacers 118 may cover the sidewalls of the main gate portion 160M located above the top surface of the nanosheet stack NSS. Each of the plurality of insulating spacers 118 may be spaced apart from the gate 160, and a gate dielectric film 152 is located between each insulating spacer and the gate 160. The plurality of insulating spacers 118 may be composed of silicon nitride, silicon oxide, SiOC, SiOCN, SiCN, SiBN, SiON, SiBCN, SiOF, SiOCH, or combinations thereof. The plurality of insulating spacers 118 may comprise a monolayer film (comprising a material film selected from the materials listed above) or may comprise a multilayer film (comprising multiple material films selected from the materials listed above).

[0071] The top surface of each of the gate 160, the gate dielectric film 152, and the insulating spacer 118 may be covered with a cover insulating pattern 168. The cover insulating pattern 168 may include a silicon nitride film.

[0072] Multiple source / drain regions 130A and multiple insulating spacers 118 may be covered by an insulating pad 142. An inter-gate insulating film 144 may be disposed on the insulating pad 142. The inter-gate insulating film 144 may fill the space between pairs of gates 160 adjacent to each other in the second direction (Y direction). In some embodiments, the insulating pad 142 may comprise silicon nitride, SiCN, SiBN, SiON, SiOCN, SiBCN or combinations thereof, and the inter-gate insulating film 144 may comprise a silicon oxide film, but is not limited thereto.

[0073] Multiple source / drain contacts CA can be disposed above multiple source / drain regions 130A. Each of the multiple source / drain contacts CA can be configured to be electrically connected to at least one of the multiple source / drain regions 130A. A metal silicide film 172 can be disposed between the source / drain region 130A and the source / drain contact CA. The metal silicide film 172 can contact the corresponding source / drain region 130A. The source / drain contact CA can pass through the inter-gate insulating film 144 and the insulating pad 142 in the vertical direction (Z direction) to contact the metal silicide film 172. The source / drain contact CA can be configured to be connected to the source / drain region 130A through the metal silicide film 172. The source / drain contact CA can pass through a portion of the source / drain region 130A in the vertical direction (Z direction). The insulating pad 142 and the inter-gate insulating film 144 may surround the sidewalls of the source / drain contact CA.

[0074] In some embodiments, the metal silicide film 172 may include Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd. For example, the metal silicide film 172 may include titanium silicide. In some embodiments, the source / drain contact CA may consist only of a metal plug composed of a single metal. In some embodiments, the source / drain contact CA may include a metal plug and a conductive barrier film surrounding the metal plug. The conductive barrier film may include a metal or a conductive metal nitride.

[0075] The top surface of each of the source / drain contacts CA, the plurality of overlay insulating patterns 168, and the inter-gate insulating film 144 may be covered with an upper insulating structure 180. The upper insulating structure 180 may include an etch stop film 182 and an upper insulating film 184 sequentially stacked on each of the plurality of source / drain contacts CA, the plurality of overlay insulating patterns 168, and the inter-gate insulating film 144. The etch stop film 182 may include SiC, SiN, SiCN, SiOC, AlN, AlON, AlO, AlOC, or combinations thereof. The upper insulating film 184 may include an oxide film, a nitride film, an ultra-low k (ULK) film having an ultra-low dielectric constant of about 2.2 to about 2.4, or combinations thereof.

[0076] The source / drain path contact VA can be located on the source / drain contact CA. The source / drain path contact VA can pass through the upper insulation structure 180 and can make contact with the source / drain contact CA.

[0077] The first wiring layer M1 can be disposed on the upper insulating structure 180. Interlayer insulating films 188 can be arranged between the first wiring layers M1 in a first direction (X direction). The first wiring layer M1 can be connected to the source / drain contact CA and the gate contact CB via source / drain path contacts VA and gate path contacts. For example... Figure 6 As shown, the first wiring layer M1 may include a read ground voltage line RVSS, a write ground voltage line VSS, a read word line RWL, a write word line WWL, a write power supply voltage line VDD, a read bit line pad RBL_P, and a first write bit line pad WBL_P and a second write bit line pad WBLB_P. Multiple gate contacts CB can electrically connect multiple gates 160 to the first wiring layer M1, and multiple source / drain contacts CA can electrically connect the first to fourth active regions AP1, AP2, AP3, and AP4 to multiple first wiring layers M1.

[0078] The second wiring layer M2 can be disposed on the first wiring layer M1. The second wiring layer M2 may include multiple bit lines. The interlayer insulating film 188 may cover the second wiring layer M2.

[0079] The first wiring layer M1 and the second wiring layer M2 may include, but are not limited to, Mo, copper (Cu), W, Co, Ru, manganese (Mn), Ti, Ta, Al, combinations thereof, or alloys thereof. The constituent materials of the interlayer insulating film 188 are substantially the same as those of the upper insulating film 184 described above.

[0080] Let's refer to each other. Figure 6 The source / drain region 130A constituting the read transfer transistor RPG can be connected to the read bit line RBL via the source / drain contact CA and the read bit line pad RBL_P, and the source / drain region 130A constituting the read pull-down transistor RPD can be connected to the read ground voltage line RVSS via the source / drain contact CA. Furthermore, the source / drain region 130A constituting the first pull-down transistor PD1 can be connected to the write ground voltage line VSS of the write port via the source / drain contact CA, and the source / drain region 130A constituting the first transfer transistor PG1 can be connected to the first write bit line WBL via the source / drain contact CA and the first write bit line pad WBL_P.

[0081] In some embodiments, the integrated circuit device 100 may form the read transfer transistor RPG and read pull-down transistor RPD of the read port RP, and the first transfer transistor PG1 and first pull-down transistor PD1 of the write port WP on a finned active region FA. Therefore, compared to a comparative example where the read transfer transistor RPG and read pull-down transistor RPD of the read port RP and the first transfer transistor PG1 and first pull-down transistor PD1 of the write port WP are arranged on different active regions, the area of ​​the integrated circuit device 100 can be reduced. Therefore, the integration density of the integrated circuit device 100 can be improved.

[0082] Furthermore, by arranging multiple bit lines in the second wiring layer M2 located on the first wiring layer M1, the bit lines can be designed to be thicker. Therefore, the bit line capacitance can be reduced to improve the electrical performance of the integrated circuit device 100.

[0083] Figures 8 to 12 It is according to the embodiment along Figure 6 A cross-sectional view of a portion of the integrated circuit device 100 taken by line Y1-Y1', to illustrate a method of manufacturing the integrated circuit device 100 according to the process sequence.

[0084] refer to Figure 8A stacked structure in which multiple sacrificial semiconductor layers 104 and multiple nanosheet semiconductor layers NS are alternately stacked on a substrate 102 can be formed. In the stacked structure, the multiple sacrificial semiconductor layers 104 and the multiple nanosheet semiconductor layers NS can comprise semiconductor materials with different etch selectivity. In some embodiments, the multiple nanosheet semiconductor layers NS can comprise Si layers, and the multiple sacrificial semiconductor layers 104 can comprise SiGe films. The SiGe film constituting the sacrificial semiconductor layer 104 can have a Ge content ratio selected from the range of about 5 at% to about 50 at%, for example, about 10 at% to about 40 at%.

[0085] A finned active region FA can be formed by forming a mask pattern with openings that partially expose the top surface of the stacked structure, and using the mask pattern as an etching mask to etch a portion of each of the plurality of sacrificial semiconductor layers 104, the plurality of nanosheet semiconductor layers NS, and the substrate 102. In this case, the finned active region FA can be combined with... Figures 3 to 6 This corresponds to the first active region AP1 in the middle.

[0086] Multiple trench regions can be defined on substrate 102 by means of fin-type active regions FA. Multiple sacrificial semiconductor layers 104 and multiple nanosheet semiconductor layers NS can be retained on the front surface FF of fin-type active regions FA. Then, a device isolation film can be formed to fill the multiple trench regions and cover the sidewalls of fin-type active regions FA.

[0087] refer to Figure 9 , can Figure 8 As a result, multiple dummy gate structures DGS are formed. Each dummy gate structure in the multiple dummy gate structures DGS can extend longitudinally in a first direction (X direction). Each dummy gate structure in the multiple dummy gate structures DGS may include a dummy oxide film D122, a dummy gate layer D124, and a capping layer D126 sequentially stacked on a stacked structure including multiple sacrificial semiconductor layers 104 and multiple nanosheet semiconductor layers NS. In some embodiments, the dummy gate layer D124 may include polysilicon, and the capping layer D126 may include a silicon nitride film.

[0088] The multiple nanosheet semiconductor layers NS can be divided into multiple nanosheet stacks NSS comprising first to third nanosheets N1, N2 and N3 by forming multiple insulating spacers 118 covering the two sidewalls of each of the multiple dummy gate structures DGS, and by using the multiple dummy gate structures DGS and the multiple insulating spacers 118 as an etching mask to etch a portion of each of the multiple sacrificial semiconductor layers 104 and the multiple nanosheet semiconductor layers NS, as well as a portion of the fin active region FA.

[0089] Then, multiple recesses R1 can be formed above each finned active region FA. Each of the first to third nanosheets N1, N2, and N3 can have a width defined by the multiple recesses R1 in the second direction (Y direction). Etching can be performed using dry etching, wet etching, or a combination thereof to form the multiple recesses R1.

[0090] refer to Figure 10 , can Figure 9 The result is the formation of multiple source / drain regions 130A that fill multiple recesses R1. In order to form multiple source / drain regions 130A, semiconductor materials can be epitaxially grown from the sidewalls of each of the first to third nanosheets N1, N2 and N3 exposed in the multiple recesses R1 and the surface of the fin-type active region FA.

[0091] Subsequently, after forming an insulating pad 142 covering multiple source / drain regions 130A and forming an inter-gate insulating film 144 on the insulating pad 142, a portion of each of the insulating pad 142 and the inter-gate insulating film 144 can be etched to expose multiple capping layers D126 (see below). Figure 9 The top surface of the gate layer D124 can then be removed. Thereafter, multiple cover layers D126 can be removed to expose the dummy gate layer D124, and the insulating pad 142 and the inter-gate insulating film 144 can be partially removed such that the top surface of the inter-gate insulating film 144 is at substantially the same height as the top surface of the dummy gate layer D124.

[0092] refer to Figure 11 It can be seen from Figure 10 The dummy gate layer D124 and the dummy oxide film D122 are removed to form the gate structure GS. Then, the plurality of sacrificial semiconductor layers 104 retained on the substrate 102 can be selectively removed via the gate structure GS to extend the gate structure GS to the space between each of the first to third nanosheets N1, N2 and N3 and the space between the first nanosheet N1 and the front surface FF.

[0093] refer to Figure 12 , can Figure 11 The result is the formation of a gate dielectric film 152 covering the exposed surfaces of the first to third nanosheets N1, N2, and N3, as well as each finned active region FA. The gate dielectric film 152 can be formed using an atomic layer deposition (ALD) process.

[0094] Then, a filled gate structure GS can be formed over the gate dielectric film 152 (see...). Figure 11The gate 160. Then, a portion of the top surface of each of the gate 160, the gate dielectric film 152 and the insulating spacer 118 can be removed to reduce their height, thereby forming a plurality of covering insulating patterns 168 covering the top surface of each of the gate 160, the gate dielectric film 152 and the insulating spacer 118.

[0095] Then, a source / drain contact hole exposing a plurality of source / drain regions 130A can be formed between two adjacent gates 160 among the plurality of gates 160. A metal silicide film 172 can be formed on the surface of the plurality of source / drain regions 130A through the source / drain contact hole, and a plurality of source / drain contacts CA filling the source / drain contact hole can be formed on the metal silicide film 172.

[0096] Return to reference Figure 7 ,exist Figure 12 As a result, an etch stop film 182 and an upper insulating film 184 covering the top surfaces of each of the source / drain contact CA, the plurality of covering insulating patterns 168, and the inter-gate insulating film 144 can be sequentially formed to form an upper insulating structure 180. Thereafter, a plurality of source / drain path contacts VA passing through the upper insulating structure 180 in the vertical direction (Z direction) and connected to the source / drain contact CA can be formed; and a plurality of gate contacts CB passing through the upper insulating structure 180 and the covering insulating patterns 168 in the vertical direction (Z direction) and connected to the gate 160 (see [link to relevant documentation]). Figure 6 Then, a first wiring layer M1 can be formed on the upper insulating structure 180, and a second wiring layer M2 can be formed on the first wiring layer M1.

[0097] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A bit unit including a read port and a write port, the bit unit comprising: Multiple active regions, which are spaced parallel to each other in a first direction and extend in a second direction perpendicular to the first direction; as well as A plurality of gates, which are spaced parallel to each other in the second direction, extend in the first direction, and are arranged in at least one of the plurality of active regions to each form a transistor. The read port includes a read transfer transistor and a read pull-down transistor. The write port includes a first transmission transistor, a second transmission transistor, a first pull-down transistor, a second pull-down transistor, a first pull-up transistor, and a second pull-up transistor. The read transmission transistor, the read pull-down transistor, the first transmission transistor, and the first pull-down transistor share an active region.

2. The bit unit according to claim 1, wherein, The read transfer transistor, the read pull-down transistor, the first pull-down transistor, and the first transfer transistor all include N-type transistors.

3. The bit unit according to claim 1, wherein, The plurality of active regions include a first active region, a second active region, a third active region, and a fourth active region. The plurality of gates includes a first gate, a second gate, a third gate, and a fourth gate. The first active region and the first gate form the read transfer transistor. The first active region and the second gate form the read pull-down transistor. The first active region and the third gate form the first pull-down transistor, and The first active region and the fourth gate form the first transmission transistor.

4. The bit unit according to claim 3, wherein, The second active region and the third gate form the first pull-up transistor. The third active region and the second gate form the second pull-up transistor. The fourth active region and the second gate form the second pull-down transistor, and The fourth active region and the third gate form the second transmission transistor.

5. The bit unit according to claim 4, wherein, The first pull-up transistor and the second pull-up transistor include P-type transistors, and The second pull-down transistor and the second transmission transistor include N-type transistors.

6. The bit cell of claim 1, further comprising a first wiring layer disposed on the plurality of gates, the first wiring layer comprising a plurality of metal lines spaced parallel to each other in the first direction and extending in the second direction, wherein, The plurality of metal lines in the first wiring layer include read word lines connected to the read port and write word lines connected to the write port.

7. The bit unit according to claim 6, wherein, The plurality of metal lines in the first wiring layer further include read bit line pads connected to the read port and write bit line pads connected to the write port, and The lengths of the read bit line pads and the write bit line pads in the second direction are less than the lengths of the read word lines and the write word lines in the second direction.

8. The bit cell of claim 7, further comprising a second wiring layer disposed on the first wiring layer, the second wiring layer comprising a plurality of metal lines spaced parallel to each other in the second direction and extending in the first direction, wherein, The plurality of metal lines in the second wiring layer include read bit lines connected to the read bit line pads and write bit lines connected to the write bit line pads.

9. The bit unit according to claim 8, wherein, The thickness of the read bit line and the write bit line in the second direction is greater than the thickness of the read word line and the write word line in the first direction.

10. A bit unit, the bit unit comprising: The read port includes a read transfer transistor and a read pull-down transistor; as well as The write port includes a first transfer transistor, a second transfer transistor, a first pull-down transistor, a second pull-down transistor, a first pull-up transistor, and a second pull-up transistor. The read transmission transistor, the read pull-down transistor, the first transmission transistor, and the first pull-down transistor share an active region.

11. The bit unit according to claim 10, wherein, The read transfer transistor, the read pull-down transistor, the first pull-down transistor, and the first transfer transistor all include N-type transistors.

12. The bit cell according to claim 10, further comprising a first wiring layer disposed on the active region, the first wiring layer comprising a plurality of metal lines, wherein, The first wiring layer extends in a direction parallel to the active region.

13. The bit unit according to claim 10, wherein the bit unit further comprises: A read word line connected to the read port and a write word line connected to the write port are disposed on the active region; as well as The read bit line pads are connected to the read port, and the write bit line pads are connected to the write port. The read bit line pads and the write bit line pads are disposed on the active region. The lengths of the read bit line pads and the write bit line pads are less than the lengths of the read word lines and the write word lines.

14. The bit unit according to claim 12, further comprising a second wiring layer disposed on the first wiring layer, the second wiring layer comprising a plurality of metal lines, wherein, The second wiring layer extends in a direction perpendicular to the active region.

15. The bit unit according to claim 14, wherein, The plurality of metal lines in the second wiring layer include read bit lines connected to the read port and write bit lines connected to the write port.

16. An integrated circuit device, the integrated circuit device comprising: The bit unit includes a read port and a write port, the bit unit comprising: A plurality of active regions, including a first active region, a second active region, a third active region, and a fourth active region, wherein the first active region, the second active region, the third active region, and the fourth active region are spaced parallel to each other in a first direction and extend in a second direction perpendicular to the first direction; and A plurality of gates, including a first gate, a second gate, a third gate, and a fourth gate, wherein the first gate, the second gate, the third gate, and the fourth gate are spaced parallel to each other in a second direction, extend in the first direction, and are arranged in at least one of the plurality of active regions to each form a transistor. The read port includes a read transfer transistor and a read pull-down transistor. The write port includes a first transmission transistor, a second transmission transistor, a first pull-down transistor, a second pull-down transistor, a first pull-up transistor, and a second pull-up transistor. The read transmission transistor, the read pull-down transistor, the first transmission transistor, and the first pull-down transistor share an active region.

17. The integrated circuit device according to claim 16, wherein, The read transfer transistor, the read pull-down transistor, the first pull-down transistor, and the first transfer transistor all include N-type transistors.

18. The integrated circuit device according to claim 16, wherein, The first pull-up transistor and the second pull-up transistor include P-type transistors, and The second pull-down transistor and the second transmission transistor include N-type transistors.

19. The integrated circuit device of claim 16, further comprising a first wiring layer disposed on the plurality of gates, the first wiring layer comprising a plurality of word lines electrically connected to each of the read port and the write port, wherein, The first wiring layer extends in a direction parallel to the active region.

20. The integrated circuit device of claim 19, further comprising a second wiring layer disposed on the first wiring layer, the second wiring layer comprising a plurality of bit lines electrically connected to each of the read port and the write port. in, The second wiring layer extends in a direction perpendicular to the active region.

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