A memory single bit flip test system and method for a protective relay

Abstract

The application discloses a memory single-bit flip test system and method for a relay protection device, and belongs to the technical field of relay protection device reliability testing. The system comprises: a relay protection device to be tested; an automatic test platform configured to issue a memory single-bit flip instruction to the relay protection device to be tested, read the running indicator light state, protection outlet state and event uploading message of the relay protection device to be tested, perform result judgment and write a test report; and a relay protection tester controlled by the automatic test platform and configured to apply an electrical fault quantity signal to the relay protection device to be tested, so as to verify the protection function state of the relay protection device to be tested. The application realizes the automation of the memory single-bit flip test of the relay protection device, effectively saves working hours and improves test efficiency.

Description

Technical Field

[0001] This invention relates to a memory single-bit flip test system and method for relay protection devices, belonging to the field of reliability testing technology for relay protection equipment. Background Technology

[0002] With the rapid development of power systems and the increasing complexity and variability of power grid structures, higher demands are placed on the reliability of relay protection devices. A single-bit anomaly in the storage unit of a relay protection device refers to an unexpected flip of a data bit in the internal RAM, Flash, or DDR storage units during operation, caused by factors such as electromagnetic interference, power fluctuations, temperature drift, and cosmic rays. This flip can lead to errors in critical control variables, abnormal logical judgments, and the risk of malfunction or failure to operate the relay protection device.

[0003] For handling single-bit anomalies, major domestic relay protection manufacturers have adopted a dual mechanism of hardware ECC verification and software CRC verification for memory chips. After the relay protection device is powered on, it has the function of monitoring and verifying all data in memory, and can detect and automatically correct single-bit errors in real time. If the core program area verification fails, the device will alarm and lock out protection, thus eliminating the risks caused by single-bit anomalies.

[0004] Currently, single-bit flips in the memory of relay protection devices are all tested manually. Since memory data is represented by 8-bit hexadecimal numbers (32-bit binary), each address has 32 possible single-bit flips. Given that the number of memory addresses is in the millions or tens of millions, the amount of test data is enormous, and manual testing cannot cover it comprehensively. Furthermore, during the testing process, monitoring of protection outputs, protection function status, device operation indicator lights, and event transmission messages all require manual inspection, which is time-consuming, labor-intensive, and inefficient.

[0005] Therefore, in order to automate the single-bit flip test of the memory of relay protection devices, so as to save working time and improve testing efficiency, there is an urgent need for a single-bit flip test system and method for the memory of relay protection devices. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide a memory single-bit flip test system and method for relay protection devices, which can realize the automation of memory single-bit flip test of relay protection devices, effectively saving working time and improving test efficiency.

[0007] To achieve the above objectives, the present invention is implemented using the following technical solution: In a first aspect, the present invention provides a memory single-bit flip-over test system for relay protection devices, comprising: The relay protection device under test; The automatic testing platform is used to send memory single-bit toggling instructions to the relay protection device under test, read the running indicator status, protection output status and event transmission messages of the relay protection device under test, judge the results and write them into the test report. The relay protection tester, controlled by an automatic test platform, applies electrical fault signals to the relay protection device under test for verifying the protection function status of the device.

[0008] Furthermore, the automated testing platform includes: The single-bit memory test module is connected to the debugging port of the relay protection device under test. It is used to generate the memory address test range of the relay protection device under test and send memory value read and write instructions to the relay protection device under test. The memory write instruction includes specified bit flipping and random bit flipping. The communication protocol engine module is connected to the Ethernet port of the relay protection device under test. It is used to generate a communication point table of the relay protection device under test, read the status of the device's operating indicator lights and event transmission messages, and issue pressure plate activation / deactivation and setting instructions to the relay protection device under test. The tester interface module is connected to the Ethernet port of the relay protection tester and is used to send test parameter commands to the relay protection tester. The test template editing module is used to generate test cases based on the type of the relay protection device under test, the memory address test range, and the communication point table. The main automated testing module is used to execute test tasks based on test cases and generate test reports.

[0009] Furthermore, the test report records test cases, test case result values, and test conclusions. The test case result values ​​include: memory address, toggled bit, original memory value, modified memory value, device operation indicator status verification, protection exit monitoring during memory modification, protection function status verification after memory modification, and event upload message verification. The test conclusions include whether the test results are qualified.

[0010] Furthermore, the analog output interface of the relay protection tester is connected to the analog input terminal of the relay protection device under test, the digital input interface of the relay protection tester is connected to the output terminal of the relay protection device under test, and the digital output interface of the relay protection tester is connected to the input terminal of the relay protection device under test.

[0011] In a second aspect, the present invention provides a method for testing single-bit flipping of memory in a relay protection device, based on the system described in the first aspect, comprising: Model the relay protection device under test, and generate the communication point table and memory address range of the relay protection device under test; Create test cases based on the type of the relay protection device under test, the communication point table, and the memory address range; According to the test cases, the relay protection device under test is sent with instructions for enabling / disabling the pressure plate and modifying the setting, so that the relay protection device under test meets the test status requirements; The test steps are executed repeatedly according to the test cases until all memory addresses have been processed, and a test report is generated. The testing steps include: The system sends memory read and memory write commands to the relay protection device under test. The memory write command includes specified bit flipping and random bit flipping. During the memory modification process, the system obtains the protection output action status of the relay protection device under test to verify whether the protection output status is qualified, and obtains the running indicator status of the relay protection device under test to verify whether the running indicator status is qualified. By applying electrical fault parameter commands to the relay protection device under test using a relay protection tester, the protection function status of the relay protection device under test can be verified to be qualified. Acquire the event transmission message of the relay protection device under test, and verify whether the event transmission message is qualified; Write the memory address, toggled bit, original memory value, modified memory value, protection output status verification result, device operation indicator status verification result, protection function status verification result, and event transmission message verification result into the test report.

[0012] Furthermore, the specified bit-flipping or random bit-flipping method includes: Obtain the original memory value of the relay protection device under test at a specified memory address. The original memory value is in 8-bit hexadecimal format. Convert the original memory value to a 32-bit unsigned decimal integer; Determine the target flipped bit. If it is a specified bit flip, the target flipped bit is taken from the preset bit number in the test case. If it is a random bit flip, the target flipped bit is determined by a uniform random number generation function. Construct a mask value based on the determined target flipped bits, and perform a 32-bit bitwise XOR operation between the converted original decimal memory value and the constructed mask value to obtain the decimal intermediate result of the target modified value. Sum all the bits resulting from the XOR operation according to their bit weights to obtain the final 32-bit unsigned decimal target modified value; Convert the decimal target modification value to a hexadecimal number to obtain an 8-digit hexadecimal target modification value; The 8-bit hexadecimal target modification value is sent to the original memory address of the relay protection device under test, completing the single-bit memory flip operation of that memory address.

[0013] Furthermore, the verification of whether the protected exit status is qualified includes: Based on the expected results of the test cases, determine whether the obtained protection exit status is qualified. The status of the protection exit includes malfunction and normal operation.

[0014] Furthermore, the verification of whether the protection function status is qualified includes: Obtain the protection function status of the relay protection device under test, and determine whether the protection function status is qualified based on the expected results of the test cases. The protection function status includes normal and abnormal, and the abnormal includes protection failure to operate and protection malfunction.

[0015] Furthermore, verifying the validity of the event transmission message includes: Based on the acquired event transmission messages, extract the event name, event status, event timestamp, and fault parameters. Based on the expected results of the test cases, determine whether the protection event transmission messages are qualified.

[0016] Furthermore, the electrical fault parameter instructions include the fault type and duration.

[0017] Thirdly, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the methods described above.

[0018] Fourthly, the present invention provides a computer device, comprising: Memory, used to store computer programs / instructions; A processor for executing the computer program / instructions to implement the steps of any of the methods described above.

[0019] Fifthly, the present invention provides a computer program product, including a computer program / instructions that, when executed by a processor, implement the steps of any of the methods described above.

[0020] Compared with the prior art, the beneficial effects achieved by the present invention are as follows: This invention provides a memory single-bit flip-over testing system and method for relay protection devices, which effectively improves testing efficiency and shortens the testing cycle compared to existing technologies. Furthermore, this invention can record multiple operational information of the relay protection device under test, ensuring complete test data. Testers only need to design test cases in advance through the automated testing platform, and can start testing with one click until all test cases are completed, without manual intervention. This significantly reduces the technical experience requirements for test technicians, simplifies the testing process, and improves testing efficiency. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of a memory single-bit flip test system for a relay protection device provided in Embodiment 1 of the present invention; Figure 2 This is a flowchart illustrating a single-bit flip test method for a relay protection device provided in Embodiment 2 of the present invention. Figure 3 This is a flowchart illustrating the single-bit memory flipping method in Embodiment 2 of the present invention.

[0022] In the diagram: 1. Automatic test platform; 1-1. Automatic test main module; 1-2. Memory single-bit test module; 1-3. Communication protocol engine module; 1-4. Tester interface module; 1-5. Test template editing module; 2. Network switch; 3. Relay protection device under test; 4. Relay protection tester. Detailed Implementation

[0023] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments and specific features in the embodiments are detailed descriptions of the technical solution of the present application, rather than limitations thereof. In the absence of conflict, the embodiments and technical features in the embodiments can be combined with each other.

[0024] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship. Example 1

[0025] like Figure 1 As shown, this embodiment provides a memory single-bit flip test system for relay protection devices, including: 3. Relay protection device under test; Automatic test platform 1 is used to send a single-bit memory toggle instruction to the relay protection device under test 3, read the status of the operation indicator light, the status of the protection output and the event transmission message of the relay protection device under test 3, judge the result and write it into the test report. The relay protection tester 4, controlled by the automatic test platform 1, applies electrical fault signals to the relay protection device 3 under test for verifying the protection function status of the relay protection device 3 under test.

[0026] The automatic test platform 1, relay protection tester 4, and relay protection device under test 3 are connected to the network switch 2 via twisted pair cables to realize communication connection and data transmission between the devices. Twisted pair cables are low in cost and easy to obtain. Under the premise of meeting the signal transmission conditions, using twisted pair cables as the data transmission medium can effectively reduce communication costs.

[0027] Furthermore, the automated testing platform 1 includes: The memory single-bit test module 1-2 is connected to the debugging port of the relay protection device under test 3. It is used to generate the memory address test range of the relay protection device under test 3 and send memory value read instructions and write instructions to the relay protection device under test 3. The memory write instructions include specified bit flipping and random bit flipping. The communication protocol engine module 1-3 is connected to the Ethernet port of the relay protection device 3 under test, and performs data communication through the IEC61850 protocol. It is used to generate the communication point table of the relay protection device 3 under test, read the status of the device operation indicator light and the event transmission message, and issue pressure plate activation / deactivation and setting value instructions to the relay protection device 3 under test. The tester interface modules 1-4 are connected to the Ethernet port of the relay protection tester 4 and are used to send test parameter commands to the relay protection tester 4. Test template editing modules 1-5 are used to generate test cases based on the type of the relay protection device under test 3, the memory address test range, and the communication point table. The main automatic testing module 1-1 is used to execute test tasks based on test cases and generate test reports.

[0028] like Figure 1 As shown, to achieve the connection between the relay protection tester 4 and the relay protection device under test 3, the analog output interface of the relay protection tester 4 is connected to the analog input terminal of the relay protection device under test 3. Its function is to output analog quantities to the relay protection device under test 3 according to the set test parameters. The analog quantities include voltage and current. The digital input interface of the relay protection tester 4 is connected to the output terminal of the relay protection device under test 3. Its function is to receive the protection output operation status. The digital output interface of the relay protection tester 4 is connected to the input terminal of the relay protection device under test 3. Its function is to output DC excitation to the input quantity of the relay protection device under test 3 according to the set test parameters. The DC excitation type is generally 110VDC or 220VDC.

[0029] The automatic testing platform 1 generates test cases based on the single-bit memory anomaly protection requirements of the relay protection device. Based on the test cases, it sends pressure plate activation / deactivation and setting instructions to the relay protection device under test 3 through the protocol engine module, sends memory value read / write instructions to the relay protection device through the single-bit memory testing modules 1-2, and sends test parameter instructions to the relay protection tester 4 through the tester interface modules 1-4. It then verifies the device's operating indicator light status, monitors the protection output during memory modification, verifies the protection function status after memory modification, verifies the event upload message, and generates a test report.

[0030] In this embodiment, test cases are generated through the test template editing module. The test cases are reusable and effective. Through the open design of the memory single-bit flip-flop test system for relay protection devices of this invention, test cases are created according to three types of relay protection devices under test. These relay protection device categories include: line protection, transformer protection, reactor protection, busbar protection, generator-transformer group protection, etc., resulting in highly scalable test cases.

[0031] The test cases consist of multiple XML-formatted test files, each corresponding to a specific test item, such as: random bit flipping of memory values, specified bit flipping of memory values, modification of a single memory address at once, and modification of multiple memory addresses at once. The test files include: pressure plate activation / deactivation and setting instructions, memory value read / write instructions, electrical fault parameter issuance instructions, protection output status monitoring logic during memory modification, device operation indicator status verification logic, protection function status verification logic after memory value modification, and event upload message verification logic. The automatic test main module 1-1 reads and writes the test cases and displays the test case content on a designated interface on the PC for viewing and modification.

[0032] In this implementation, the test report is automatically generated by the program and is in Excel format. The test report records test cases, test case result values, and test conclusions. Test case result values ​​include: memory address, toggled bits, original memory value, modified memory value, device operation indicator status verification, protection exit status monitoring during memory modification, protection function status verification after memory modification, and event upload message verification. Test conclusions are automatically entered into the report after each test item is completed during the actual test, including whether the test result is qualified or unqualified. Unqualified test cases are highlighted in red on a designated interface on the PC for troubleshooting.

[0033] The test report in this invention can be customized according to user needs, has good scalability, and automatically writes and saves test data and results after each test project is completed, effectively reducing test complexity and labor costs and improving test efficiency. Example 2

[0034] like Figure 2 As shown, this embodiment provides a method for testing single-bit flipping of memory in a relay protection device, based on the system described in any one of Embodiment 1, comprising: Model the relay protection device under test, and generate the communication point table and memory address range of the relay protection device under test; Create test cases based on the type of the relay protection device under test, the communication point table, and the memory address range; According to the test cases, the relay protection device under test is sent with instructions for enabling / disabling the pressure plate and modifying the setting, so that the relay protection device under test meets the test status requirements; The test steps are executed repeatedly according to the test cases until all memory addresses have been processed, and a test report is generated. The testing steps include: The system sends memory read and memory write commands to the relay protection device under test. The memory write command includes specified bit flipping and random bit flipping. During the memory modification process, the system obtains the protection output action status of the relay protection device under test to verify whether the protection output status is qualified, and obtains the running indicator status of the relay protection device under test to verify whether the running indicator status is qualified. By applying electrical fault parameter commands to the relay protection device under test using a relay protection tester, the protection function status of the relay protection device under test can be verified to be qualified. Acquire the event transmission message of the relay protection device under test, and verify whether the event transmission message is qualified; Write the test data of the current memory address, the verification results of the protection exit status, the verification results of the device operation indicator status, the verification results of the protection function status, and the verification results of the event transmission message into the test report.

[0035] The memory single-bit flip test method for relay protection devices provided in this embodiment involves the following steps in its application process: Step S101: Set up the test environment by connecting the automatic test platform 1, the relay protection tester 4, and the relay protection device under test 3 to the same network switch 2. The automatic test platform 1 establishes a communication connection with the Ethernet port of the relay protection device 3 under test through the communication protocol engine modules 1-3; The automatic test platform 1 establishes a test connection with the debugging port of the relay protection device under test 3 through the memory single-bit test module 1-2; Step S102: Model the relay protection device 3 under test, and generate the communication point table and memory address test range of the relay protection device 3 under test; the communication point table is read online and automatically generated by the communication protocol engine module 1-3; the memory address test range is read online and automatically generated by the memory single bit test module 1-2. Step S103: Create test cases according to the communication point table and memory address test range of the relay protection device under test. The test cases include multiple test files in XML format, each corresponding to a test item, such as: random flipping of memory value bits, specified flipping of memory value bits, modification of a single memory address at once, modification of multiple memory addresses at once, etc. The test files include: pressure plate activation / deactivation and setting instructions, memory value read / write instructions, electrical fault parameter issuance instructions, monitoring of protection output status during memory modification, verification of device operation indicator status, verification of protection function status after memory value modification, and verification of event transmission messages. Step S104: Start the test. According to the test instructions, the communication protocol engine module 1-3 sends the pressure plate activation / deactivation and setting value modification operations to the relay protection device under test 3, so that the relay protection device under test 3 meets the test status requirements. Step S105: According to the test instructions, the memory single-bit test module 1-2 sends memory read instructions and memory write instructions to the relay protection device under test 3 to verify the memory protection reliability of the relay protection device 3. The memory write instructions include: specified bit flipping and random bit flipping. Specified bit flipping refers to the bit flipping sequence number set before the test, with a sequence number range of 0 ≤ n ≤ 31. Random bit flipping refers to the test system generating a random number after the test starts, using the random number as the bit flipping sequence number, i.e., n = rand(0, 31), where rand(a, b) is a uniform random number generation function that returns any integer within the closed interval [a, b], with a sequence number range of 0 ≤ n ≤ 31, covering all 32 binary bits.

[0036] Step S106: Monitoring the status of protection output during memory modification. The specific operation is as follows: The input terminal of the relay protection tester 4 receives the protection output action status of the relay protection device 3 under test. The protection output status monitoring includes: malfunction and no malfunction. Based on the expected results of the test case, it is determined whether the protection output status is qualified. Step S107: Verify the status of the device operation indicator light. The specific operation is as follows: Obtain the status of the operation indicator light of the relay protection device under test 3 through the communication protocol engine module 1-3. The status of the device operation indicator light includes: lit and off. Based on the expected results of the test case, determine whether the status of the device operation indicator light is qualified. Step S108: Verify the protection function status after the memory value modification is completed. The specific operation is as follows: After the memory value modification is completed, according to the test instruction, the tester interface module 1-4 sends test parameters to the relay protection tester 4. According to the test parameters, the relay protection tester 4 applies electrical fault quantities to the relay protection device under test 3. The input terminals of the relay protection tester 4 receive the protection output action status of the relay protection device under test 3 and verify the protection function status of the relay protection device under test 3. The protection function status includes: normal and abnormal. Abnormal situations include: protection failure to operate and protection maloperation. According to the expected results of the test cases, determine whether the protection function status is qualified. Step S109: Event transmission message verification, the specific operation is as follows: through the communication protocol engine module 1-3, the event transmission message of the relay protection device under test 3 is obtained, the automatic test main module 1-1 parses the protection event transmission message, extracts information such as event name, event status, event timestamp, fault parameters, etc., and judges whether the protection event transmission message is qualified according to the expected results of the test case. Step S110: Write the memory address, flipped bit, original memory value, modified memory value, monitoring results of protection exit status during memory modification, verification results of device operation indicator status, verification results of protection function status after memory value modification is completed, and verification results of event uploading message into the test report; Step S111: Determine if this is the last memory address, and repeat steps S105 to S110 until all memory addresses have been processed. Generate a test report (Excel format). The test report is saved locally (on the PC where the automatic test platform 1 is located) for testers to review.

[0037] According to the above-described solution of the present invention, after clicking the "Start Test" button, test cases can be automatically loaded and instructions executed sequentially, achieving one-click operation and improving the user experience. It effectively simplifies the testing process, shortens testing time, and improves testing efficiency, possessing significant practical value.

[0038] To achieve precise flipping of specified or random bits, and to adapt to the 32-bit binary single-bit flipping requirement of 8-bit hexadecimal memory values, such as... Figure 3 As shown, the flipping method for specifying bit flipping or random bit flipping includes: 1. Obtain 8-bit hexadecimal raw memory value: The raw data at a specified memory address of the relay protection device under test is read through the single-bit memory test module. The data format is an 8-bit hexadecimal number, denoted as... ; 2. Convert to decimal value: Convert the 8-bit hexadecimal raw memory value to a 32-bit unsigned decimal integer. The conversion formula is: ; In the formula 8-digit hexadecimal number The Bit( (the least significant bit) ∈{0,1,...,9,A,B,C,D,E,F}, corresponding to decimal values ​​0~15; 3. Random / Specified Bit Flip: Determine the target bit flip n, n∈N and 0≤n≤31; if it is a specified bit flip, take the preset bit index in the test case; if it is a random bit flip, it is determined by a uniform random number generation function, i.e., n=rand(0,31), where rand(a,b) is a uniform random number generation function that returns any integer in the closed interval [a,b], achieving random coverage of all bits of the 32-bit binary system; 4. Generate the corresponding bit mask: Construct the mask value based on the target flipped bits n. The mask value formula is as follows: In the formula The decimal representation of the mask value is a 32-bit binary form where only the nth bit is 1 and the rest are 0. 5. Bitwise XOR Operation: Performs a 32-bit bitwise XOR operation between the original decimal memory value and the mask value to obtain the intermediate decimal result of the target modified value. The formula is as follows: ， In the formula, ⊕ is the bitwise XOR operator, and the bitwise operation rule is: for and For the same bit k, if the original bit ≠ mask bit Then the result bit =1; if the original bit =mask bits Then the result bit =0; 6. Different bit weighting: Sum all the bits resulting from the XOR operation according to their bit weights to obtain the final 32-bit unsigned decimal target modified value. The summation formula is as follows: In the formula The result of the XOR operation on the k-th bit. Let k be the bit weight of the k-th bit. 7. Convert to 8-digit hexadecimal value: Convert the decimal target value back to a hexadecimal number using the following formula: In the formula This is a formatting function for converting decimal to hexadecimal; the generated hexadecimal target value is modified using a single-bit memory test module. The format is a fixed 8-digit hexadecimal number (if the conversion result is less than 8 digits, zeros are padded on the left to bring it to 8 digits), consistent with the data storage format in the memory of the relay protection device; 8. Write the value to the corresponding memory address: The target modified value of 8 hexadecimal bits is sent to the original memory address of the relay protection device under test through the memory single-bit test module, and the memory single-bit flip operation of the address is completed. 9. Determine if this is the last memory address, and repeat steps 1 to 8 until all memory addresses have been processed.

[0039] This algorithm achieves precise and automated flipping of single bits in memory through the above 9 steps, and supports both specified and random flipping modes to adapt to the needs of different test cases. The following specific example verifies the algorithm's execution process:

Example

[0040] Example output: Original memory value 0x00001009 → target modified value 0x0000100B, the first bit (0) is flipped to 1, and the remaining bits remain unchanged, accurately realizing the single bit flipping function of memory.

[0041] The testing system and method of this invention have been successfully applied to the verification of single-bit flip-over testing of relay protection device memory. It can fully test the reliability of the memory protection of relay protection device, effectively improve testing efficiency and reduce labor costs. It has very important reference value for improving the reliability and safety of smart substation operation.

[0042] Example 3: This example provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in any of Examples 2.

[0043] Example 4: This example provides a computer device, including: Memory, used to store computer programs / instructions; A processor for executing the computer program / instructions to implement the steps of the method described in any of Embodiment 2.

[0044] Example 5: This example provides a computer program product, including a computer program / instructions, which, when executed by a processor, implement the steps of the method described in any one of Examples 2.

[0045] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

[0046] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program products. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0047] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0048] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0049] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0050] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure and not to limit its protection scope. Although this disclosure has been described in detail with reference to the above embodiments, those skilled in the art should understand that after reading this disclosure, they can still make various changes, modifications or equivalent substitutions to the specific implementation of the invention, but these changes, modifications or equivalent substitutions are all within the protection scope of the pending claims.

Claims

1. A memory single-bit flip-over test system for relay protection devices, characterized in that, include: The relay protection device under test; The automatic testing platform is used to send memory single-bit toggling instructions to the relay protection device under test, read the running indicator status, protection output status and event transmission messages of the relay protection device under test, judge the results and write them into the test report. The relay protection tester, controlled by an automatic test platform, applies electrical fault signals to the relay protection device under test for verifying the protection function status of the device.

2. The memory single-bit flip test system for relay protection devices according to claim 1, characterized in that, The automated testing platform includes: The single-bit memory test module is connected to the debugging port of the relay protection device under test. It is used to generate the memory address test range of the relay protection device under test and send memory value read and write instructions to the relay protection device under test. The memory write instruction includes specified bit flipping and random bit flipping. The communication protocol engine module is connected to the Ethernet port of the relay protection device under test. It is used to generate a communication point table of the relay protection device under test, read the status of the device's operating indicator lights and event transmission messages, and issue pressure plate activation / deactivation and setting instructions to the relay protection device under test. The tester interface module is connected to the Ethernet port of the relay protection tester and is used to send test parameter commands to the relay protection tester. The test template editing module is used to generate test cases based on the type of the relay protection device under test, the memory address test range, and the communication point table. The main automated testing module is used to execute test tasks based on test cases and generate test reports.

3. The memory single-bit flip test system for relay protection devices according to claim 2, characterized in that, The test report records the test cases, the result values ​​of the test cases, and the test conclusions. The result values ​​of the test cases include: memory address, toggled bits, original memory value, modified memory value, device operation indicator status verification, protection exit monitoring during memory modification, protection function status verification after memory modification, and event upload message verification. The test conclusions include whether the test results are qualified.

4. The memory single-bit flip test system for relay protection devices according to claim 3, characterized in that, The analog output interface of the relay protection tester is connected to the analog input terminal of the relay protection device under test, the digital input interface of the relay protection tester is connected to the output terminal of the relay protection device under test, and the digital output interface of the relay protection tester is connected to the input terminal of the relay protection device under test.

5. A method for testing single-bit flipping of memory in a relay protection device, based on the system described in any one of claims 1-4, characterized in that, The method includes: Model the relay protection device under test, and generate the communication point table and memory address range of the relay protection device under test; Create test cases based on the type of the relay protection device under test, the communication point table, and the memory address range; According to the test cases, the relay protection device under test is sent with instructions for enabling / disabling the pressure plate and modifying the setting, so that the relay protection device under test meets the test status requirements; The test steps are executed repeatedly according to the test cases until all memory addresses have been processed, and a test report is generated. The testing steps include: The system sends memory read and memory write commands to the relay protection device under test. The memory write command includes specified bit flipping and random bit flipping. During the memory modification process, the system obtains the protection output action status of the relay protection device under test to verify whether the protection output status is qualified, and obtains the running indicator status of the relay protection device under test to verify whether the running indicator status is qualified. By applying electrical fault parameter commands to the relay protection device under test using a relay protection tester, the protection function status of the relay protection device under test can be verified to be qualified. Acquire the event transmission message of the relay protection device under test, and verify whether the event transmission message is qualified; Write the memory address, toggled bit, original memory value, modified memory value, protection output status verification result, device operation indicator status verification result, protection function status verification result, and event transmission message verification result into the test report.

6. The memory single-bit flip test method for relay protection devices according to claim 5, characterized in that, The specified bit-flipping or random bit-flipping method includes: Obtain the original memory value of the relay protection device under test at a specified memory address. The original memory value is in 8-bit hexadecimal format. Convert the original memory value to a 32-bit unsigned decimal integer; Determine the target flipped bit. If it is a specified bit flip, the target flipped bit is taken from the preset bit number in the test case. If it is a random bit flip, the target flipped bit is determined by a uniform random number generation function. Construct a mask value based on the determined target flipped bits, and perform a 32-bit bitwise XOR operation between the converted original decimal memory value and the constructed mask value to obtain the decimal intermediate result of the target modified value. Sum all the bits resulting from the XOR operation according to their bit weights to obtain the final 32-bit unsigned decimal target modified value; Convert the decimal target modification value to a hexadecimal number to obtain an 8-digit hexadecimal target modification value; The 8-bit hexadecimal target modification value is sent to the original memory address of the relay protection device under test, completing the single-bit memory flip operation of that memory address.

7. The memory single-bit flip test method for relay protection devices according to claim 6, characterized in that, The verification of whether the protected exit status is qualified includes: Based on the expected results of the test cases, determine whether the obtained protection exit status is qualified. The status of the protection exit includes malfunction and normal operation.

8. The memory single-bit flip test method for relay protection devices according to claim 7, characterized in that, Whether the verification protection function status is qualified includes: Obtain the protection function status of the relay protection device under test, and determine whether the protection function status is qualified based on the expected results of the test cases. The protection function status includes normal and abnormal, and the abnormal includes protection failure to operate and protection malfunction.

9. The memory single-bit flip test method for relay protection devices according to claim 8, characterized in that, Verification of the validity of the event upload message includes: Based on the acquired event transmission messages, extract the event name, event status, event timestamp, and fault parameters. Based on the expected results of the test cases, determine whether the protection event transmission messages are qualified.

10. The memory single-bit flip test method for relay protection devices according to claim 9, characterized in that, The electrical fault parameter instructions include the fault type and duration.

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