High-precision linear decibel programmable gain amplifier and control method

Abstract

The application discloses a high-precision linear decibel programmable gain amplifier and a control method. The high-precision linear decibel programmable gain amplifier comprises a segmented attenuation network, a plurality of transconductance stage arrays, a digital logic control module, an adjustable current bank and an output amplifier. The segmented attenuation network is used for receiving a differential input signal and discretely attenuating the differential input signal into a plurality of groups of attenuation signals with equal decibel intervals. The plurality of transconductance stage arrays are used for receiving the plurality of groups of attenuation signals. The digital logic control module is used for receiving a plurality of digital gain control words and generating a gating signal and a control signal. The gating signal is used for gating two adjacent transconductance amplifiers in the plurality of transconductance stage arrays. The control signal is used for distributing current between the two adjacent transconductance amplifiers. The adjustable current bank is used for distributing total tail current to the two adjacent transconductance amplifiers according to the control signal. The output amplifier is used for collecting output currents of all the transconductance amplifiers through a feedback network and outputting a final linear decibel gain signal. The application fundamentally eliminates the influence of process, voltage and temperature fluctuations on gain accuracy.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design technology, specifically to a high-precision linear decibel programmable gain amplifier and its control method. Background Technology

[0002] Ultrasonic imaging and sonar scanning systems, as core branches of active acoustic detection technology, have been widely applied in fields such as medical diagnosis, non-destructive testing, underwater target identification, and marine topographic mapping. Both are based on the pulse-echo principle: the system emits sound waves (ultrasonic or sonar signals) that penetrate the medium, receives the echo signals reflected or scattered by the target, and reconstructs the image or structural features of the object being measured by analyzing its transit time, amplitude, phase, and other information. With the development of electronic technology and signal processing algorithms, modern systems place higher demands on spatial resolution, dynamic range, and real-time imaging capabilities.

[0003] However, in real physical environments, ultrasonic and sonar signals suffer severe attenuation during propagation due to absorption, scattering, and diffraction effects of the medium, and the degree of attenuation increases exponentially with propagation depth (i.e., echo reception time). This inherent characteristic results in the echo signal amplitude of deep targets often being several orders of magnitude weaker than that of shallow targets (dynamic range can reach 80dB~120dB), posing a significant challenge to subsequent signal detection and imaging processing.

[0004] To compensate for signal attenuation caused by absorption, scattering, and diffraction effects, existing technologies employ amplifiers with gain that varies with time (or depth). Higher gain is applied to weak echoes in deeper layers, while lower gain is applied to strong echoes in shallower layers, thereby compressing the large dynamic range of the input signal into a level range that can be processed by the subsequent analog-to-digital converter (ADC). Among these, the analog controlled voltage gain amplifier (VGA) has become a key module for achieving this time-gain compensation and adaptive gain control due to its continuously adjustable gain, fast response speed, and low noise figure. This type of amplifier changes its gain coefficient by an externally applied control voltage (such as a ramp voltage or closed-loop feedback voltage), thereby compressing signal amplitude fluctuations within the dynamic range, preventing ADC saturation, and maximizing the system's signal-to-noise ratio.

[0005] However, existing analog controlled voltage gain amplifiers (VGAs) are susceptible to fluctuations in process, temperature, and voltage (PVT). Furthermore, noise in the control signal can be directly coupled to the output, leading to a decrease in gain accuracy. Summary of the Invention

[0006] To address this issue, this application provides a high-precision linear decibel programmable gain amplifier and its control method, thereby solving the problem that existing analog control voltage gain amplifiers are easily affected by process, temperature, and voltage fluctuations.

[0007] To achieve the above objectives, this application provides the following technical solution:

[0008] In a first aspect, a high-precision linear decibel programmable gain amplifier includes:

[0009] A segmented attenuation network is used to receive differential input signals and discretely attenuate the differential input signals into multiple sets of attenuated signals with equal decibel intervals; the segmented attenuation network is composed of a multi-stage R-2R trapezoidal resistor network.

[0010] A multi-channel transconductance stage array is used to receive multiple sets of attenuated signals; the multi-channel transconductance stage array is composed of multiple transconductance amplifiers connected in parallel, and the input terminal of each transconductance amplifier is electrically connected to one attenuation signal node of the multi-stage R-2R trapezoidal resistor network.

[0011] A digital logic control module is used to receive a multi-bit digital gain control word and generate a gating signal and a control signal according to the multi-bit digital gain control word; the gating signal is used to select two adjacent transconductance amplifiers in the multi-channel transconductance stage array to ensure that under any given digital gain control word, only two adjacent transconductance amplifiers are in the active gating state; the control signal is used to perform current distribution between the two selected adjacent transconductance amplifiers.

[0012] An adjustable current bank is used to distribute the total tail current to the two adjacent selected transconductance amplifiers according to the control signal.

[0013] The output amplifier stage is used to summarize the output currents of all transconductance amplifiers through a feedback network and output the final linear decibel gain signal.

[0014] Preferably, the attenuation of each stage of the segmented attenuation network is 6.02 dB.

[0015] Preferably, the multi-channel transconductance stage array is composed of 9 transconductance amplifiers connected in parallel, and each of the transconductance amplifiers adopts a wide-swing folded cascade architecture.

[0016] Preferably, the 9-channel transconductance amplifier includes odd-numbered stages and even-numbered stages, with the tail current of the odd-numbered stages connected to a first current bus and the tail current of the even-numbered stages connected to a second current bus.

[0017] Preferably, the multi-bit digital gain control word is an 8-bit digital gain control word, which is divided into 3 high bits and 5 low bits. The 3 high bits are used to generate the gating signal, and the 5 low bits are used to generate the control signal.

[0018] Preferably, the digital logic control module includes a 3-to-8 decoder and an LSB decoder. The 3-to-8 decoder is used to generate the strobe signal based on the 3 high-order bits, and the LSB decoder is used to generate the control signal based on the 5 low-order bits. The LSB decoder is a Celsius decoder.

[0019] Preferably, the adjustable current library includes 32 unit current sources, and the on or off state of the 32 unit current sources is controlled by the digital logic control module, so that linear interpolation adjustment is achieved within the equal decibel intervals of the segmented attenuation network.

[0020] Preferably, the digital logic control module is also used to receive a direction selection signal, which is used to lock the switching logic when the multi-bit digital gain control word undergoes a cross-regional jump, so as to eliminate glitches in the output signal.

[0021] Secondly, a high-precision linear decibel programmable gain control method, applied to the aforementioned high-precision linear decibel programmable gain amplifier, includes:

[0022] Receives a multi-bit digital gain control word and splits it into high and low bits;

[0023] After the high-order bits are decoded, two adjacent transconductance amplifiers in the multi-channel transconductance stage array are selected and activated.

[0024] The low-order bits are decoded to control the adjustable current bank and determine the distribution ratio of the total tail current between the two selected transconductance amplifiers.

[0025] The two selected transconductance amplifiers weight the attenuation signals of different nodes of the segmented attenuation network according to the allocation ratio, and output the final linear decibel gain signal through the output amplification stage.

[0026] Preferably, the method further includes: when the multi-bit digital gain control word jumps, determining whether it is at the inter-stage switching critical point; if it is at the critical point, then using the direction selection signal to execute glitch-free switching logic and locking the switching state; if it is not at the critical point, then maintaining the current current distribution.

[0027] Compared with the prior art, this application has at least the following beneficial effects:

[0028] 1. This application provides a high-precision linear decibel programmable gain amplifier, comprising:

[0029] A segmented attenuation network receives the differential input signal and discretely attenuates it into multiple sets of attenuated signals with equal decibel intervals. A multi-channel transconductance stage array receives these attenuated signals. A digital logic control module receives a multi-bit digital gain control word and generates a gating signal and a control signal based on the word. The gating signal selects two adjacent transconductance amplifiers in the multi-channel transconductance stage array. The control signal distributes current between the selected two adjacent transconductance amplifiers. An adjustable current bank distributes the total tail current to the selected two adjacent transconductance amplifiers according to the control signal. An output amplification stage aggregates the output currents of all transconductance amplifiers through a feedback network and outputs the final linear decibel gain signal. This application replaces traditional analog voltage control with a digitally controlled current ratio distribution method, making the gain accuracy depend only on the ratio parameter of the transconductance stage, rather than absolute device parameters or control voltage, thus fundamentally eliminating the impact of process, voltage, and temperature fluctuations on gain accuracy.

[0030] 2. This application adopts an architecture that separates the tail current paths of odd-numbered and even-numbered stages. Combined with the direction selection signal, it executes glitch-free switching logic when the control code jumps, which solves the gain jump problem caused when the control word crosses the region boundary. Attached Figure Description

[0031] To more intuitively illustrate the prior art and this application, exemplary drawings are provided below. It should be understood that the specific shapes and structures shown in the drawings should not generally be regarded as limiting conditions for implementing this application; for example, based on the technical concept disclosed in this application and the exemplary drawings, those skilled in the art are able to easily make conventional adjustments or further optimizations to the addition / reduction / classification, specific shapes, positional relationships, connection methods, size ratios, etc. of certain units (components).

[0032] Figure 1 This is a schematic diagram of the structure of a high-precision linear decibel programmable gain amplifier provided in Embodiment 1 of this application;

[0033] Figure 2 This is a schematic diagram of the connection structure between the current control switch and the amplifier switch control provided in Embodiment 1 of this application;

[0034] Figure 3 This is a flowchart illustrating the control method logic provided in Embodiment 1 of this application.

[0035] Figure 4 This is a schematic diagram of the gain control results provided in Embodiment 1 of this application. Detailed Implementation

[0036] The present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0037] In the description of this application: unless otherwise stated, "a plurality of" means two or more. The terms "first," "second," "third," etc., in this application are intended to distinguish the objects referred to and do not have any special meaning in terms of technical connotation (e.g., they should not be construed as an emphasis on importance or order). Expressions such as "including," "comprising," and "having" also mean "not limited to" (certain units, components, materials, steps, etc.).

[0038] The terms used in this application, such as "upper," "lower," "left," "right," and "middle," are generally used to indicate the general relative positional relationship for the purpose of intuitive understanding by referring to the accompanying drawings, and are not absolute limitations on the positional relationship in the actual product.

[0039] Example 1

[0040] This embodiment provides a high-precision linear-in-dB programmable gain amplifier (PGA) for use in ultrasonic imaging and sonar scanning systems. It can achieve linear decibel adjustment in very small steps (about 0.188 dB) and eliminate glitch during switching.

[0041] Please see Figure 1 and Figure 2 The high-precision linear decibel programmable gain amplifier provided in this embodiment includes a segmented attenuation network, a multi-channel transconductance (g_m) array, a digital logic control module, an adjustable current library, and an output amplification stage.

[0042] The segmented attenuation network is used to receive differential input signals (VIP, VIN) and discretely attenuate the differential input signals into multiple sets of attenuated signals with equal decibel intervals; the segmented attenuation network is composed of a multi-stage R-2R trapezoidal resistor network.

[0043] Specifically, the segmented attenuation network uses an 8-stage R-2R resistor ladder network as a segmented attenuator to discretely attenuate the input differential signal into 9 groups of signals with equal decibel intervals, with each stage interval being approximately 6.02 dB (i.e., the attenuation amount of each stage of the segmented attenuation network is 6.02 dB).

[0044] More specifically, each R-2R node (TAP0 to TAP8) in the R-2R ladder network provides a constant gain order. In this embodiment, the attenuation of each order is set to 6.02 dB. The differential inputs of the nine g_m stages (A11-A82) are connected to the corresponding nodes of the R-2R ladder network. For example, gm0 is connected to TAP0 (minimum attenuation), gm1 is connected to TAP1, and so on, with gm9 connected to TAP8 (maximum attenuation).

[0045] A multi-channel transconductance stage array is used to receive multiple sets of attenuated signals. The multi-channel transconductance stage array is composed of multiple transconductance amplifiers connected in parallel. The input terminal of each transconductance amplifier is electrically connected to an attenuation signal node of a multi-stage R-2R trapezoidal resistor network.

[0046] Specifically, the multi-channel transconductance stage array consists of nine transconductance amplifiers (gm0-gm9) connected in parallel. The output currents of the nine g_m stages are summed at the virtual ground node of the output amplifier (A100). By controlling the tail current distribution of these g_m stages, precise gain interpolation can be achieved between two adjacent R-2R attenuation nodes (i.e., a 6.02 dB step). To enhance the robustness of the system, each g_m stage (e.g., gm0) preferably employs a wide-swing folded cascode architecture.

[0047] More specifically, the 9-channel transconductance amplifier includes odd-numbered stages (gm1, gm3, gm5, gm7) and even-numbered stages (gm0, gm2, gm4, gm6, gm8). The tail current of all odd-numbered stages is connected to the same first current bus (I_A), and the tail current of even-numbered stages is connected to the second current bus (I_B). Independent current sinking for odd and even stages is achieved through separate first and second current buses.

[0048] In other words, when distributing current between two gated stages, the current bank actually redistributes the total current Itail between the I_A and I_B paths. For example, when gm0 (even) and gm1 (odd) are activated, if the LSB code increases, the logic control causes I_B (the current allocated to gm0) to gradually decrease, while I_A (the current allocated to gm1) to gradually increase.

[0049] The digital logic control module is used to receive a multi-bit digital gain control word and generate a gating signal and a control signal based on the multi-bit digital gain control word. The gating signal is used to select two adjacent transconductance amplifiers in the multi-channel transconductance stage array, ensuring that under any given digital gain control word, only the two adjacent transconductance amplifiers are in the active gating state. The control signal is used to distribute the current between the two selected adjacent transconductance amplifiers.

[0050] Specifically, the multi-bit digital gain control word is an 8-bit digital gain control word, which is divided into 3 high bits (MSB) and 5 low bits (LSB). The digital logic control module uses the 3 high bits (MSB) to decode and generate enable gating signals for nine transconductance amplifiers, ensuring that under any given digital gain control word, only two adjacent transconductance amplifiers are in the active gating state. The digital logic control module uses the 5 low bits (LSB) to decode and generate control signals to control the adjustable current bank, determine the distribution ratio d of the total tail current between the two active transconductance amplifiers, and distribute the total tail current between the two g_m stages according to the ratio d, thereby achieving linear interpolation within a 6.02 dB interval.

[0051] Specifically, the digital logic control module includes a 3-to-8 decoder and an LSB decoder. The 3-to-8 decoder is used to generate a strobe signal based on the 3 high-order bits, and the LSB decoder is used to generate a control signal based on the 5 low-order bits. The LSB decoder uses a Celsius decoder.

[0052] More specifically, high-order bit control (inter-stage gating): The 3 high-order bits are processed by a 3-to-8 decoder within the digital logic control module to generate enable signals for gating adjacent g_m stages. The digital logic control module generates 9 enable signals EN0 to EN8. Preferably, in any given control word state, only two adjacent g_m stages are gated and activated (EN_i and EN_i+1 are high), while the other 7 stages remain disabled, thereby significantly reducing power consumption.

[0053] Low-order control (current library interpolation): 5 low-order bits are used to control the precise gain step within a 6.02 dB increment. The digital logic control module includes a decoder for processing LSBs, preferably a Celsius decoder. This decoder controls an adjustable current consisting of 32 unit current sources. By controlling these 32 switches (SW1-SWN), the total tail current (Itail) can be distributed in d proportions to the two selected g_m levels. The minimum gain step achieved in this embodiment is approximately 6.02 dB / 32 ≈ 0.188 dB.

[0054] More specifically, the digital logic control module is also used to receive a direction selection signal (D-SEL), which is used to lock the switching logic to eliminate glitches in the output signal when a multi-bit digital gain control word jumps across regions.

[0055] An adjustable current bank is used to distribute the total tail current (Itail) to the two adjacent transconductance amplifiers selected based on a control signal.

[0056] Specifically, the adjustable current library consists of 32 unit current sources. The current library, composed of 32 current sources, is responsible for driving the activated g_m level tail current. The on or off state of the 32 unit current sources is controlled by the digital logic control module (i.e., 5-bit low-order decoding signal), so that linear interpolation adjustment is achieved within the equal decibel interval (6.02 dB) of the segmented attenuation network.

[0057] The output amplifier stage is used to summarize the output currents of all transconductance amplifiers through a feedback network and output the final linear decibel gain signal (VOUTP / VOUTN).

[0058] Specifically, the output amplification stage consists of a differential output amplifier (A100) and its feedback network (RA, RB). That is, the summed current is amplified by resistive feedback through the output amplification stage (A100) and the feedback network (RA, RB) to achieve the final voltage gain.

[0059] This embodiment provides a high-precision linear decibel programmable gain amplifier that can realize a glitch-free gain switching control method, especially solving the gain jump problem caused when the control word crosses the region boundary (such as when the high-order MSB changes).

[0060] Specifically, the glitch-free switching logic based on D-SEL is as follows:

[0061] When the digital gain control word jumps across adjacent regions (i.e., the MSB changes, requiring a switch of the g_m strobe pair), traditional control logic is prone to causing instantaneous fluctuations in the total transconductance. This embodiment utilizes a direction selection signal (D-SEL, generated by the digital logic control module to indicate whether the code is incrementing or decrementing) and a parity separation architecture to achieve glitch-free switching.

[0062] Taking the change of control code from 31 (region 0 boundary) to 32 (region 1 boundary) as an example, the specific implementation steps are as follows (see Figure 3 (Process Logic)

[0063] Step 1, State A (Code 31): The active gating pairs are gm0 (even) and gm1 (odd) (gated by EN0 and EN1). Code 31 means that the LSB is at full scale (thermometer code is all '1'), which means that almost all of the tail current Itail is allocated to path I_A, i.e., gm1 (odd), while the current gm0 (even) on I_B is close to zero.

[0064] Step 2, when the switch occurs (Code 31→32): Control code jump. The digital logic control module detects the D-SEL signal indicating an increase in the code. Since gm0 and gm1 are separately connected to I_B and I_A, and the current on I_B (the current of gm0) is close to zero, the digital logic control module safely turns off signal EN0 and simultaneously turns on signal EN2 (strobe gm2, odd).

[0065] Step 3, State B (Code 32): At this point, the active gating pair becomes gm1 (odd) and gm2 (even). Since the current has been smoothly and completely transferred to the I_A bus (gm2) in Code 31, and there is no significant current flowing through the I_B bus at the moment gm0 is turned off and gm2 is turned on, this transition of the inter-stage gating pair does not cause a sudden change or decrease in the total output current (i.e., the total gain), successfully eliminating glitches.

[0066] The above logic applies to switching between any adjacent regions. For example, when switching from Code 63 to 64, the transition from (gm1, gm2) to (gm2, gm3) is performed by using the moment when the current on the I_A bus (odd level) is close to zero to perform a glitch-free switch from EN1 to EN3, avoiding a large jump in the tail current at the moment of switching, thereby eliminating glitches in the output signal.

[0067] Please see Figure 4 Based on gain synthesis and experimental results, this PGA achieves a perfect linear decibel gain control line with an 8-bit control word (0-255). The total dynamic range covers 48 dB, and the measured precision gain step is approximately 0.188 dB. Simulations performed at different process corners and temperatures show a gain error of less than 0.05 dB, demonstrating the excellent performance of this embodiment.

[0068] This embodiment provides a high-precision linear decibel programmable gain amplifier, employing a segmented R-2R ladder network combined with a multi-g_m interpolation stage architecture. An 8-bit digital control word is used for adjustment, split into 3 high-order bits (MSB) and 5 low-order bits (LSB). The high-order bits are decoded to select two adjacent g_m amplification stages; the low-order bits are decoded using a Celsius decoder to control a current bank consisting of 32 unit current sources, proportionally distributing the tail current between the two selected g_m stages, thereby achieving precise gain interpolation. This embodiment further employs an architecture that separates the tail current paths for odd-numbered and even-numbered g_m stages, and combines this with a direction selection signal (D-SEL) to execute glitch-free switching logic during control code transitions. This embodiment achieves an extremely small gain step of approximately 0.188 dB and a dynamic range of 48 dB, with no glitches generated across the entire gain range, and the gain accuracy exhibits strong robustness to process, voltage, and temperature (PVT) fluctuations.

[0069] The high-precision linear decibel programmable gain amplifier provided in this embodiment has the following advantages:

[0070] 1. High-precision stepping: A minimum gain step of approximately 0.188 dB is achieved through 256-step adjustment.

[0071] 2. PVT insensitivity: Since the gain depends on the ratio parameter of the transconductance stage rather than the absolute resistance, the gain error of the system is small under different process angles and voltage fluctuations.

[0072] In summary, this embodiment replaces the traditional analog voltage control with a digitally controlled current ratio distribution method, so that the gain accuracy depends only on the ratio parameter of the transconductance stage, rather than the absolute device parameters or control voltage, thereby fundamentally eliminating the influence of process, voltage and temperature fluctuations on gain accuracy.

[0073] Example 2

[0074] This embodiment provides a high-precision linear decibel programmable gain control method, applied to a high-precision linear decibel programmable gain amplifier provided in Embodiment 1, including:

[0075] S1, Input and Splitting: Receives a multi-bit digital gain control word and splits it into high and low bits;

[0076] Specifically, it receives an 8-bit digital gain control word and splits it into 3 high-order bits (MSB) and 5 low-order bits (LSB).

[0077] S2, Interstage gating: After decoding the high-order bits, two adjacent transconductance amplifiers in the multi-channel transconductance stage array are gating and put into the active state;

[0078] Specifically, the 3 high-order bits are processed by 3-8 decoding to select two adjacent paths in the nine-channel transconductance amplifier stage (e.g.: and It enters the active state.

[0079] S3, Current Interpolation: The low-order bits are processed by decoding, and the adjustable current bank is controlled to determine the distribution ratio of the total tail current between the two selected transconductance amplifiers.

[0080] Specifically, the 5 lower bits are decoded to control a current pool consisting of 32 unit current sources, and the distribution ratio d of the total tail current (Itail) between the two selected transconductance amplifier stages is determined.

[0081] S4, Gain Synthesis: The two selected transconductance amplifiers weight the attenuation signals of different nodes in the segmented attenuation network according to the allocation ratio, and output the final linear decibel gain signal through the output amplification stage.

[0082] Specifically, the two activated transconductance amplifier stages perform weighted interpolation on the attenuation signals of different nodes in the R-2R network according to the allocation ratio d, and output a linear decibel gain signal after amplification by the output stage.

[0083] This embodiment provides a high-precision linear decibel programmable gain control method, which also includes glitch detection and handling: when a multi-bit digital gain control word jumps, it is determined whether it is at an inter-stage switching critical point; if it is at a critical point (e.g., jumping from "011111" to "100000"), then the glitch-free switching logic is executed using the direction selection signal (D-SEL), and the switching state is locked; if it is not at a critical point, the current current distribution is maintained. It should be noted that the glitch-free switching logic is achieved by maintaining the current stability on the odd-even stage buses I_A and I_B at the moment of switching.

[0084] In the high-precision linear decibel programmable gain control method provided in this embodiment, the total dynamic gain range A CL This is related to the selection of the current control proportional parameter d and the gm level. Here, d is the current distribution coefficient adjusted by the lower-order control word, ranging from 0 / 32 to 32 / 32.

[0085] For details on the implementation of a high-precision linear decibel programmable gain control method, please refer to the above description of a high-precision linear decibel programmable gain amplifier, which will not be repeated here.

[0086] The technical features of the above embodiments can be combined in any way (as long as there is no contradiction in the combination of these technical features). For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described; these embodiments not explicitly written should also be considered to be within the scope of this specification.

Claims

1. A high-precision linear decibel programmable gain amplifier, characterized in that, include: A segmented attenuation network is used to receive differential input signals and discretely attenuate the differential input signals into multiple sets of attenuated signals with equal decibel intervals. The segmented attenuation network is composed of a multi-stage R-2R trapezoidal resistor network; A multi-channel transconductance stage array is used to receive multiple sets of attenuated signals; the multi-channel transconductance stage array is composed of multiple transconductance amplifiers connected in parallel, and the input terminal of each transconductance amplifier is electrically connected to one attenuation signal node of the multi-stage R-2R trapezoidal resistor network; A digital logic control module is used to receive a multi-bit digital gain control word and generate a gating signal and a control signal according to the multi-bit digital gain control word; the gating signal is used to select two adjacent transconductance amplifiers in the multi-channel transconductance stage array to ensure that under any given digital gain control word, only two adjacent transconductance amplifiers are in the active gating state; the control signal is used to perform current distribution between the two selected adjacent transconductance amplifiers. An adjustable current bank is used to distribute the total tail current to the two adjacent selected transconductance amplifiers according to the control signal. The output amplifier stage is used to summarize the output currents of all transconductance amplifiers through a feedback network and output the final linear decibel gain signal.

2. The high-precision linear decibel programmable gain amplifier according to claim 1, characterized in that, The attenuation of each stage of the segmented attenuation network is 6.02 dB.

3. The high-precision linear decibel programmable gain amplifier according to claim 1, characterized in that, The multi-channel transconductance stage array is composed of 9 transconductance amplifiers connected in parallel, and each of the transconductance amplifiers adopts a wide-swing folded cascade architecture.

4. The high-precision linear decibel programmable gain amplifier according to claim 3, characterized in that, The 9-channel transconductance amplifier includes odd-numbered stages and even-numbered stages. The tail current of the odd-numbered stages is connected to the first current bus, and the tail current of the even-numbered stages is connected to the second current bus.

5. The high-precision linear decibel programmable gain amplifier according to claim 1, characterized in that, The multi-bit digital gain control word is an 8-bit digital gain control word, which is divided into 3 high bits and 5 low bits. The 3 high bits are used to generate the gating signal, and the 5 low bits are used to generate the control signal.

6. The high-precision linear decibel programmable gain amplifier according to claim 5, characterized in that, The digital logic control module includes a 3-to-8 decoder and an LSB decoder. The 3-to-8 decoder is used to generate the strobe signal based on the 3 high-order bits, and the LSB decoder is used to generate the control signal based on the 5 low-order bits. The LSB decoder is a Celsius decoder.

7. The high-precision linear decibel programmable gain amplifier according to claim 1, characterized in that, The adjustable current library includes 32 unit current sources. The on or off state of the 32 unit current sources is controlled by the digital logic control module, so that linear interpolation adjustment is achieved within the equal decibel intervals of the segmented attenuation network.

8. The high-precision linear decibel programmable gain amplifier according to claim 1, characterized in that, The digital logic control module is also used to receive a direction selection signal, which is used to lock the switching logic when the multi-bit digital gain control word jumps across regions, so as to eliminate glitches in the output signal.

9. A high-precision linear decibel programmable gain control method, characterized in that, The high-precision linear decibel programmable gain amplifier applied to any one of claims 1 to 8 comprises: Receives a multi-bit digital gain control word and splits it into high and low bits; After the high-order bits are decoded, two adjacent transconductance amplifiers in the multi-channel transconductance stage array are selected and activated. The low-order bits are decoded to control the adjustable current bank and determine the distribution ratio of the total tail current between the two selected transconductance amplifiers. The two selected transconductance amplifiers weight the attenuation signals of different nodes of the segmented attenuation network according to the allocation ratio, and output the final linear decibel gain signal through the output amplification stage.

10. The high-precision linear decibel programmable gain control method according to claim 9, characterized in that, Also includes: When the multi-digit gain control word jumps, determine whether it is at the inter-stage switching critical point; If it is at the critical point, the direction selection signal is used to execute the glitch-free switching logic and lock the switching state; If not at a critical point, the current current distribution is maintained.

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