Semiconductor device and method of manufacture, power module, power conversion circuit and vehicle

Abstract

The application discloses a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle, and belongs to the technical field of semiconductors. The semiconductor device comprises a semiconductor body comprising a first surface and a second surface oppositely arranged in a thickness direction; the semiconductor body is provided with a groove extending from the first surface into the semiconductor body, and the semiconductor body further comprises a JTE region and a first region with opposite conductive types, the JTE region covers the sidewall and the bottom of the groove, and the first region is located at the bottom of the groove and is arranged in a spaced manner with the JTE region; the first region comprises multiple sub-regions which are sequentially distributed and connected in the thickness direction, and the doping concentration of the multiple sub-regions gradually increases in the direction from the first surface to the second surface; and a dielectric layer is filled in the groove. The application can reduce the local field intensity, improve the breakdown voltage of the device, and thus improve the reliability of the device.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and particularly relates to a semiconductor device and its preparation method, a power module, a power conversion circuit, and a vehicle. Background Technology

[0002] SiC MOSFETs (Silicon Carbide Metal-Oxide-Semiconductor Field-Effect Transistors) have evolved from planar to trench types. By improving the gate structure, the current flow direction on the gate changed from planar to vertical. However, SiC MOSFETs in related technologies have electric field spikes at the terminals, making the devices prone to breakdown and affecting their reliability. Summary of the Invention

[0003] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a semiconductor device and its fabrication method, a power module, a power conversion circuit, and a vehicle, which can reduce local field strength, increase the breakdown voltage of the device, and thus improve the reliability of the device.

[0004] In a first aspect, this application provides a semiconductor device, comprising: A semiconductor body includes a first surface and a second surface disposed opposite to each other in the thickness direction; the semiconductor body has a trench extending from the first surface into the semiconductor body, and the semiconductor body also includes a JTE region and a first region with opposite conductivity types, the JTE region covering the sidewalls and bottom of the trench, the first region being located at the bottom of the trench and spaced apart from the JTE region; the first region includes a multi-level sub-regions distributed and connected sequentially along the thickness direction, and the doping concentration of the multi-level sub-regions gradually increases in the direction from the first surface to the second surface; A dielectric layer is filled in the trench.

[0005] According to the semiconductor device of this application, a trench extending from a first surface into the semiconductor body is formed in the semiconductor body, and a first region is formed in the semiconductor body at the bottom of the trench. The first region includes a multi-level sub-region that is distributed and connected sequentially along the thickness direction. In the direction from the first surface to the second surface, the doping concentration of the multi-level sub-region gradually increases, forming a longitudinal (i.e., thickness direction) conductive path. The electric field gradually decreases along the longitudinal direction, avoiding excessively high local field strength and improving the breakdown voltage of the device. In addition, the trench is filled with a dielectric layer, and the sidewalls and bottom of the trench are covered with JTE regions, further reducing the local field strength and further improving the breakdown voltage, thereby improving the reliability of the device.

[0006] According to one embodiment of this application, the multi-level sub-regions are distributed in a stepped manner, and the width of the multi-level sub-regions gradually decreases in the direction from the first surface to the second surface.

[0007] According to one embodiment of this application, the trench includes a series of interconnected sub-trenches distributed in a stepped manner along the depth direction, wherein the width of the series of sub-trenches gradually decreases in the direction from the first surface to the second surface. The JTE region covers the sidewalls and bottom of the multi-level sub-trench, and the dielectric layer fills the multi-level sub-trench, forming a stepped structure.

[0008] According to one embodiment of this application, the depth of the multi-level sub-trenches gradually decreases in the direction from the first surface to the second surface.

[0009] According to one embodiment of this application, the number of levels of the multi-level sub-region is the same as the number of levels of the multi-level sub-trench.

[0010] According to one embodiment of this application, the multi-level sub-region includes a first-level sub-region to an Nth-level sub-region with gradually increasing doping concentration, and the semiconductor body also includes a multi-level scattering region with the same conductivity type as the first region, the multi-level scattering region including a first-level scattering region to an Nth-level scattering region with gradually increasing doping concentration; The first-level scattering region encompasses the JTE region and the first-level sub-region, and the nth-level scattering region encompasses the (n-1)th-level scattering region and the nth-level sub-region, where 2 ≤ n ≤ N.

[0011] According to one embodiment of this application, the doping concentration of the i-th order scattering region is less than the doping concentration of the i-th order sub-region, 1≤i≤N.

[0012] According to one embodiment of this application, the semiconductor body further includes a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer sequentially distributed between the second surface and the first surface. The JTE region, the second epitaxial layer, and the third epitaxial layer have the same conductivity type, which is opposite to the conductivity type of the first epitaxial layer and the first region. The doping concentration of the second epitaxial layer is greater than that of the third epitaxial layer. The trench extends from the first surface into the third epitaxial layer, and the first region is located in the third epitaxial layer and the second epitaxial layer, or the first region is located in the second epitaxial layer; or, The trench extends from the first surface into the second epitaxial layer, and the first region is located in the second epitaxial layer.

[0013] According to one embodiment of this application, the semiconductor body further includes a plurality of epitaxial pillars spaced apart, the epitaxial pillars having a conductivity type opposite to that of the first epitaxial layer; The epitaxial pillar extends from the surface of the first epitaxial layer near the second epitaxial layer into the first epitaxial layer, or the epitaxial pillar penetrates the first epitaxial layer.

[0014] According to one embodiment of this application, the semiconductor body is provided with a plurality of trenches, the sidewalls and bottom of each trench are covered with the JTE region, and each trench is filled with the dielectric layer; the semiconductor body includes a plurality of first regions, and the plurality of first regions are respectively located at the bottom of the plurality of JTE trenches; In the direction toward the edge of the semiconductor body, a plurality of trenches are spaced apart, the width and / or depth of the plurality of trenches gradually increase, and / or the width and / or thickness of the plurality of first regions gradually increase.

[0015] According to one embodiment of this application, the spacing between adjacent trenches is the same.

[0016] According to one embodiment of this application, the semiconductor device further includes: A field oxide layer is located on the first surface of the semiconductor body.

[0017] Secondly, this application provides a method for fabricating a semiconductor device, the method comprising: A semiconductor body is provided, the semiconductor body including a first surface and a second surface disposed opposite to each other in the thickness direction; A trench is formed extending from the first surface into the semiconductor body, and a first region is formed in the semiconductor body at the bottom of the trench; the first region includes a multi-level sub-region that is sequentially distributed and connected along the thickness direction, and the doping concentration of the multi-level sub-region gradually increases in the direction from the first surface to the second surface; A JTE region is formed in the semiconductor body, covering the sidewalls and bottom of the trench. The JTE region is spaced apart from the first region and has the opposite conductivity type to the first region. A medium layer is filled into the trench.

[0018] According to one embodiment of this application, the multi-level sub-region includes a first-level sub-region to an Nth-level sub-region with gradually increasing doping concentration, and the trench includes a multi-level sub-trench, which includes a first-level sub-trench to an Nth-level sub-trench. The formation of a trench extending from the first surface into the semiconductor body, and the formation of a first region in the semiconductor body at the bottom of the trench, includes: A first mask layer having a first opening is formed on the first surface; A first-level sub-trench is formed through the first opening, extending from the first surface into the semiconductor body. A first-level sub-region is formed in the semiconductor body at the bottom of the first-level sub-trench; An nth mask layer with an nth opening is formed on the surface of the (n-1)th level sub-trench, the nth opening exposing the bottom surface of the (n-1)th level sub-trench; 2≤n≤N; An nth sub-trench is formed through the nth opening, extending from the bottom surface of the (n-1)th sub-trench into the semiconductor body. The nth sub-region is formed in the semiconductor body at the bottom of the (n-1)th sub-region through the nth sub-trench, and the nth sub-region is connected to the (n-1)th sub-region. Remove the second mask layer up to the Nth mask layer.

[0019] According to one embodiment of this application, forming a JTE region covering the sidewalls and bottom of the trench in the semiconductor body includes: The first mask layer around the first opening is etched to enlarge the first opening into the target opening; The semiconductor body on the sidewalls and bottom of the multi-level sub-trench is doped through the target opening to form the JTE region; Remove the first mask layer.

[0020] Thirdly, this application provides a power module including a substrate and a semiconductor device as described in the first aspect above, wherein the substrate is used to support the semiconductor device.

[0021] Fourthly, this application provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and a semiconductor device as described in the first aspect above, the semiconductor device being electrically connected to the circuit board.

[0022] Fifthly, this application provides a vehicle including a load and a power conversion circuit as described in the fourth aspect above, the power conversion circuit being used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the converted direct current to the load.

[0023] The above-described one or more technical solutions in the embodiments of this application have at least one of the following technical effects: By setting a trench extending from the first surface into the semiconductor body, and setting a first region in the semiconductor body at the bottom of the trench, the first region includes a multi-level sub-region that is sequentially distributed and connected along the thickness direction. In the direction from the first surface to the second surface, the doping concentration of the multi-level sub-region gradually increases, forming a longitudinal (i.e., thickness direction) conductive path. The electric field gradually decreases along the longitudinal direction, avoiding excessively high local field strength and improving the breakdown voltage of the device. In addition, the trench is filled with a dielectric layer, and the sidewalls and bottom of the trench are covered with JTE regions, which further reduces the local field strength, further improves the breakdown voltage, and improves the reliability of the device.

[0024] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0025] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is one of the schematic diagrams of the semiconductor device provided in the embodiments of this application; Figure 2 This is a top view of the semiconductor device provided in the embodiments of this application; Figure 3 This is a second schematic diagram of the structure of the semiconductor device provided in the embodiments of this application; Figure 4 This is the third schematic diagram of the semiconductor device provided in the embodiments of this application; Figure 5 This is the fourth schematic diagram of the semiconductor device provided in the embodiments of this application; Figure 6 This is a schematic flowchart of the method for fabricating a semiconductor device provided in an embodiment of this application; Figure 7 This is one of the structural schematic diagrams in the method for fabricating a semiconductor device provided in the embodiments of this application; Figure 8 This is a second schematic diagram of the structure in the method for fabricating a semiconductor device provided in the embodiments of this application; Figure 9 This is the third schematic diagram of the structure in the method for fabricating the semiconductor device provided in the embodiments of this application; Figure 10 This is the fourth schematic diagram of the structure in the method for fabricating the semiconductor device provided in the embodiments of this application; Figure 11 This is the fifth schematic diagram of the structure in the method for fabricating the semiconductor device provided in the embodiments of this application; Figure 12 This is the sixth schematic diagram of the structure in the method for fabricating the semiconductor device provided in the embodiments of this application; Figure 13 This is the seventh schematic diagram of the structure in the method for fabricating the semiconductor device provided in the embodiments of this application; Figure 14 This is the eighth schematic diagram of the structure in the method for fabricating a semiconductor device provided in the embodiments of this application; Figure 15 This is the ninth schematic diagram of the structure in the method for fabricating the semiconductor device provided in the embodiments of this application; Figure 16 This is the tenth schematic diagram of the structure in the method for fabricating the semiconductor device provided in the embodiments of this application; Figure 17 This is eleventh of the structural schematic diagrams in the method for fabricating a semiconductor device provided in the embodiments of this application. Detailed Implementation

[0026] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0027] The following description, with reference to the accompanying drawings, describes the semiconductor device and its fabrication method, power module, power conversion circuit, and vehicle provided in embodiments of this application.

[0028] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application. The semiconductor device may be a MOSFET semiconductor device.

[0029] like Figure 1 As shown, the semiconductor device provided in this application embodiment includes a semiconductor body 1.

[0030] The semiconductor body 1 may include a substrate 10 and an epitaxial layer 11, wherein the epitaxial layer 11 is located on one side of the thickness direction X of the substrate 10. The epitaxial layer 11 may include a stacked structure formed by multiple film layers. Figure 1 The epitaxial layer 11 shown includes three film layers stacked sequentially, namely the first epitaxial layer 111, the second epitaxial layer 112, and the third epitaxial layer 113.

[0031] The material of the substrate 10 and the epitaxial layer 11 can be the same or different. In some embodiments, both the epitaxial layer 11 and the substrate 10 can be made of SiC. SiC has excellent physical and electrical properties. Compared with silicon, SiC has a larger bandgap and advantages such as high breakdown electric field, high thermal conductivity, high electron saturation velocity, and strong radiation resistance. Therefore, semiconductor devices made of SiC can not only operate stably at higher temperatures, but are also suitable for high-voltage and high-frequency applications.

[0032] The semiconductor body 1 includes a first surface S1 and a second surface S2 disposed opposite to each other along the thickness direction X. When the semiconductor body 1 includes a substrate 10 and an epitaxial layer 11, the second surface S2 is the surface of the substrate 10 away from the epitaxial layer 11, and the first surface S1 is the surface of the epitaxial layer 11 away from the substrate 10. Figure 1 The second surface S2 shown is the bottom surface of the semiconductor body 1, and the first surface S1 is the top surface of the semiconductor body 1.

[0033] The substrate 10 has a first conductivity type, which can be either N-type or P-type. The substrate 10 can be doped with N-type dopant ions to form an N-type substrate; these N-type dopant ions can include P (phosphorus) or N (nitrogen) ions, etc. The substrate 10 can also be doped with P-type dopant ions to form a P-type substrate; these P-type dopant ions can include Al (aluminum) or B (boron) ions, etc. When the epitaxial layer 11 comprises multiple layers, the conductivity types of the multiple layers can be the same or opposite. Figure 1 The first epitaxial layer 111 shown has a first conductivity type, and the second epitaxial layer 112 and the third epitaxial layer 113 have a second conductivity type, which is the opposite of the first conductivity type.

[0034] Combination Figure 2 As shown, the semiconductor device includes an active region A and a termination region B surrounding the active region A. The semiconductor device also includes a main junction region C, which surrounds the active region A, and the termination region B surrounds the main junction region C.

[0035] The semiconductor body 1 has a trench 12 extending from the first surface S1 into the semiconductor body 1. The trench 12 may be located in the termination region B. The semiconductor body also includes a JTE (junction termination extension) region 13 and a first region 15 with opposite conductivity types. The JTE region 13 covers the sidewalls and bottom of the trench 12, thus enclosing the trench 12. The first region 15 is located at the bottom of the trench 12 and is spaced apart from the JTE region 13, i.e., the first region 15 is located at the bottom of the JTE region 13.

[0036] In this context, the JTE region has a second conductivity type, and the first region 15 has a first conductivity type. For example, substrate 10 is an N-type substrate, JTE region 13 is a P-type doped region, and the first region 15 is an N-type doped region.

[0037] The first region 15 includes a multi-level sub-region that is sequentially distributed and connected along the thickness direction X. The doping concentration of the multi-level sub-region gradually increases in the direction from the first surface S1 to the second surface S2.

[0038] As an example, the first region 15 includes three interconnected sub-regions (i.e., first-level sub-region 151, second-level sub-region 152, and third-level sub-region 153) arranged in a stepped manner along the thickness direction X. The second-level sub-region 152 is located at the bottom of the first-level sub-region 151 and is connected to it, and the third-level sub-region 153 is located at the bottom of the second-level sub-region 152 and is connected to it. The doping concentration of the first-level sub-region 151, the second-level sub-region 152, and the third-level sub-region 153 gradually increases, making the first region 15 a gradient doped region.

[0039] It should be noted that Zone 15 can also include two or more sub-zones. The number of sub-zones can be set according to actual needs, and no specific limit is made here.

[0040] The semiconductor device also includes a dielectric layer 2 that fills the trench 12. In some embodiments, the dielectric layer 2 is made of materials such as silicon oxide or undoped polysilicon.

[0041] In this embodiment, the first region 15 includes a multi-level sub-region that is sequentially distributed and connected along the thickness direction X. From the first surface S1 to the second surface S2, the doping concentration of the multi-level sub-regions gradually increases, forming a longitudinal (i.e., thickness direction X) conductive path. The electric field gradually decreases along the longitudinal direction, avoiding excessively high local field strength and improving the device's breakdown voltage. Furthermore, the trench 12 is filled with a dielectric layer 2, and the sidewalls and bottom of the trench 12 are covered with JTE regions 13, further reducing the local field strength and further improving the breakdown voltage, thus enhancing the device's reliability. Moreover, after forming the trench 12 in this embodiment, low-energy ion implantation can be used to form JTE regions 13 on the sidewalls and bottom of the trench 12, reducing the risk of terminal lattice damage and further improving the device's reliability.

[0042] The semiconductor body 1 includes a second region 14 extending from the first surface S1 into the semiconductor body 1. The second region 14 may be located in the main junction region C. When the semiconductor body 1 includes a first epitaxial layer 111, a second epitaxial layer 112, and a third epitaxial layer 113, the second region 14 extends from the first surface S1 into the second epitaxial layer 112. The conductivity type of the second region 14 is a second conductivity type.

[0043] The semiconductor device may also include a source electrode 3. The source electrode 3 is located on the first surface S1 and is connected to the second region 14. The material of the source electrode 3 may include metals such as aluminum, copper, and nickel.

[0044] The semiconductor device may also include a drain 4, which is located on the second surface S2 of the semiconductor body 1. The material of the drain 4 may include metals such as aluminum, copper, and nickel.

[0045] In some embodiments, the multi-level sub-regions are distributed in a stepped manner, with the width of the multi-level sub-regions gradually decreasing in the direction from the first surface S1 to the second surface S2. The width of the multi-level sub-region refers to its dimension in the transverse direction (perpendicular to the thickness direction). The thickness of the multi-level sub-regions may be the same or different, and this is not specifically limited here.

[0046] The first region 15 includes three levels of sub-regions (i.e., first-level sub-region 151, second-level sub-region 152, and third-level sub-region 153) that are distributed and connected in a stepped manner along the thickness direction X. The widths of the first-level sub-region 151, the second-level sub-region 152, and the third-level sub-region 153 gradually decrease, so that the first region 15 forms a stepped structure, that is, the sidewalls of the first region 15 are stepped.

[0047] In this embodiment, the first region 15 is distributed in a stepped manner, which further reduces the electric field concentration and further improves the device breakdown voltage.

[0048] In some embodiments, the trench 12 includes a series of interconnected sub-trenches distributed in a stepped manner along the depth direction (i.e., the thickness direction X), with the width of the sub-trenches gradually decreasing from the first surface S1 to the second surface S2. The width of the sub-trench refers to its lateral dimension. The JTE region 13 covers the sidewalls and bottom of the sub-trenches, and the dielectric layer 2 fills the sub-trenches, forming a stepped structure.

[0049] As an example, the trench 12 includes three interconnected sub-trenches (i.e., first-level sub-trench 121, second-level sub-trench 122, and third-level sub-trench 123) that are distributed in a stepped manner along the thickness direction X. The first-level sub-trench 121 extends from the first surface S1 into the semiconductor body 1, the second-level sub-trench 122 extends from the bottom surface of the first-level sub-trench 121 into the semiconductor body 1, and the third-level sub-trench 123 extends from the bottom surface of the second-level sub-trench 122 into the semiconductor body 1. The widths of the first-level sub-trench 121, the second-level sub-trench 122, and the third-level sub-trench 123 gradually decrease, so that the trench 12 constitutes a stepped trench, that is, the sidewalls of the trench 12 are stepped.

[0050] It should be noted that trench 12 may also include two-level or three-level or more sub-trenches. The number of sub-trenches can be set according to actual needs, and no specific limitation is made here.

[0051] JTE region 13 covers the sidewalls and bottom of the multi-level sub-trench, thus enclosing the multi-level sub-trench. The inner surface of JTE region 13 (i.e., the surface of JTE region 13 near trench 12) is stepped, and the outer surface of JTE region 13 (i.e., the surface of JTE region 13 away from trench 12) can also be stepped. The conductivity type of JTE region 13 is the second conductivity type.

[0052] As an example, the multi-level sub-trench of trench 12 includes a first-level sub-trench 121, a second-level sub-trench 122 and a third-level sub-trench 123, and the JTE region 13 covers the sidewalls and bottom of the first-level sub-trench 121, the sidewalls and bottom of the second-level sub-trench 122 and the sidewalls and bottom of the third-level sub-trench 123.

[0053] The dielectric layer 2 is filled in a multi-level sub-trench, forming a stepped structure. Because the multi-level sub-trench is distributed in a stepped manner along the thickness direction X, the dielectric layer 2 is also distributed in a stepped manner along the thickness direction X. That is, the dielectric layer 2 includes multiple dielectric sub-layers that are distributed in a stepped manner along the thickness direction X and are connected, with one dielectric sub-layer filling each level of the sub-trench. The width of the multiple dielectric sub-layers gradually decreases in the direction from the first surface S1 to the second surface S2.

[0054] As an example, dielectric layer 2 includes a first dielectric sublayer, a second dielectric sublayer, and a third dielectric sublayer. The third dielectric sublayer fills a third-level sub-trench 123, the second dielectric sublayer fills a second-level sub-trench 122, and the first dielectric sublayer fills a first-level sub-trench 121. The widths of the first, second, and third dielectric sublayers gradually decrease to form a stepped structure, i.e., the sidewalls of dielectric layer 2 are stepped.

[0055] In this embodiment, the dielectric layer 2 fills the multi-level sub-trench, forming a stepped structure. Furthermore, the width of the multiple dielectric sub-layers gradually decreases along the direction from the first surface S1 to the second surface S2, providing multi-level electric field mitigation, further reducing local electric field concentration, and further improving the breakdown voltage. Moreover, the JTE region 13 covers the sidewalls and bottom of the multi-level sub-trench, enhancing the longitudinal extension of the depletion region, reducing local field strength, further improving the breakdown voltage, and enhancing the reliability of the device.

[0056] In some embodiments, the depth of the multi-level sub-trench gradually decreases in the direction from the first surface S1 to the second surface S2. The depth of the multi-level sub-trench refers to its dimension in the thickness direction X. The dielectric layer 2 includes multiple dielectric sub-layers, each corresponding to and filling one of the multi-level sub-trenches. The thickness of the multiple dielectric sub-layers gradually decreases in the direction from the first surface S1 to the second surface S2.

[0057] As an example, the multi-level sub-trench includes a first-level sub-trench 121, a second-level sub-trench 122, and a third-level sub-trench 123, with the depths of the first-level sub-trench 121, the second-level sub-trench 122, and the third-level sub-trench 123 gradually decreasing. Correspondingly, the dielectric layer 2 includes a first dielectric sublayer, a second dielectric sublayer, and a third dielectric sublayer, with the thicknesses of the first dielectric sublayer, the second dielectric sublayer, and the third dielectric sublayer gradually decreasing.

[0058] In this embodiment, the depth variation of the multi-level sub-trenches causes the thickness of the multiple dielectric sub-layers of dielectric layer 2 to gradually decrease in the direction from the first surface S1 to the second surface S2, further reducing local electric field concentration and improving breakdown voltage.

[0059] In some embodiments, the number of levels in the multi-level sub-region is the same as the number of levels in the multi-level sub-trench. Each level of sub-trench corresponds to the formation of a sub-region. The width of each sub-region can be greater than the width of the corresponding level of sub-trench.

[0060] As an example, after forming the first-level sub-groove 121, a corresponding first-level sub-region 151 is formed, and the width of the first-level sub-region 151 can be greater than the width of the first-level sub-groove 121; after forming the second-level sub-groove 122, a corresponding second-level sub-region 152 is formed, and the width of the second-level sub-region 152 can be greater than the width of the second-level sub-groove 122; after forming the third-level sub-groove 123, a corresponding third-level sub-region 153 is formed, and the width of the third-level sub-region 153 can be greater than the width of the third-level sub-groove 123.

[0061] In some embodiments, the semiconductor body further includes a scattering region that covers the JTE region 13 and the first region 15. The scattering region has the same conductivity type as the first region 15, and the doping concentration of the scattering region is lower than that of the first region 15.

[0062] This embodiment sets up a scattering region to further reduce the local field strength and increase the breakdown voltage.

[0063] In some embodiments, the multi-level sub-regions include first-level sub-regions to Nth-level sub-regions with gradually increasing doping concentrations. The semiconductor body 1 also includes a multi-level scattering region with the same conductivity type as the first region 15, comprising first-level scattering regions to Nth-level scattering regions with gradually increasing doping concentrations. The first-level scattering region covers the JTE region 13 and the first-level sub-region, and the nth-level scattering region covers the (n-1)th-level scattering region and the nth-level sub-region, where 2 ≤ n ≤ N.

[0064] The number of levels in the scattering region is the same as the number of levels in the multi-level sub-regions. Each level of sub-region forms a corresponding level of scattering region. The multi-level scattering regions are distributed sequentially from the inside out, and the doping concentration of the multi-level scattering regions gradually increases from the inside out.

[0065] As an example, N=3, such as Figure 3As shown, the multi-level sub-regions include a first-level sub-region 151, a second-level sub-region 152, and a third-level sub-region 153 with gradually increasing doping concentrations. The multi-level scattering region includes a first-level scattering region 171, a second-level scattering region 172, and a third-level scattering region 173 with gradually increasing doping concentrations. The first-level scattering region 171 encloses the JTE region 13 and the first-level sub-region 151. The second-level scattering region 172 encloses the first-level scattering region 171 and the second-level sub-region 152. The third-level scattering region 173 encloses the second-level scattering region 172 and the third-level sub-region 153.

[0066] In this embodiment, the multi-level scattering region constitutes a scattering gradient doping, which further reduces the local field strength and increases the breakdown voltage.

[0067] In some embodiments, the doping concentration of the i-th order scattering region is less than the doping concentration of the i-th order sub-region, where 1 ≤ i ≤ N. Simultaneously with the formation of the i-th order sub-region, scattering forms the i-th order scattering region, such that the doping concentration of the i-th order scattering region is less than the doping concentration of the i-th order sub-region.

[0068] As an example, the doping concentration of the first-level scattering region 171 is less than the doping concentration of the first-level sub-region 151, the doping concentration of the second-level scattering region 172 is less than the doping concentration of the second-level sub-region 152, and the doping concentration of the third-level scattering region 173 is less than the doping concentration of the third-level sub-region 153.

[0069] In some embodiments, combined with Figure 2 As shown, trench 12 is disposed around active region A, and trench 12 can be a continuous trench disposed around active region A. The dielectric layer 2 filling trench 12 is disposed around active region A, and JTE region 13 covering trench 12 is disposed around active region A, with JTE region 13 spaced apart from active region A. First region 15 is disposed around active region A, and first region 15 can be a continuous doped region disposed around active region A, with first region 15 spaced apart from active region A.

[0070] In some embodiments, the semiconductor body 1 has a plurality of trenches 12, and the sidewalls and bottom of each trench 12 are covered with JTE regions 13, that is, the semiconductor body 1 includes a plurality of JTE regions 13, and the plurality of JTE regions 13 respectively cover the plurality of trenches 12. Each trench 12 is filled with a dielectric layer 2. The plurality of trenches 12 are spaced apart in the direction toward the edge of the semiconductor body 1 (i.e., the direction from the active region A to the terminal region B). Figure 2 As shown, each trench 12 is arranged around the active region A, and multiple trenches 12 are distributed at intervals from the inside to the outside.

[0071] It should be noted that the number of grooves 12 can be set according to actual needs, and no specific limit is made here.

[0072] In some embodiments, the multiple trenches 12 have the same structure, that is, the width and depth of the multiple trenches 12 are the same. The dielectric layer 2 filling the multiple trenches 12 has the same structure, and the JTE region covering the multiple trenches 12 can have the same structure.

[0073] In some embodiments, the width and / or depth of the plurality of trenches 12 gradually increase in the direction toward the edge of the semiconductor body 1. When the trenches 12 include multi-level sub-trenches, the number of sub-trench levels of the plurality of trenches 12 is the same. In the direction toward the edge of the semiconductor body 1, the width and / or depth of the sub-trenches of the same level in the plurality of trenches 12 gradually increase. In the direction toward the edge of the semiconductor body 1, the width and / or thickness of the dielectric layer 2 filling the plurality of trenches 12 gradually increase, and the overall width and / or overall thickness of the JTE region covering the plurality of trenches 12 gradually increases.

[0074] In some embodiments, the semiconductor body 1 includes a plurality of first regions 15, each corresponding to the bottom of a plurality of trenches 12, and the plurality of first regions 15 are spaced apart from their corresponding JTE regions 13. The number of first regions 15 may be the same as the number of trenches 12, and the plurality of first regions 15 are spaced apart in the direction toward the edge of the semiconductor body 1. Each first region 15 is disposed around the active region A, and the plurality of first regions 15 are spaced apart from the inside to the outside.

[0075] In some embodiments, the multiple first regions 15 have the same structure, that is, the width and thickness of the multiple first regions 15 are the same.

[0076] In some embodiments, the width and / or thickness of the plurality of first regions 15 gradually increase in the direction toward the edge of the semiconductor body 1. The plurality of first regions 15 have the same number of sub-regions, and the width and / or thickness of the sub-regions of the same number of sub-regions of the plurality of first regions 15 gradually increase in the direction toward the edge of the semiconductor body 1.

[0077] In some embodiments, the spacing between adjacent trenches 12 is the same, and the spacing between adjacent dielectric layers 2 is the same.

[0078] In some embodiments, the spacing between adjacent first regions 15 is the same.

[0079] In some embodiments, the semiconductor device further includes a field oxide layer 5, which is located on the first surface S1 of the semiconductor body 1. The field oxide layer 5 covers the termination region B. The material of the field oxide layer 5 may include silicon oxide, such as SiO2.

[0080] In some embodiments, the semiconductor device further includes an interlayer dielectric layer 6, which covers the field oxide layer 5. The material of the interlayer dielectric layer 6 may include silicon oxide, silicon nitride, etc.

[0081] In some embodiments, the semiconductor body 1 further includes a first epitaxial layer 111, a second epitaxial layer 112, and a third epitaxial layer 113 sequentially distributed between the second surface S2 and the first surface S1, i.e., the epitaxial layer 11 includes the first epitaxial layer 111, the second epitaxial layer 112, and the third epitaxial layer 113. The first epitaxial layer 111 is located on one side of the substrate 10 in the thickness direction X, the second epitaxial layer 112 is located on the side of the first epitaxial layer 111 opposite to the substrate 10, and the third epitaxial layer 113 is located on the side of the second epitaxial layer 112 opposite to the first epitaxial layer 111. The surface of the third epitaxial layer 113 opposite to the second epitaxial layer 112 is the first surface S1, and the surface of the substrate 10 opposite to the first epitaxial layer 111 is the second surface S2.

[0082] The JTE region 13, the second epitaxial layer 112, and the third epitaxial layer 113 have the same conductivity type, which is opposite to that of the first epitaxial layer 111 and the first region 15. The doping concentration of the second epitaxial layer 112 is greater than that of the third epitaxial layer 113. That is, the JTE region 13, the second epitaxial layer 112, and the third epitaxial layer 113 all have the first conductivity type, while the first epitaxial layer 111 and the first region 15 all have the second conductivity type.

[0083] As an example, substrate 10 is an N-type substrate, JTE region 13 is a P-type doped region, and first region 15 is an N-type doped region. First epitaxial layer 111 is an N-type epitaxial layer, which can serve as a drift region to provide high resistivity to withstand high voltage. Second epitaxial layer 112 and third epitaxial layer 113 are both P-type epitaxial layers; for example, second epitaxial layer 112 is a P+ epitaxial layer, and third epitaxial layer 113 is a P- epitaxial layer.

[0084] In this embodiment, the epitaxial layer 11 forms a PPN structure, which helps the depletion region to extend longitudinally, further reducing the electric field peak and improving the breakdown voltage.

[0085] In some embodiments, the trench 12 extends from the first surface S1 into the third epitaxial layer 113, i.e., the trench 12 is located in the third epitaxial layer 113. The first region 15 is located in the third epitaxial layer 113 and the second epitaxial layer 112, or the first region 15 is located in the second epitaxial layer 112. For example... Figure 1 As shown, the first-level sub-region 151 of the first region 15 is located at the junction of the third epitaxial layer 113 and the second epitaxial layer 112, while the second-level sub-region 152 and the third-level sub-region 153 are located in the second epitaxial layer 112.

[0086] In some embodiments, the trench 12 extends from the first surface S1 into the second epitaxial layer 112, that is, the trench 12 penetrates the third epitaxial layer 113 and extends into the second epitaxial layer 112, meaning the trench 12 can be located in the third epitaxial layer 113 and the second epitaxial layer 112. The first region 15 is located in the second epitaxial layer 112.

[0087] In this embodiment, the epitaxial layer 11 forms a PPN structure, which works synergistically with the gradient doping of the first region 15 to continuously extend the depletion region from the first surface S1 to the first epitaxial layer 111, further reducing the peak electric field and improving the device breakdown voltage.

[0088] In some embodiments, such as Figure 4 and Figure 5 As shown, the semiconductor body 1 also includes a plurality of epitaxial pillars 16 spaced apart. The epitaxial pillars 16 are located in the first epitaxial layer 111. The conductivity type of the epitaxial pillars 16 is opposite to that of the first epitaxial layer 111, that is, the conductivity type of the epitaxial pillars 16 is the second conductivity type.

[0089] As an example, the first epitaxial layer 111 is an N-type epitaxial layer, and the epitaxial pillar 16 is a P-pillar.

[0090] In some embodiments, such as Figure 4 As shown, the epitaxial pillar 16 can extend from the surface of the first epitaxial layer 111 near the second epitaxial layer 112 into the first epitaxial layer 111. The height of the epitaxial pillar 16 is less than the thickness of the first epitaxial layer 111. The epitaxial pillar 16 and the first epitaxial layer 111 form a semi-superjunction structure, enabling the semiconductor device to be used in a semi-superjunction device.

[0091] In some embodiments, such as Figure 5 As shown, the epitaxial pillar 16 penetrates the first epitaxial layer 111. The height of the epitaxial pillar 16 is equal to the thickness of the first epitaxial layer 111. The epitaxial pillar 16 and the first epitaxial layer 111 constitute a superjunction structure, enabling the semiconductor device to be used in a superjunction device.

[0092] According to the semiconductor device provided in the embodiments of this application, a trench 12 extending from the first surface S1 into the semiconductor body 1 is formed in the semiconductor body 1. A first region 15 is formed in the semiconductor body 1 at the bottom of the trench 12. The first region 15 includes a multi-level sub-regions that are sequentially distributed and connected along the thickness direction X. In the direction from the first surface S1 to the second surface S2, the doping concentration of the multi-level sub-regions gradually increases, forming a longitudinal (i.e., thickness direction X) conductive path. The electric field gradually decreases along the longitudinal direction, avoiding excessively high local field strength and improving the breakdown voltage of the device. Furthermore, the trench 12 is filled with a dielectric layer 2, and the sidewalls and bottom of the trench 12 are covered with JTE regions 13, further reducing the local field strength and further improving the breakdown voltage, thereby improving the reliability of the device. Moreover, after the trench 12 is formed, low-energy ion implantation can be used to form JTE regions 13 on the sidewalls and bottom of the trench 12, reducing the risk of terminal lattice damage and further improving the reliability of the device.

[0093] Accordingly, this application also provides a method for fabricating a semiconductor device.

[0094] Figure 6 This is a schematic flowchart illustrating the method for fabricating a semiconductor device provided in an embodiment of this application.

[0095] like Figure 6 As shown, the method for fabricating a semiconductor device provided in this application includes steps S110 to S140.

[0096] Step S110: Provide a semiconductor body, the semiconductor body including a first surface and a second surface disposed opposite to each other in the thickness direction.

[0097] In some embodiments, combined with Figure 7 As shown, the semiconductor body 1 may include a substrate 10 and a semiconductor epitaxial layer 11. First, a substrate 10 is provided, and then a semiconductor epitaxial layer 11 is formed on one side of the substrate 10 in the thickness direction X by means of vapor phase epitaxy, liquid phase epitaxy, or solid phase epitaxy. The material of the substrate 10 and the material of the semiconductor epitaxial layer 11 may be the same or different. In some embodiments, both the semiconductor epitaxial layer 11 and the substrate 10 may be made of SiC.

[0098] The semiconductor body 1 includes a first surface S1 and a second surface S2 disposed opposite to each other along the thickness direction X. The second surface S2 is the surface of the substrate 10 away from the semiconductor epitaxial layer 11, and the first surface S1 is the surface of the semiconductor epitaxial layer 11 away from the substrate 10.

[0099] In some embodiments, the semiconductor body 1 further includes a first epitaxial layer 111, a second epitaxial layer 112, and a third epitaxial layer 113 sequentially distributed between the second surface S2 and the first surface S1, i.e., the epitaxial layer 11 includes the first epitaxial layer 111, the second epitaxial layer 112, and the third epitaxial layer 113. The first epitaxial layer 111 is located on one side of the substrate 10 in the thickness direction X, the second epitaxial layer 112 is located on the side of the first epitaxial layer 111 opposite to the substrate 10, and the third epitaxial layer 113 is located on the side of the second epitaxial layer 112 opposite to the first epitaxial layer 111. The surface of the third epitaxial layer 113 opposite to the second epitaxial layer 112 is the first surface S1, and the surface of the substrate 10 opposite to the first epitaxial layer 111 is the second surface S2.

[0100] The JTE region 13, the second epitaxial layer 112 and the third epitaxial layer 113 have the same conductivity type, which is opposite to that of the first epitaxial layer 111 and the first region 15. The doping concentration of the second epitaxial layer 112 is greater than that of the third epitaxial layer 113.

[0101] The substrate 10, the first epitaxial layer 111, and the first region 15 are all of the first conductivity type, such as N-type. The second epitaxial layer 112, the third epitaxial layer 113, and the JTE region 13 are all of the second conductivity type, such as P-type.

[0102] In this embodiment, the epitaxial layer 11 forms a PPN structure, which helps the depletion region to extend longitudinally, reduces the electric field peak, and improves the breakdown voltage.

[0103] Combination Figure 8 As shown, an ion implantation process is used to form a second region 14, which extends from the first surface S1 into the semiconductor body 1. In the case where the semiconductor body 1 includes a first epitaxial layer 111, a second epitaxial layer 112, and a third epitaxial layer 113, the second region 14 extends from the first surface S1 into the second epitaxial layer 112. The conductivity type of the second region 14 is a second conductivity type, such as P-type.

[0104] Step S120: Form a trench extending from the first surface into the semiconductor body, and form a first region in the semiconductor body at the bottom of the trench; the first region includes a multi-level sub-region that is sequentially distributed and connected along the thickness direction, and the doping concentration of the multi-level sub-region gradually increases in the direction from the first surface to the second surface.

[0105] Combination Figures 9 to 11 As shown, an etching process is used to form an inner trench 12 in the epitaxial layer 11 extending from the first surface S1 to the semiconductor body 1 in the terminal region B.

[0106] In some embodiments, the trench includes multi-level sub-trenches, which include first-level sub-trenches to Nth-level sub-trenches, where N≥2. Along the direction from the first surface S1 to the second surface S2, the first-level sub-trenches to the Nth-level sub-trenches are distributed in a stepped manner and are interconnected, with the width of the first-level sub-trenches to the Nth-level sub-trenches gradually decreasing.

[0107] In some embodiments, the multi-level sub-regions include first-level sub-regions to Nth-level sub-regions with gradually increasing doping concentration. Along the direction from the first surface S1 to the second surface S2, the first-level sub-regions to Nth-level sub-regions are distributed in a stepped manner and connected, with the doping concentration gradually increasing and the width gradually decreasing.

[0108] Step S120, forming a trench extending from the first surface into the semiconductor body and forming a first region in the semiconductor body at the bottom of the trench, includes: A first mask layer with a first opening is formed on the first surface; A first-level sub-trench is formed through the first opening, extending from the first surface into the semiconductor body. A first-level sub-region is formed in the semiconductor body at the bottom of the first-level sub-trench; An nth mask layer with an nth opening is formed on the surface of the (n-1)th level sub-trench, and the nth opening exposes the bottom surface of the (n-1)th level sub-trench; 2≤n≤N; Through the nth opening, an nth sub-trench is formed that extends from the bottom surface of the (n-1)th sub-trench into the semiconductor body; The nth sub-region is formed in the semiconductor body at the bottom of the (n-1)th sub-region through the nth sub-trench, and the nth sub-region is connected to the (n-1)th sub-region. Remove the second mask layer up to the Nth mask layer.

[0109] As an example, N=3, combined with Figures 9 to 11 As shown, the multi-level sub-trench includes a first-level sub-trench 121, a second-level sub-trench 122, and a third-level sub-trench 123, and the multi-level sub-region includes a first-level sub-region 151, a second-level sub-region 152, and a third-level sub-region 153.

[0110] Combination Figure 9 As shown, a first mask layer 71 is first formed on the first surface S1 of the semiconductor body 1. The first mask layer 71 has a first opening 711, which exposes a portion of the first surface of the terminal region B. The first mask layer 71 can be a hard mask layer (HM mask). Then, using an etching process (such as dry etching), the epitaxial layer 11 is etched through the first opening 711 to form a first-level sub-trench 121. The first-level sub-trench 121 can extend from the first surface S1 into the third epitaxial layer 113.

[0111] Then, through the first-level sub-trench 121 and using a vertical ion implantation process, a first-level sub-region 151 is formed in the epitaxial layer 11 at the bottom of the first-level sub-trench 121. The width of the first-level sub-region 151 can be greater than the width of the first-level sub-trench 121. The first-level sub-region 151 and the first-level sub-trench 121 are distributed alternately.

[0112] Then, combine Figure 10 As shown, a second mask layer 72 is formed on the surface of the first-level sub-trench 121 (including the sidewalls and bottom of the first-level sub-trench 121). The second mask layer 72 has a second opening 721, which exposes a portion of the bottom surface of the first-level sub-trench 121. The material of the second mask layer 72 may include SiN, etc. Then, using an etching process (such as dry etching), the epitaxial layer 11 at the bottom of the first-level sub-trench 121 is etched through the second opening 721 to form a second-level sub-trench 122. The second-level sub-trench 122 extends from the bottom surface of the first-level sub-trench 121 into the third epitaxial layer 113, and the width of the second-level sub-trench 122 is smaller than the width of the first-level sub-trench 121. The first-level sub-region 151 is located at the bottom of the second-level sub-trench 122, and the first-level sub-region 151 and the second-level sub-trench 122 are spaced apart.

[0113] Then, through the second sub-trench 122 and using a vertical ion implantation process, a second sub-region 152 is formed in the epitaxial layer 11 at the bottom of the first sub-region 151. The second sub-region 152 is connected to the first sub-region 151, and the doping concentration of the second sub-region 152 is greater than that of the first sub-region 151. The width of the second sub-region 152 is less than the width of the first sub-region 151. The width of the second sub-region 152 can be greater than the width of the second sub-trench 122.

[0114] Then, combine Figure 11 As shown, a third mask layer 73 is formed on the surface of the second sub-trench 122 (including the sidewalls and bottom of the second sub-trench 122). The third mask layer 73 has a third opening 731, which exposes a portion of the bottom surface of the second sub-trench 122. The material of the third mask layer 73 may include SiN, etc. Then, using an etching process (such as dry etching), the epitaxial layer 11 at the bottom of the second sub-trench 122 is etched through the third opening 731 to form the third sub-trench 123. The third sub-trench 123 can extend from the bottom surface of the second sub-trench 122 into the third epitaxial layer 113, or the third sub-trench 123 can extend from the bottom surface of the second sub-trench 122 into the second epitaxial layer 112, and the width of the third sub-trench 123 is smaller than the width of the second sub-trench 122. The first-level sub-region 151 is located at the bottom of the third-level sub-groove 123, and the first-level sub-region 151 and the third-level sub-groove 123 are distributed alternately.

[0115] Then, through the third sub-trench 123, a third sub-region 153 is formed at the bottom of the second sub-region 152 using a vertical ion implantation process. The third sub-region 153 is connected to the second sub-region 152, and the doping concentration of the third sub-region 153 is greater than that of the second sub-region 152. The width of the third sub-region 153 is less than the width of the second sub-region 152. The width of the third sub-region 153 can be greater than the width of the third sub-trench 123.

[0116] Then, combine Figure 12 As shown, the second mask layer 72 and the third mask layer 73 are removed by an etching solution, such as by removing the SiN mask layer by hot phosphoric acid, while the first mask layer 71 is retained.

[0117] In this embodiment, the trenches 12 are distributed in a stepped manner, and the first region 15 is distributed in a stepped manner, which further reduces the layout electric field strength and improves the device breakdown voltage. Moreover, each sub-trench is formed, and a corresponding sub-region is formed, which simplifies the fabrication process.

[0118] Step S130: Form a JTE region in the semiconductor body that covers the sidewalls and bottom of the trench.

[0119] Combination Figure 13As shown, the JTE region 13 covers the sidewalls and bottom of the trench 12, so that the JTE region 13 encloses the trench 12. The conductivity type of the JTE region 13 is a second conductivity type, such as P-type.

[0120] In some embodiments, forming a JTE region covering the sidewalls and bottom of the trench in the semiconductor body includes: The first mask layer around the first opening is etched to enlarge the first opening into the target opening; By doping the semiconductor body on the sidewalls and bottom of the multilevel sub-trench through the target opening, a JTE region is formed. Remove the first mask layer.

[0121] Combination Figure 13 As shown, an etching process (such as wet etching) is used to etch the first mask layer 71 around the first opening 711 to enlarge the size of the first opening 711. By controlling the wet etching time, the enlarged size of the first opening 711 can be controlled to meet actual requirements. The enlarged first opening is the target opening 711', which exposes the epitaxial layer 11 around the first-level sub-trench 121.

[0122] A vertical ion implantation process is used to implant ions into the sidewalls and bottom of the trench 12 through the target opening 711', forming a JTE region 13 that completely covers the trench 12. It should be noted that by enlarging the first opening 711 to the target opening 711', ion implantation is performed on the sidewalls of the first-level sub-trench 121 of the trench 12, allowing the JTE region 13 to completely cover the trench 12.

[0123] Combination Figure 14 As shown, the first mask layer 71 is removed by an etching process (such as wet etching).

[0124] In this embodiment, the JTE region 13 covers the sidewalls and bottom of the trench 12, enhancing the longitudinal extension of the depletion region, further reducing the local field strength, increasing the breakdown voltage, and improving the reliability of the device. Moreover, after the trench 12 is formed, the JTE region 13 can be formed on the sidewalls and bottom of the multi-level sub-trench using low-energy ion implantation, reducing the risk of terminal lattice damage and further improving the reliability of the device.

[0125] Step S140: Fill the trench with a dielectric layer.

[0126] Combination Figure 15As shown, a thin-film deposition process is used to fill the trench 12 with a dielectric layer 2. Since the multi-level sub-trenches of the trench 12 are distributed in a stepped manner along the thickness direction X, the dielectric layer 2 is also distributed in a stepped manner along the thickness direction X. That is, the dielectric layer 2 includes multiple dielectric sub-layers that are distributed in a stepped manner along the thickness direction X and are connected, with one dielectric sub-layer filling each level of the sub-trench. The width of the multiple dielectric sub-layers gradually decreases in the direction from the first surface S1 to the second surface S2. In some embodiments, the material of the dielectric layer 2 includes silicon oxide, such as SiO2.

[0127] In this embodiment, the dielectric layer 2 forms a stepped structure, and the width of multiple dielectric sublayers gradually decreases in the direction from the first surface S1 to the second surface S2, so as to provide multi-level electric field mitigation, further reduce local electric field concentration, and improve breakdown voltage.

[0128] In some embodiments, the preparation method further includes: sequentially forming a field oxygen layer, an interlayer dielectric layer, a source electrode, and a drain electrode.

[0129] Combination Figure 16 As shown, a field oxide layer 5 is formed on the first surface S1 of the semiconductor body 1 using a thin film deposition process. The field oxide layer 5 covers the terminal region B and also covers the edge of the main junction region A2. The material of the field oxide layer 5 may include silicon oxide, such as SiO2.

[0130] Combination Figure 17 As shown, a thin-film deposition process is used to form an interlayer dielectric layer 6 covering the field oxygen layer 5. The material of the interlayer dielectric layer 6 may include silicon oxide, silicon nitride, etc.

[0131] Then, a source electrode 3 is formed on the first surface S1 of the semiconductor body 1 using a thin film deposition process, and the source electrode 3 is connected to the second region 14. The material of the source electrode 3 may include metals such as aluminum, copper, and nickel.

[0132] Combination Figure 1 As shown, a drain 4 is formed on the second surface S2 of the semiconductor body 1 using a thin-film deposition process. The drain 4 can cover the second surface S2 of the semiconductor body 1. The material of the drain 4 can include metals such as aluminum, copper, and nickel.

[0133] According to the semiconductor device fabrication method provided in the embodiments of this application, a trench 12 extending from the first surface S1 into the semiconductor body 1 is formed in the semiconductor body 1. A first region 15 is formed in the semiconductor body 1 at the bottom of the trench 12. The first region 15 includes a multi-level sub-region that is sequentially distributed and connected along the thickness direction X. In the direction from the first surface S1 to the second surface S2, the doping concentration of the multi-level sub-regions gradually increases, forming a longitudinal (i.e., thickness direction X) conductive path. The electric field gradually decreases along the longitudinal direction, avoiding excessively high local field strength and improving the breakdown voltage of the device. Furthermore, the trench 12 is filled with a dielectric layer 2, and the sidewalls and bottom of the trench 12 are covered with JTE regions 13, further reducing the local field strength and further improving the breakdown voltage, thereby improving the reliability of the device. Moreover, after the trench 12 is formed, low-energy ion implantation can be used to form JTE regions 13 on the sidewalls and bottom of the trench 12, reducing the risk of terminal lattice damage and further improving the reliability of the device.

[0134] Accordingly, this application also provides a power module. The power module includes a substrate and the semiconductor device from any of the above embodiments, wherein the substrate is used to support the semiconductor device.

[0135] For example, a power module can be used as one of a power amplifier, power converter, power controller, power management module, or power regulator. A power amplifier amplifies the power of an electrical signal. A power converter converts electrical energy from one form to another; for example, a power converter can be an AC / DC converter or a DC / DC converter. A power controller is a device for controlling the flow of power. A power management module manages the power supply, ensuring that power is stably and efficiently distributed to different parts of an electronic device. A power regulator adjusts the power output to meet the needs of a specific application.

[0136] On the other hand, embodiments of this application also provide a power conversion circuit. The power conversion circuit includes a circuit board and the semiconductor device in any of the above embodiments. The semiconductor device is electrically connected to the circuit board, and the power conversion circuit can be used for current conversion, voltage conversion, or power factor correction.

[0137] For example, the power conversion circuit can be used as one of an AC / DC converter, an AC / AC converter, a DC / DC converter, a DC / AC inverter, or a power factor correction (PFC) circuit, wherein the AC / DC converter is used to convert alternating current to direct current, the AC / AC converter is used to convert alternating current to alternating current, the DC / DC converter is used to convert direct current to direct current, the DC / AC inverter is used to convert direct current to alternating current, and the power factor correction circuit is used to improve the power factor of the power supply and reduce harmonic pollution of the power grid.

[0138] On the other hand, embodiments of this application also provide a vehicle. The vehicle includes a load and the power conversion circuit described in the above embodiments. The power conversion circuit is used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the converted direct current to the load to supply power to the load.

[0139] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and are not limited in number; for example, a first object can be one or more.

[0140] In the description of this application, "multiple" means two or more.

[0141] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0142] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor body includes a first surface and a second surface disposed opposite to each other in the thickness direction; the semiconductor body has a trench extending from the first surface into the semiconductor body, and the semiconductor body also includes a JTE region and a first region with opposite conductivity types, the JTE region covering the sidewalls and bottom of the trench, the first region being located at the bottom of the trench and spaced apart from the JTE region; the first region includes a multi-level sub-regions distributed and connected sequentially along the thickness direction, and the doping concentration of the multi-level sub-regions gradually increases in the direction from the first surface to the second surface; A dielectric layer is filled in the trench.

2. The semiconductor device according to claim 1, characterized in that, The multi-level sub-regions are distributed in a stepped manner, and the width of the multi-level sub-regions gradually decreases in the direction from the first surface to the second surface.

3. The semiconductor device according to claim 1, characterized in that, The trench includes a series of interconnected sub-trenches distributed in a stepped manner along the depth direction, and the width of the sub-trenches gradually decreases in the direction from the first surface to the second surface. The JTE region covers the sidewalls and bottom of the multi-level sub-trench, and the dielectric layer fills the multi-level sub-trench, forming a stepped structure.

4. The semiconductor device according to claim 3, characterized in that, The depth of the multi-level sub-trenches gradually decreases in the direction from the first surface to the second surface.

5. The semiconductor device according to claim 3, characterized in that, The number of levels in the multi-level sub-regions is the same as the number of levels in the multi-level sub-trenches.

6. The semiconductor device according to claim 1, characterized in that, The multi-level sub-region includes a first-level sub-region to an Nth-level sub-region with gradually increasing doping concentration. The semiconductor body also includes a multi-level scattering region with the same conductivity type as the first region. The multi-level scattering region includes a first-level scattering region to an Nth-level scattering region with gradually increasing doping concentration. The first-level scattering region encompasses the JTE region and the first-level sub-region, and the nth-level scattering region encompasses the (n-1)th-level scattering region and the nth-level sub-region, where 2 ≤ n ≤ N.

7. The semiconductor device according to claim 6, characterized in that, The doping concentration of the i-th order scattering region is less than the doping concentration of the i-th order sub-region, and 1≤i≤N.

8. The semiconductor device according to claim 1, characterized in that, The semiconductor body further includes a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer sequentially distributed between the second surface and the first surface. The JTE region, the second epitaxial layer, and the third epitaxial layer have the same conductivity type, which is opposite to that of the first epitaxial layer and the first region. The doping concentration of the second epitaxial layer is greater than that of the third epitaxial layer. The trench extends from the first surface into the third epitaxial layer, and the first region is located in the third epitaxial layer and the second epitaxial layer, or the first region is located in the second epitaxial layer; or, The trench extends from the first surface into the second epitaxial layer, and the first region is located in the second epitaxial layer.

9. The semiconductor device according to claim 8, characterized in that, The semiconductor body further includes a plurality of epitaxial pillars spaced apart, wherein the epitaxial pillars have the opposite conductivity type to the first epitaxial layer; The epitaxial pillar extends from the surface of the first epitaxial layer near the second epitaxial layer into the first epitaxial layer, or the epitaxial pillar penetrates the first epitaxial layer.

10. The semiconductor device according to any one of claims 1-9, characterized in that, The semiconductor body is provided with a plurality of trenches, the sidewalls and bottom of each trench are covered with the JTE region, and each trench is filled with the dielectric layer; the semiconductor body includes a plurality of first regions, and the plurality of first regions are respectively located at the bottom of the plurality of JTE trenches; In the direction toward the edge of the semiconductor body, a plurality of trenches are spaced apart, the width and / or depth of the plurality of trenches gradually increase, and / or the width and / or thickness of the plurality of first regions gradually increase.

11. The semiconductor device according to claim 10, characterized in that, The spacing between adjacent trenches is the same.

12. The semiconductor device according to claim 10, characterized in that, The semiconductor device further includes: A field oxide layer is located on the first surface of the semiconductor body.

13. A method for fabricating a semiconductor device, characterized in that, The method includes: A semiconductor body is provided, the semiconductor body including a first surface and a second surface disposed opposite to each other in the thickness direction; A trench is formed extending from the first surface into the semiconductor body, and a first region is formed in the semiconductor body at the bottom of the trench; the first region includes a multi-level sub-region that is sequentially distributed and connected along the thickness direction, and the doping concentration of the multi-level sub-region gradually increases in the direction from the first surface to the second surface; A JTE region is formed in the semiconductor body, covering the sidewalls and bottom of the trench. The JTE region is spaced apart from the first region and has the opposite conductivity type to the first region. A medium layer is filled into the trench.

14. The method for fabricating a semiconductor device according to claim 13, characterized in that, The multi-level sub-regions include first-level sub-regions to Nth-level sub-regions with gradually increasing doping concentrations, and the trenches include multi-level sub-trenches, which include first-level sub-trenches to Nth-level sub-trenches; The formation of a trench extending from the first surface into the semiconductor body, and the formation of a first region in the semiconductor body at the bottom of the trench, includes: A first mask layer having a first opening is formed on the first surface; A first-level sub-trench is formed through the first opening, extending from the first surface into the semiconductor body. A first-level sub-region is formed in the semiconductor body at the bottom of the first-level sub-trench; An nth mask layer with an nth opening is formed on the surface of the (n-1)th level sub-trench, the nth opening exposing the bottom surface of the (n-1)th level sub-trench; 2≤n≤N; An nth sub-trench is formed through the nth opening, extending from the bottom surface of the (n-1)th sub-trench into the semiconductor body. The nth sub-region is formed in the semiconductor body at the bottom of the (n-1)th sub-region through the nth sub-trench, and the nth sub-region is connected to the (n-1)th sub-region. Remove the second mask layer up to the Nth mask layer.

15. The method for fabricating a semiconductor device according to claim 14, characterized in that, The formation of a JTE region covering the sidewalls and bottom of the trench in the semiconductor body includes: The first mask layer around the first opening is etched to enlarge the first opening into the target opening; The semiconductor body on the sidewalls and bottom of the multi-level sub-trench is doped through the target opening to form the JTE region; Remove the first mask layer.

16. A power module, characterized in that, Including a substrate and as claimed in claim 1 12 The semiconductor device of any one of the claims, wherein the substrate is used to support the semiconductor device.

17. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and as claimed in claim 1. The semiconductor device of the 12th embodiment is electrically connected to the circuit board.

18. A vehicle, characterized in that, The device includes a load and a power conversion circuit as described in claim 17, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

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