Semiconductor device including transistor structure and separation structure

Abstract

A semiconductor device includes a separation structure and a transistor structure on a side surface of the separation structure. The transistor structure includes: a first source / drain region; a second source / drain region spaced apart from the first source / drain region; a channel layer connected to the first source / drain region and the second source / drain region, the channel layer being spaced apart in a first direction; a gate electrode covering each of the channel layers; a gate dielectric structure between the first source / drain region and the second source / drain region and the gate electrode, between the channel layers and the gate electrode, and between the separation structure and the gate electrode; and first and second insulating spacers spaced apart from each other, adjacent to the separation structure, and between the first source / drain region and the second source / drain region.

Description

Cross-references to related applications

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2025-0010596, filed on January 23, 2025, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to a semiconductor device including a transistor structure and a partition structure. Background Technology

[0003] With the increasing demand for high performance, high speed, and / or multifunctionality in semiconductor devices, the integration density of semiconductor devices has been improved. To manufacture semiconductor devices with fine patterns that correspond to this trend of high integration, it has become important to realize patterns with fine widths or fine gaps. Furthermore, to overcome the limitations in operating characteristics caused by the reduction in the size of planar metal-oxide-semiconductor field-effect transistors (MOSFETs), efforts have been made to develop semiconductor devices including transistors with three-dimensional channel structures.

[0004] The information disclosed in this background section is technical information that was known to or derived by the inventor before or during the implementation of embodiments of this application, or that was acquired during the implementation of embodiments. Therefore, it may contain information that does not form prior art known to the public. Summary of the Invention

[0005] One or more example embodiments provide a semiconductor device capable of improving integration and performance, and a method of manufacturing the semiconductor device.

[0006] Additional aspects will be set forth in part in the description which follows, and will become clear in part from the description, or may be learned by practice of the embodiments presented.

[0007] According to an aspect of an example embodiment, a semiconductor device may include a separation structure and a transistor structure on a side surface of the separation structure. The transistor structure may include: a first source / drain region; a second source / drain region spaced apart from the first source / drain region; a channel layer connected to the first source / drain region and the second source / drain region, the channel layers being spaced apart in a first direction; a gate electrode covering each of the channel layers; a gate dielectric structure between the first source / drain region and the second source / drain region and the gate electrode, between the channel layer and the gate electrode, and between the separation structure and the gate electrode; a first insulating spacer and a second insulating spacer, spaced apart from each other, adjacent to the separation structure, and between the first source / drain region and the second source / drain region.

[0008] According to an example embodiment, a semiconductor device may include: a partition structure having a first side surface and a second side surface opposite to the first side surface in a first direction; a first transistor structure and a second transistor structure, the first transistor structure being on the first side surface of the partition structure and the second transistor structure being on the second side surface of the partition structure, wherein each of the first transistor structure and the second transistor structure includes: channel layers stacked and spaced apart from each other in a second direction intersecting the first direction, and each having a first side surface facing the partition structure and a second side surface opposite to the first side surface; a gate electrode covering the upper surface, lower surface and first side surface of each of the channel layers; and a gate dielectric structure between the channel layers and the gate electrode. Between the gate electrode and the partition structure, wherein in each of the first transistor structure and the second transistor structure, the gate electrode includes: a lower electrode portion located below the lower surface of the lowest channel layer in the second direction; an upper electrode portion located on the upper surface of the highest channel layer in the second direction; and an intermediate electrode portion located between intermediate channel layers adjacent to each other in the second direction and between the highest and lowest channel layers, and the distance between the intermediate electrode portion of the gate electrode of the first transistor structure and the intermediate electrode portion of the gate electrode of the second transistor structure is less than the distance between the highest channel layer of the first transistor structure and the highest channel layer of the second transistor structure.

[0009] According to an example embodiment, a semiconductor device may include: a separator having a first side surface and a second side surface opposite to the first side surface in a first direction; a first transistor structure and a second transistor structure, the first transistor structure being on the first side surface of the separator and the second transistor structure being on the second side surface of the separator, wherein each of the first transistor structure and the second transistor structure includes: a first source / drain region and a second source / drain region, spaced apart from each other in a second direction perpendicular to the first direction; and a channel layer connected to the first source / drain region and the second source / drain region, the channel layers being spaced apart from each other in a third direction intersecting the first and second directions, and each having a first side surface facing the separator. and a second side surface opposite to the first side surface; a gate electrode covering the upper surface, lower surface and first side surface of each of the channel layers; and a gate dielectric structure between the first source / drain region and the second source / drain region and the gate electrode, between the channel layer and the gate electrode, and between the partition structure and the gate electrode, wherein the partition structure includes a first partition region between the gate electrode of the first transistor structure and the gate electrode of the second transistor structure, and wherein the first partition region includes: a first partition pattern between the channel layer of the first transistor structure and the channel layer of the second transistor structure, and having a first width; and a second partition pattern at a level higher than the channel layer, on the first partition pattern, and having a second width greater than the first width.

[0010] According to an example embodiment, a method of manufacturing a semiconductor device may include: alternately stacking a sacrificial layer and a trench layer on a substrate; forming a capping layer; sequentially stacking a first mask pattern and a second mask pattern on the capping layer; forming trenches and a stacked pattern by etching the first mask pattern and the second mask pattern; forming an insulating pad in the trench; forming a first separating insulating layer on the insulating pad; etching the first separating insulating layer to form a first separating pattern; forming a second separating insulating layer on the upper surface of the first separating pattern; etching the second separating insulating layer to form a preliminary separating insulating pattern; and forming a trench and a stacked pattern by etching the preliminary separating insulating layer. The process involves: forming an insulating pattern to create an element isolation insulating pattern; forming a sacrificial gate line; forming a spacer material layer on the sacrificial gate line; forming a gate spacer by etching the spacer material layer; etching a stacked pattern to form a source / drain trench; etching an insulating pad; forming a spacer material layer; forming a third partition pattern through the spacer material layer; etching the spacer material layer to form an insulating spacer; forming a source / drain region within the source / drain trench; removing the sacrificial gate line to form a gate trench; forming an insulating pattern; forming a first gate dielectric layer; forming a second gate dielectric layer; forming a gate electrode; and forming a gate partition pattern. Attached Figure Description

[0011] The above and other aspects, features, and advantages of certain exemplary embodiments of the present disclosure will become clearer from the following description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4 , Figure 5A and Figure 5B This is a diagram illustrating a semiconductor device according to one or more embodiments;

[0013] Figure 6 This is an enlarged plan view of a semiconductor device according to one or more embodiments;

[0014] Figure 7 This is an enlarged plan view of a semiconductor device according to one or more embodiments;

[0015] Figure 8 This shows an enlarged cross-sectional view of a semiconductor device according to one or more embodiments;

[0016] Figure 9 This shows an enlarged cross-sectional view of a semiconductor device according to one or more embodiments;

[0017] Figure 10 This shows an enlarged cross-sectional view of a semiconductor device according to one or more embodiments;

[0018] Figure 11 This shows an enlarged cross-sectional view of a semiconductor device according to one or more embodiments;

[0019] Figure 12 , Figure 13 and Figure 14 This shows a cross-sectional view of a semiconductor device according to one or more embodiments;

[0020] Figure 15 This shows a partial cross-sectional view of a semiconductor device according to one or more embodiments;

[0021] Figure 16 This shows a partial cross-sectional view of a semiconductor device according to one or more embodiments; and

[0022] Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 , Figure 24A , Figure 24B , Figure 24C , Figure 25 , Figure 26A , Figure 26B, Figure 26C , Figure 27A , Figure 27B , Figure 28 , Figure 29 , Figure 30 , Figure 31A , Figure 31B , Figure 31C , Figure 32A , Figure 32B , Figure 33A , Figure 33B , Figure 34 and Figure 35 This is a diagram illustrating a method for manufacturing a semiconductor device according to one or more embodiments. Detailed Implementation

[0023] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The same components in the drawings are referred to by the same reference numerals, and repeated descriptions thereof will be omitted. The embodiments described herein are exemplary embodiments, and therefore, the present disclosure is not limited thereto and may be implemented in various other forms.

[0024] As used in this article, expressions such as "at least one of..." modify the entire list of elements after the list of elements, rather than modifying individual elements in the list. For example, the expression "at least one of a, b, and c" should be understood as including only a, including only b, including only c, including both a and b, including both a and c, including both b and c, or including all of a, b, and c.

[0025] It will be understood that when a component or layer is referred to as being "above," "on top of," "above," "below," "below," "connected to," or "coupled to" another component or layer, it may be directly above, above, above, below, below, or below that other component or layer, or there may be intermediate components or layers. Conversely, when a component is referred to as being "directly above," "above," "above," "below," "below," "below," "directly connected to," or "directly coupled to" another component or layer, there are no intermediate components or layers.

[0026] In the following text, terms such as “upper,” “middle,” and “lower” may be replaced by other terms such as “first,” “second,” and “third,” and may be used to describe elements of this specification. Terms such as “first,” “second,” and “third” may be used to describe various elements, but are not limited to these, and a “first element” may be referred to as a “second element.” In this specification, terms such as “lower,” “upper,” “upper end,” and “lower end” may be used to describe elements based on the accompanying drawings.

[0027] Terms such as “first” and “second” can be used to describe various components, but only for the purpose of distinguishing one component from another. These terms do not limit the differences in the materials or structures of the components.

[0028] Unless otherwise specified, singular terms may include plural forms. Furthermore, when a section “includes” a component, unless otherwise stated, it means that other components may also be included, rather than excluding them.

[0029] The use of the term "the" and similar indicative terms can correspond to both the singular and plural forms.

[0030] Unless explicitly described in terms of order, the operations of the method may be performed in the appropriate order. Furthermore, the use of all illustrative terms (e.g., etc.) is solely for the purpose of describing the technical idea in detail, and its scope is not limited by these illustrative or exemplary terms unless restricted by the claims.

[0031] In this specification, a "transistor structure" may include: a first element included in the transistor (e.g., a channel layer, source / drain regions, gate dielectric structure, and gate electrode); and a second element in contact with or adjacent to the transistor (e.g., a gate spacer, insulating spacer, insulating pattern, insulating structure, gate capping pattern, etc.). However, embodiments of this disclosure are not limited thereto.

[0032] In the following text, reference will be made to Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4 , Figure 5A , Figure 5B , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 Example embodiments of the partition structure and transistor structure are described, and references will be made to... Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16 An example embodiment of an interconnect structure that is electrically connected to elements of a transistor is described.

[0033] Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4 , Figure 5A and Figure 5BThis is a diagram illustrating a semiconductor device according to one or more embodiments.

[0034] First, refer to Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4 , Figure 5A and Figure 5B A semiconductor device is described according to one or more embodiments. Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4 , Figure 5A and Figure 5B middle, Figure 1A A semiconductor device according to one or more embodiments is made of Figure 3A , Figure 3B , Figure 4 , Figure 5A and Figure 5B The “H1” in the diagram indicates the plan view at the first elevation level (H1). Figure 1B It shows the result of Figure 1A A magnified view of the area indicated by "A1" in the image. Figure 2A A semiconductor device according to one or more embodiments is made of Figure 3A , Figure 3B , Figure 4 , Figure 5A and Figure 5B The "H2" in the diagram indicates the plan view at the second altitude level (H2). Figure 2B It shows the result of Figure 2A A magnified view of the area indicated by "A2" in the image. Figure 3A It shows along Figure 1A and Figure 2A A cross-sectional view of the region intercepted by line I-I'. Figure 3B It shows the result of Figure 3A A magnified view of the area indicated by "B" in the image. Figure 4 It shows along Figure 1A and Figure 2A A cross-sectional view of the area intercepted by line II-II. Figure 5A It shows along Figure 1A and Figure 2A A cross-sectional view of the area intercepted by line III-III, and Figure 5B It shows the result of Figure 5A A magnified view of the area indicated by the "C".

[0035] refer to Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4 , Figure 5A and Figure 5B The semiconductor device 1 according to one or more embodiments may include a partition structure 51 and transistor structures T1, T2, T3 and T4. Each partition structure 51 may have a first side surface 51S1 and a second side surface 51S2 that are parallel to each other in a first horizontal direction (X direction). Each partition structure 51 may have a line shape extending in a second horizontal direction (Y direction) perpendicular to the first horizontal direction (X direction).

[0036] Transistor structures T1, T2, T3, and T4 may include a first transistor structure T1, a second transistor structure T2, a third transistor structure T3, and a fourth transistor structure T4. The first transistor structure T1 and the second transistor structure T2 may face each other with a separator structure 51 between them, and the third transistor structure T3 and the fourth transistor structure T4 may also face each other with a separator structure 51 between them. The first transistor structure T1 and the second transistor structure T2, which face each other, may have a mirror-symmetric structure, and the third transistor structure T3 and the fourth transistor structure T4, which face each other, may also have a mirror-symmetric structure. The second transistor structure T2 and the third transistor structure T3 may be disposed between a pair of adjacent separator structures 51.

[0037] Each of the first transistor structure T1 and the second transistor structure T2 may include elements that can form the first transistor and elements that are in contact with or adjacent to such elements, and each of the third transistor structure T3 and the fourth transistor structure T4 may include elements that can form the second transistor and elements that are in contact with or adjacent to such elements. Here, the first transistor may be an n-type metal-oxide-semiconductor (MOS) transistor (NMOS) or a p-type MOS transistor (PMOS), and when the first transistor is an NMOS transistor, the second transistor may be a PMOS transistor, and when the first transistor is a PMOS transistor, the second transistor may be an NMOS transistor.

[0038] In the following text, a partition structure 51 and a first transistor structure T1 and a second transistor structure T2 arranged on both sides of the partition structure 51 in the horizontal direction will be described.

[0039] The first transistor structure T1 can be disposed on the first side surface 51S1 of the partition structure 51, and the second transistor structure T2 can be disposed on the second side surface 51S2 of the partition structure 51.

[0040] Each of transistor structures T1, T2, T3, and T4 may include a channel layer 9, gate electrodes 81 and 82, a gate dielectric structure 79, and source / drain regions 54 and 57. The source / drain regions 54 of the first transistor structure T1 and the second transistor structure T2 may have a different conductivity type than the source / drain regions 57 of the third transistor structure T3 and the fourth transistor structure T4.

[0041] The channel layer 9 can face the partition structure 51 in the first horizontal direction (X direction).

[0042] In each of the first transistor structure T1 and the second transistor structure T2, the gate electrode 81, the gate dielectric structure 79, the channel layer 9, and the source / drain region 54 can form the first transistor.

[0043] In each of the third transistor structure T3 and the fourth transistor structure T4, the gate electrode 82, the gate dielectric structure 79, the channel layer 9, and the source / drain region 57 can form a second transistor.

[0044] Source / drain regions 54 and 57 may include epitaxial semiconductor material layers formed by an epitaxial growth process.

[0045] The source / drain regions 54 of the first transistor structure T1 and the second transistor structure T2 can have a first conductivity type, and the source / drain regions 57 of the third transistor structure T3 and the fourth transistor structure T4 can have a second conductivity type. One of the first conductivity type and the second conductivity type can be an N-type conductivity type, and the other can be a P-type conductivity type.

[0046] In one or more embodiments, when the source / drain region 54 is an N-type conductive source / drain region of an NMOS transistor, each source / drain region 54 may include a silicon (Si) layer.

[0047] In one or more embodiments, when the source / drain region 57 is a P-type conductive source / drain region of a PMOS transistor, each source / drain region 57 may include at least one of a silicon (Si) layer, a germanium (Ge) layer, or a silicon-germanium (SiGe) layer.

[0048] In the following text, a partition structure 51 and a first transistor structure T1 and a second transistor structure T2 disposed on both sides of the partition structure 51 in the horizontal direction will be described.

[0049] The source / drain region 54 may include a first source / drain region 54a and a second source / drain region 54b that are spaced apart from each other and adjacent to each other in a second horizontal direction (Y direction). The second horizontal direction (Y direction) may be perpendicular to the first horizontal direction (X direction).

[0050] The channel layer 9 can be disposed between the source / drain regions 54. The lower surface of the source / drain regions 54 can be disposed at a lower level than the channel layer 9.

[0051] In the following text, the channel layer 9 disposed between the first source / drain region 54a and the second source / drain region 54b will be described.

[0052] The channel layers 9 can be stacked and spaced apart from each other in a vertical direction (Z direction). The vertical direction (Z direction) can be perpendicular to the first horizontal direction (X direction) and the second horizontal direction (Y direction). The channel layers 9 can be connected to the first source / drain region 54a and the second source / drain region 54b. Each channel layer 9 can have a first side surface 9S1 facing the partition structure 51 and a second side surface 9S2 opposite to the first side surface 9S1. The channel layers 9 can be spaced apart from the partition structure 51. The channel layers 9 can include a lower channel layer 9L, a first intermediate channel layer 9M1 on the lower channel layer 9L, a second intermediate channel layer 9M2 on the first intermediate channel layer 9M1, and an upper channel layer 9U on the second intermediate channel layer 9M2. The channel layers 9 can be formed of a semiconductor material that can be used as a channel region of a transistor. For example, the channel layers 9 can include a semiconductor material such as single-crystal silicon.

[0053] The distance between the channel layer 9 and the separator structure 51 can be from about 1 nm to about 5 nm.

[0054] The gate electrode 81 may cover each channel layer 9. For example, the gate electrode 81 may cover the upper surface, lower surface, and first side surface 9S1 of each channel layer 9. The gate electrode 81 may include a lower electrode portion 81L, intermediate electrode portions 81M1, 81M2, and 81M3, and an upper electrode portion 81U. The lower electrode portion 81L may be disposed below the lower surface of the lower channel layer 9L. The intermediate electrode portions 81M1, 81M2, and 81M3 may be disposed between adjacent channel layers 9 in the vertical direction (Z direction). For example, the intermediate electrode portions 81M1, 81M2, and 81M3 may include a first intermediate electrode portion 81M1 disposed between the lower channel layer 9L and the first intermediate channel layer 9M1, a second intermediate electrode portion 81M2 disposed between the first intermediate channel layer 9M1 and the second intermediate channel layer 9M2, and a third intermediate electrode portion 81M3 disposed between the second intermediate channel layer 9M2 and the upper channel layer 9U. The upper electrode portion 81U can be disposed on the upper surface of the upper channel layer 9U.

[0055] The gate electrode 81 may be formed of a conductive material. For example, the gate electrode 81 may include a first conductive material for controlling the work function to control the threshold voltage of the transistor, and a second conductive material having a low resistivity to reduce resistance. For example, the gate electrode 81 may include a first conductive material and a second conductive material. The first conductive material may include at least one of TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSiN, or RuTiN, and the second conductive material may include at least one of Ti, Ta, Ru, W, Mo, Pt, Ni, or Co.

[0056] The distance between the channel layer 9 and the separator structure 51 can be greater than the distance between the gate electrode 81 and the separator structure 51. For example, the distance between the first intermediate electrode portion 81M and the separator structure 51 can be less than the distance between the first intermediate channel layer 9M1 and the separator structure 51.

[0057] Each of the first intermediate electrode portion 81M1, the second intermediate electrode portion 81M2, and the third intermediate electrode portion 81M3 may include a first electrode portion 81a and a second electrode portion 81b. The first electrode portion 81a is disposed between adjacent channel layers 9 in the vertical direction (Z direction), and the second electrode portion 81b extends from the first electrode portion 81a in a direction oriented toward the partition structure 51. In each of the first intermediate electrode portion 81M1, the second intermediate electrode portion 81M2, and the third intermediate electrode portion 81M3, the thickness of the second electrode portion 81b in the vertical direction (Z direction) may be greater than the thickness of the first electrode portion 81a in the vertical direction (Z direction).

[0058] The distance between the gate electrode 81 of the first transistor structure T1 and the gate electrode 81 of the second transistor structure T2 can be less than the distance between the channel layer 9 of the first transistor structure T1 and the channel layer 9 of the second transistor structure T2. For example, the distance between the intermediate electrode portions 81M1, 81M2, and 81M3 of the gate electrode 81 of the first transistor structure T1 and the intermediate electrode portions 81M1, 81M2, and 81M3 of the gate electrode 81 of the second transistor structure T2 can be less than the distance between the upper channel layer 9U of the first transistor structure T1 and the upper channel layer 9U of the second transistor structure T2.

[0059] Each of the first transistor structure T1 and the second transistor structure T2 may include a gate spacer 42a and an insulating spacer 45. The gate spacer 42a may include a first gate spacer 42a1 and a second gate spacer 42a2 disposed on both sides of the gate electrode 81 in a second horizontal direction. Each gate spacer 42a may include a first spacer material layer 39 disposed on both sides of the gate electrode 81 in a second horizontal direction and a second spacer material layer 36 disposed between the first spacer material layer 39 and the channel layer 9. The first spacer material layer 39 may include at least one of SiN, SiOCN, SiOC, SiBN, or SiCN, and the second spacer material layer 36 may include at least one of SiN, SiOCN, SiOC, SiBN, or SiCN. The second spacer material layer 36 may include a material different from the first spacer material layer 39.

[0060] The insulating spacer 45 may include a first insulating spacer 45a and a second insulating spacer 45b, which are disposed between the first source / drain region 54a and the second source / drain region 54b, adjacent to the partition structure 51, and spaced apart from each other in a second horizontal direction (Y direction). The first insulating spacer 45a may contact the first source / drain region 54a, and the second insulating spacer 45b may contact the second source / drain region 54b. The insulating spacer 45 may be spaced apart from the gate spacer 42a at a first level lower than the level of the upper surface of the upper channel layer 9U in the channel layer 9. The insulating spacer 45 may contact the partition structure 51.

[0061] The thickness of each insulating spacer 45 in the second horizontal direction (Y direction) may be about 5 nm or less.

[0062] The thickness of each insulating spacer 45 in the second horizontal direction (Y direction) can be from about 0.5 nm to about 4 nm.

[0063] The insulating spacer 45 may include materials other than silicon oxide. For example, the insulating spacer 45 may include at least one of SiN, SiOCN, SiOC, SiBN, or SiCN.

[0064] Each of the first transistor structure T1 and the second transistor structure T2 may further include an insulating pattern 72. The insulating pattern 72 may include a first portion 72a and a second portion 72b extending from the first portion 72a. The first portion 72a of the insulating pattern 72 may be disposed between the channel layer 9 and the partition structure 51. The second portion 72b of the insulating pattern 72 may be disposed between the lower electrode portion 81L and the partition structure 51, between the intermediate electrode portions 81M1, 81M2, and 81M3 and the partition structure 51, and between the upper electrode portion 81U and the partition structure 51. In the insulating pattern 72, the thickness of each first portion 72a in the first horizontal direction (X direction) may be greater than the thickness of each second portion 72b in the first horizontal direction (X direction).

[0065] The thickness of each first portion 72a in the first horizontal direction (X direction) can be from about 1 nm to about 5 nm. The thickness of each second portion 72b in the first horizontal direction (X direction) can be less than the thickness of each first portion 72a in the first horizontal direction (X direction), and can be about 4 nm or less.

[0066] The thickness of each first portion 72a in the first horizontal direction (X direction) can be greater than the thickness of the second gate dielectric layer 77.

[0067] In one or more embodiments, the thickness of each second portion 72b in the first horizontal direction (X direction) may be less than the thickness of the second gate dielectric layer 77.

[0068] In one or more embodiments, the thickness of each second portion 72b in the first horizontal direction (X direction) may be the same as or substantially the same as the thickness of the second gate dielectric layer 77 (e.g., allowing minor variations).

[0069] Each first portion 72a may have a concave upper surface and a concave lower surface. When viewed in a plan view, each first portion 72a may have a concave side surface in the second horizontal direction (Y direction). The insulating pattern 72 may contact the channel layer 9 and the partition structure 51 between the channel layer 9 and the partition structure 51.

[0070] The width of the insulating pattern 72 in the second horizontal direction (Y direction) may be smaller than the width of each channel layer 9 in the second horizontal direction (Y direction). The width of the insulating pattern 72 in the first horizontal direction (X direction) may be smaller than the width of each channel layer 9 in the first horizontal direction (X direction).

[0071] The width of the insulating pattern 72 in the second horizontal direction (Y direction) may be greater than the width of each insulating spacer 45 in the second horizontal direction (Y direction).

[0072] The insulating pattern 72 may include a material different from the insulating spacer 45. For example, the insulating pattern 72 may include silicon oxide.

[0073] The gate dielectric structure 79 can be disposed between the gate spacer 42a and the gate electrode 81, between the channel layer 9 and the gate electrode 81, between the source / drain region 54 and the gate electrode 81, between the insulating pattern 72 and the gate electrode 81, and between the partition structure 51 and the gate electrode 81.

[0074] The gate dielectric structure 79 may include a first gate dielectric layer 75 and a second gate dielectric layer 77.

[0075] The second gate dielectric layer 77 can be disposed between the gate spacer 42a and the gate electrode 81, between the channel layer 9 and the gate electrode 81, between the source / drain region 54 and the gate electrode 81, between the insulating pattern 72 and the gate electrode 81, and between the partition structure 51 and the gate electrode 81. The second gate dielectric layer 77 can contact the gate electrode 81.

[0076] A first gate dielectric layer 75 may be disposed between the second gate dielectric layer 77 and the channel layer 9, and between the second gate dielectric layer 77 and the source / drain region 54. The first gate dielectric layer 75 may include a first dielectric portion 75a disposed between the second gate dielectric layer 77 and the channel layer 9, and a second dielectric portion 75b disposed between the second gate dielectric layer 77 and the source / drain region 54. The thickness of the second dielectric portion 75b may be greater than the thickness of the first dielectric portion 75a. Therefore, by forming the second dielectric portion 75b to be greater than the thickness of the first dielectric portion 75a, the separation distance between the gate electrode 81 and the source / drain region 54 can be increased, thereby preventing or minimizing the leakage current of the transistor caused by gate-induced drain leakage (GIDL) phenomenon.

[0077] The partition structure 51 may include a first partition pattern 21, a second partition pattern 24, and a third partition pattern 50.

[0078] The first separator pattern 21 may include nitride-based materials. The first separator pattern 21 may be formed of a dielectric material with a dielectric constant of about 7 or less. For example, the first separator pattern 21 may include SiN, SiOCN, SiBN, or SiCN.

[0079] The second separator pattern 24 may include nitride-based materials. For example, the second separator pattern 24 may include SiN, SiOCN, SiBN, or SiCN. In one or more embodiments, the second separator pattern 24 may include the same material as the first separator pattern 21. In one or more embodiments, the second separator pattern 24 may include a different material than the first separator pattern 21.

[0080] The third separator pattern 50 may include a nitride-based material. For example, the third separator pattern 50 may include SiN, SiOCN, SiBN, or SiCN. In one or more embodiments, the third separator pattern 50 may include the same material as the first separator pattern 21. In one or more embodiments, the third separator pattern 50 may include a different material than the first separator pattern 21.

[0081] The partition structure 51 may include a first partition region 51a adjacent to the gate electrode 81, the gate dielectric structure 79, and the channel layer 9, and a second partition region 51b adjacent to the first source / drain region 54a and the second source / drain region 54b. For example, in the partition structure 51, the region disposed between the gate electrode 81 of the first transistor structure T1 and the gate electrode 81 of the second transistor structure T2 may be defined as the first partition region 51a, and the region disposed between the source / drain region 54 of the first transistor structure T1 and the source / drain region 54 of the second transistor structure T2 may be defined as the second partition region 51b.

[0082] The first partition pattern 21 can be disposed in the first partition region 51a and the second partition region 51b. The upper surface of the first partition pattern 21 in the first partition region 51a can be disposed at a level higher than the level of the upper channel layer 9U in the channel layer 9, and the upper surface of the first partition pattern 21 in the second partition region 51b can be disposed at a level lower than the level of the upper channel layer 9U. The lower surface of the first partition pattern 21 can be disposed at a level lower than the level of the lower surface of the source / drain region 54.

[0083] The second separating pattern 24 can be disposed within the first separating region 51a. The second separating pattern 24 can be disposed on top of the first separating pattern 21 within the first separating region 51a. The width of the second separating pattern 24 in the first horizontal direction (X direction) can be greater than the width of the first separating pattern 21 in the first horizontal direction (X direction). The second separating pattern 24 can cover the upper surface of the first separating pattern 21, and can cover a portion of the upper surface of the first separating pattern 21. A portion of the second separating pattern 24 can overlap with the insulating pattern 72. The upper surface of the second separating pattern 24 can be coplanar with the upper surface of the gate electrode 81.

[0084] The side surface of the second dividing pattern 24 may have a curved portion 24B. The curved portion 24B on the side surface of the second dividing pattern 24 may be disposed between a first side surface that extends from the upper surface of the second dividing pattern 24 and is substantially vertical, and a second side surface that extends from the first side surface toward the first dividing pattern 21 and is inclined.

[0085] The height difference between the curved portion 24B on the side surface of the second dividing pattern 24 and the upper surface of the upper channel layer 9U can be from about 5 nm to about 10 nm.

[0086] The height difference between the curved portion 24B on the side surface of the second partition pattern 24 and the upper surface of the upper channel layer 9U can be greater than the thickness of the gate dielectric structure 79.

[0087] The height difference between the curved portion 24B on the side surface of the second partition pattern 24 and the upper surface of the upper channel layer 9U can be greater than the distance between the channel layer 9 and the partition structure 51.

[0088] The third dividing pattern 50 can be disposed in the second dividing area 51b. The third dividing pattern 50 can contact the first dividing pattern 21 within the second dividing area 51b. Within the second dividing area 51b, the upper surface of the first dividing pattern 21 can be disposed at a level lower than the level of the upper surface of the source / drain area 54, and the upper surface of the third dividing pattern 50 can be disposed at a level higher than the level of the upper surface of the source / drain area 54.

[0089] The semiconductor device 1 may also include a substrate 3a, a protrusion 3b extending upward from the substrate 3a, and an element isolation insulating pattern 26 disposed on the substrate 3a and disposed between the protrusions 3b.

[0090] In one or more embodiments, the substrate 3a and the protruding portion 3b may include semiconductor material.

[0091] In one or more embodiments, the base 3a and the protruding portion 3b may include an insulating material.

[0092] The component isolation insulation pattern 26 may include an insulating material such as silicon oxide.

[0093] The channel layer 9 can be disposed on the protruding portion 3b and can be spaced apart from the protruding portion 3b.

[0094] When viewed from one of the protrusions 3b located below the first transistor structure T1, the lower electrode portion 81L of the gate electrode 81 can be disposed between the lower channel layer 9L and the protrusion 3b, and the gate dielectric structure 79 can cover the upper surface and side surface of the protrusion 3b.

[0095] The lower region of the partition structure 51 can be disposed on the base 3a, and can be disposed between the protrusions 3b that are adjacent to each other in the first horizontal direction (X direction) within the protrusions 3b.

[0096] In the protruding portion 3b, the upper surface of the protruding portion 3b located below the channel layer 9 can be located at a higher level than the upper surface of the protruding portion 3b located below the source / drain region 54.

[0097] Each source / drain region 54 may include a portion of the upper surface of the contact protrusion 3b and an extension 54e that contacts the partition structure 51 and extends between the protrusion 3b and the partition structure 51.

[0098] The height difference between the lower end of the extension 54e of each source / drain region 54 and the upper surface of the protrusion 3b can be about 5 nm or less.

[0099] The upper surface of the protrusion 3b located below the channel layer 9 and the gate electrode 81 can be located at a higher level than the upper surface of the element isolation insulating pattern 26 located below the gate electrode 81.

[0100] The source / drain region 54 may include a portion overlapping the protrusion 3b and a portion overlapping the component isolation insulating pattern 26. The upper surface of the component isolation insulating pattern 26, which overlaps with and is disposed below the source / drain region 54, may be disposed at a higher level than the upper surface of the protrusion 3b disposed below the source / drain region 54. The component isolation insulating pattern 26 may include silicon oxide.

[0101] The semiconductor device 1 may further include residual spacers 42b disposed between the upper surface of the element isolation insulating pattern 26 below the source / drain region 54 and the source / drain region 54. The residual spacers 42b may include the same material as the gate spacers 42a. The residual spacers 42b may include a first spacer material layer 39 and a second spacer material layer 36, the second spacer material layer 36 being disposed between the side surface of the first spacer material layer 39 and the source / drain region 54, and between the lower surface of the first spacer material layer 39 and the upper surface of the element isolation insulating pattern 26.

[0102] The semiconductor device 1 may further include an insulating pad 18 that covers both side surfaces of the partition structure 51 in the horizontal direction. The insulating pad 18 may cover both side surfaces of the partition structure 51 in the horizontal direction and may extend to cover the lower surface of the partition structure 51. The insulating pad 18 may be disposed between the protrusion 3b and the partition structure 51 and between the partition structure 51 and the substrate 3a. The insulating pad 18 may be disposed below the insulating pattern 72.

[0103] The insulating pad 18 may include oxides. For example, the insulating pad 18 may include silicon oxide.

[0104] In one or more embodiments, the insulating pattern 72 may extend from the insulating pad 18.

[0105] In one or more embodiments, the upper surface 18S of the insulating pad 18 that contacts the insulating pattern 72 may be formed at a level lower than the level of the upper surface of the protrusion 3b.

[0106] In one or more embodiments, when the insulating pattern 72 and the insulating pad 18 are formed of the same material, the boundary between the insulating pattern 72 and the insulating pad 18 may be indistinct. For example, the insulating pattern 72 and the insulating pad 18 may be formed of the same material (e.g., silicon oxide).

[0107] Semiconductor device 1 may further include an etch stop layer 60 and an interlayer insulating layer 63. The etch stop layer 60 may be disposed on the upper surface of the element isolation insulating pattern 26, the source / drain region 54, the separator structure 51, and the side surface of the gate spacer 42a. The etch stop layer 60 may include SiN, SiCN, SiBN, or SiOCN. The interlayer insulating layer 63 may include at least one of silicon oxide or a low-k dielectric. The low-k dielectric may be a dielectric having a dielectric constant lower than that of silicon oxide.

[0108] The semiconductor device 1 may further include a gate cap pattern 84 disposed on the gate electrode 81 and the spacer structure 51 between the gate electrodes 81. The gate cap pattern 84 may include a nitride-based insulating material.

[0109] The semiconductor device 1 may further include a gate separator pattern 86 that extends through a gate cap pattern 84, passes between the gate electrode 81 of the second transistor structure T2 and the gate electrode 82 of the third transistor structure T3, and through the gate dielectric structure 79, and extends into the element isolation insulating pattern 26. The gate separator pattern 86 may include a nitride-based insulating material.

[0110] In one or more embodiments, the insulating spacer 45 can prevent leakage current between source / drain regions 54 that are adjacent to each other in the second horizontal direction (Y direction) and adjacent to the separation structure 51.

[0111] In one or more embodiments, the insulating spacer 45 can prevent bridging faults that occur when source / drain regions 54 that are adjacent to each other in the second horizontal direction (Y direction) and adjacent to the separation structure 51 are connected to each other.

[0112] In one or more embodiments, the insulating spacer 45 can prevent leakage current between the edge of the gate electrode 81 adjacent to the partition structure 51 and the source / drain region 54, such as Figure 1B The plan view is shown in the diagram.

[0113] In one or more embodiments, the distance between the gate electrode 81 and the partition structure 51 may be smaller than the distance between the channel layer 9 and the partition structure 51. Therefore, since the area where the gate electrode 81 and the channel layer 9 face each other can be increased, the gate control capability of the transistor including the gate electrode 81 and the channel layer 9 can be improved.

[0114] Next, various modified example embodiments of the elements of the above embodiments will be described. The various modified example embodiments of the elements described below will mainly describe the modified or replaced elements. Descriptions of aspects that are the same as or similar to those described above may be omitted. In addition, the elements that can be modified or replaced as described below are described with reference to the accompanying drawings, but the modified or replaced elements can be combined with each other or with the elements described above to form a semiconductor device 1 according to one or more embodiments.

[0115] Figure 6 The above is shown Figure 1B An enlarged plan view of a modified example of the second dielectric portion 75b in the diagram.

[0116] In one or more embodiments, reference Figure 6 The aforementioned second dielectric portion ( Figure 1B and Figure 5B 75b) in the text can be replaced with, for example: Figure 6 The second dielectric portion 175b shown has a reduced thickness. Therefore, the aforementioned gate dielectric structure 79 (see...) Figure 1A , Figure 1B , Figure 3A , Figure 3B , Figure 5A and Figure 5B It can be replaced by a gate dielectric structure 179 that includes a second dielectric portion 175b with reduced thickness.

[0117] The second dielectric portion 175b may have a thickness smaller than that of the second gate dielectric layer 77.

[0118] The second dielectric portion 175b may have a thickness smaller than that of the second portion 72b of the insulating pattern 72.

[0119] Figure 7 The above is shown Figure 1B An enlarged plan view of a modified example of the second part 72b of the insulating pattern 72 in the diagram.

[0120] In one or more embodiments, reference Figure 7 Part II, 72b (see above) Figure 1B ) can be replaced with, for example Figure 7 The second portion 172b shown has a reduced thickness. Therefore, the aforementioned insulating pattern 72 (see...) Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A and Figure 3B ) can be replaced with an insulating pattern 172 that includes a second portion 172b with reduced thickness.

[0121] The second part 172b may have a thickness smaller than that of the second gate dielectric layer 77.

[0122] The second part 172b may have a smaller thickness than the second dielectric part 75b.

[0123] Figure 8 It is used to explain the above. Figure 3B An enlarged cross-sectional view of a modified example of the insulating pattern 72 in the diagram.

[0124] In one or more embodiments, reference Figure 8 Insulation pattern 72 (see Figure 3A and Figure 3B The insulating pattern 272 can be replaced by an insulating pattern 272 spaced apart from each other in the vertical direction (Z direction). The insulating pattern 272 can be disposed between the channel layer 9 and the partition structure 51. The gate dielectric structure 79 can contact the partition structure 51. For example, the second gate dielectric layer 77 of the gate dielectric structure 79 can contact the first partition pattern 21 of the partition structure 51.

[0125] The thickness of each insulating pattern 272 in the vertical direction (Z direction) can be less than the thickness of each channel layer 9 in the vertical direction (Z direction).

[0126] Figure 9 This is to show the above Figure 8 An enlarged cross-sectional view of a modified example of insulation pattern 272 in the diagram.

[0127] In one or more embodiments, reference Figure 9 Insulation pattern 272 (see Figure 8 ) can be replaced with, for example Figure 9 The insulating pattern 372 is shown. The thickness of each insulating pattern 372 may be equal to or greater than the thickness of each channel layer 9.

[0128] Figure 10 The above is shown Figure 3B An enlarged cross-sectional view of a modified example of the gate dielectric structure 79.

[0129] In one or more embodiments, reference Figure 10 The aforementioned gate dielectric structure 79 (see above) Figure 3B The gate dielectric structure 179 can be replaced by a gate dielectric structure 179 surrounding each channel layer 9. For example, the gate dielectric structure 179 can cover the first side surface 9S1 and the second side surface 9S2 of each channel layer 9 facing each other in the first horizontal direction (X direction), the upper surface of each channel layer 9, and the lower surface of each channel layer 9. Therefore, the gate dielectric structure 179 can be disposed between the channel layer 9 and the separator structure 51. (This can be omitted.) Figure 3B The insulating pattern 72 described in the text.

[0130] The aforementioned second gate dielectric layer 77 (see above) Figure 3B The first gate dielectric layer 75 can be replaced by a second gate dielectric layer 177 surrounding each channel layer 9 in the first horizontal direction (X direction), and the aforementioned first gate dielectric layer 75 (see...) Figure 3B The gate dielectric structure 179 can be replaced by a first gate dielectric layer 175 disposed between the channel layer 9 and the second gate dielectric layer 177. The gate dielectric structure 179 may include the first gate dielectric layer 175 and the second gate dielectric layer 177.

[0131] Figure 11 The above is shown Figure 10 An enlarged cross-sectional view of the gate dielectric structure 179 and the modified gate electrode 81 described above.

[0132] In one or more embodiments, reference Figure 11 The aforementioned second gate dielectric layer 177 (see above) Figure 10 The first gate dielectric layer 175 can be replaced by a second gate dielectric layer 277, which includes a first dielectric portion 277a surrounding the channel layer 9 in the first horizontal direction (X direction) and a second dielectric portion 277b spaced apart from the first dielectric portion 277a and in contact with the separation structure 51. (See also: [link to first gate dielectric layer 175]) Figure 10 The gate dielectric structure 179 described above can be replaced by a first gate dielectric layer 275 disposed between the first dielectric portion 277a and the channel layer 9. Therefore, the gate dielectric structure 179 described above (see...) Figure 10 It can be replaced by a gate dielectric structure 279 including a first gate dielectric layer 275 and a second gate dielectric layer 277.

[0133] The aforementioned gate electrode 81 (see above) Figure 10 The gate electrode 181 can be replaced by a gate electrode 181, which includes an extension 181E extending between the first dielectric portion 277a and the second dielectric portion 277b. As described above, the gate electrode 181 may include: a lower electrode portion 181L disposed below the lower surface of the lower channel layer 9L; intermediate electrode portions 181M1, 181M2, and 181M3 disposed between adjacent channel layers 9 in the vertical direction (Z direction); and an upper electrode portion 181U disposed on the upper surface of the upper channel layer 9U. The extension 181E of the gate electrode 181 can extend from the lower electrode portion 181L, the intermediate electrode portions 181M1, 181M2, and 181M3, and the upper electrode portion 181U to the space between the second dielectric portion 277b and the first dielectric portion 277a.

[0134] Since the gate electrode 181 can surround each channel layer 9 in the first horizontal direction (X direction), the gate control capability of the transistor including the gate electrode 181 and the channel layer 9 can be improved.

[0135] Next, we will refer to Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16 An exemplary example of an interconnect structure that is electrically connected to a transistor element.

[0136] Figure 12 , Figure 13 and Figure 14 This is a cross-sectional view illustrating a semiconductor device according to one or more embodiments. Reference Figure 12 , Figure 13 and Figure 14 The interconnect structure electrically connected to the gate electrodes 81 and 82 and the source / drain regions 54 and 57 described above will be described. Figure 12 It is shown in it Figure 3A The insulating pattern 72 in the image was replaced with... Figure 7 A cross-sectional view of the interconnection structure of the insulating pattern 172 described in [the text]. Figure 3A In the cross-sectional structure, this interconnect structure is electrically connected to the gate electrodes 81 and 82. Figure 13 It is shown in Figure 4 A cross-sectional view of the interconnect structure electrically connected to source / drain regions 54 and 57 in the cross-sectional structure, and Figure 14 It is shown in Figure 5A A cross-sectional view of the interconnect structure electrically connected to source / drain regions 54 and 57 in the cross-sectional structure.

[0137] In one or more embodiments, reference Figure 12 , Figure 13 and Figure 14 The upper insulating layer 90 can be disposed on the gate cap pattern 84 and the interlayer insulating layer 63. A gate contact plug 92g can be disposed through the upper insulating layer 90 and the gate cap pattern 84 and connected to the gate electrodes 81 and 82. A front source / drain contact plug 92sd can be disposed through the upper insulating layer 90, the interlayer insulating layer 63 and the etch stop layer 60 and connected to the source / drain regions 54 and 57.

[0138] The gate connection interconnect 94g connected to the gate contact plug 92g and the front source / drain connection interconnect 94sd connected to the front source / drain contact plug 92sd can be disposed on the upper insulating layer 90.

[0139] An upper capping insulation structure 96 covering the gate interconnect 94g and the front source / drain interconnect 94sd can be disposed on the upper insulating layer 90.

[0140] refer to Figure 15 The interconnection structure electrically connected to the aforementioned source / drain regions 54 and 57 will be described. Figure 15 It is shown in Figure 4 A cross-sectional view of the interconnect structure electrically connected to source / drain regions 54 and 57 in the cross-sectional structure.

[0141] In one or more embodiments, reference Figure 15 The aforementioned base 3a and protruding portion 3b may be a base 103a and protruding portion 103b comprising insulating material.

[0142] The upper insulating layer 190 may be disposed on the interlayer insulating layer 63. A front source / drain contact plug 192sd may be disposed through the upper insulating layer 190, the interlayer insulating layer 63 and the etch stop layer 60 and connected to some of the source / drain regions 54 and 57, and a rear source / drain contact plug 292sd may be disposed through the substrate 103a and the protrusion 103b and connected to the other source / drain regions 54 and 57.

[0143] The front source / drain interconnect 194sd, which is connected to the front source / drain contact plug 192sd, can be disposed on the upper insulating layer 190.

[0144] An upper cover insulation structure 196 covering the front source / drain interconnect 194sd can be disposed on the upper insulation layer 190.

[0145] The rear source / drain interconnect 294sd, which is connected to the rear source / drain contact plug 292sd, can be located below the substrate 103a.

[0146] The rear cover insulation structure 296 covering the source / drain interconnect 294sd can be disposed below the substrate 103a.

[0147] refer to Figure 16 The interconnection structure electrically connected to the aforementioned source / drain regions 54 and 57 will be described. Figure 16 It is shown in Figure 4 A cross-sectional view of the interconnect structure electrically connected to source / drain regions 54 and 57 in the cross-sectional structure.

[0148] In one or more embodiments, reference Figure 16 The aforementioned base 3a and protruding portion 3b may be a base 103a and protruding portion 103b comprising insulating material.

[0149] The upper insulating layer 390 can be disposed on the interlayer insulating layer 63.

[0150] A front source / drain contact plug 392sd can be provided that penetrates the upper insulating layer 390, the interlayer insulating layer 63 and the etch stop layer 60 and is connected to some source / drain regions in the source / drain region 57, and a first rear source / drain contact plug 292sdb can be provided that penetrates the substrate 103a and the protrusion 103b and is connected to other source / drain regions in the source / drain region 57.

[0151] A second rear source / drain contact plug 492sda can be provided that penetrates the base 103a and the protrusion 103b and is simultaneously connected to the source / drain areas 54 disposed on both sides of the first dividing pattern 21 in the horizontal direction.

[0152] The front source / drain connection interconnect 394sd, which is electrically connected to the front source / drain contact plug 392sd, can be disposed on the upper insulating layer 390.

[0153] The upper cover insulation structure 396 covering the front source / drain interconnect 394sd can be disposed on the upper insulation layer 390.

[0154] A first rear source / drain connection interconnect 494sdb electrically connected to a first rear source / drain contact plug 492sdb and a second rear source / drain connection interconnect 494sda electrically connected to a second rear source / drain contact plug 492sda can be disposed below the substrate 103a.

[0155] A rear cover insulation structure 496 covering the first rear source / drain interconnect 494sdb and the second rear source / drain interconnect 494sda can be disposed below the substrate 103a.

[0156] Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 , Figure 24A , Figure 24B , Figure 24C , Figure 25 , Figure 26A , Figure 26B , Figure 26C , Figure 27A , Figure 27B , Figure 28 , Figure 29 , Figure 30 , Figure 31A , Figure 31B , Figure 31C , Figure 32A , Figure 32B , Figure 33A , Figure 33B , Figure 34 and Figure 35 This is a diagram illustrating a method for manufacturing a semiconductor device according to one or more embodiments.

[0157] Figures 17 to 23 , Figure 24A , Figure 26A , Figure 31A , Figure 32A , Figure 34 and Figure 35 It shows along Figure 1A and Figure 2B A cross-sectional view of the region intercepted by line I-I'. Figure 24B , Figure 26B , Figure 27A , Figure 29 , Figure 31B , Figure 32B and Figure 33A It shows along Figure 1A and Figure 2A A cross-sectional view of the region intercepted by line II-II'. Figure 24C , Figure 26C , Figure 27B , Figure 31C and Figure 33B It shows along Figure 1A and Figure 2A A cross-sectional view of the region intercepted by line III-III', and Figure 25 , Figure 28 and Figure 30 This is a plan view illustrating a method for manufacturing a semiconductor device according to one or more embodiments. Figure 25 , Figure 28 and Figure 30 The above is from Figure 3A , Figure 3B , Figure 4 , Figure 5A and Figure 5B The "H2" in the diagram indicates the second altitude level (H2) of the plan.

[0158] refer to Figure 17 A sacrificial layer 6 and a channel layer 9 can be formed and alternately stacked on the substrate 3. The bottommost layer of the sacrificial layer 6 and the channel layer 9 can be the bottommost sacrificial layer 6, and the topmost layer can be the topmost channel layer 9. The substrate 3 can be a semiconductor substrate. For example, the substrate 3 can be a single-crystal silicon substrate.

[0159] The channel layer 9 can be a single-crystal silicon (Si) layer formed by an epitaxial growth process. The sacrificial layer 6 can be a single-crystal silicon-germanium (SiGe) layer formed by an epitaxial growth process.

[0160] The capping layer 15 can be formed on the sacrificial layer 6 and the channel layer 9. The capping layer 15 can be formed of a material different from the material of the sacrificial layer 6 and the channel layer 9.

[0161] refer to Figure 18Mask patterns 16a and 16b can be formed, comprising a first mask layer 16a and a second mask layer 16b sequentially stacked on a capping layer 15. An etching process using mask patterns 16a and 16b as etching masks can be performed to form trenches 17a and 17b penetrating the sacrificial layer 6 and the channel layer 9 and extending into the substrate 3. Through trenches 17a and 17b, the substrate 3 can be formed from a substrate 3a and a protrusion 3b protruding from the substrate 3a, and the sacrificial layer 6 and the channel layer 9 retained on the protrusion 3b can form a stacked pattern 12. Each stacked pattern 12 can include a sacrificial layer 6 and a channel layer 9. Trenches 17a and 17b can include a first trench 17a and a second trench 17b alternately arranged in a first horizontal direction (X direction). Each of trenches 17a and 17b can extend in a second horizontal direction (Y direction) perpendicular to the first horizontal direction (X direction). In the first horizontal direction (X direction), each first groove 17a may have a width smaller than that of each second groove 17b.

[0162] An insulating pad 18 can be formed that conformally covers the inner walls of trenches 17a and 17b and covers mask patterns 16a and 16b. The insulating pad 18 can be formed of silicon oxide.

[0163] A first insulating layer 20 may be formed on the insulating pad 18. The first insulating layer 20 may fill the first trench 17a on the insulating pad 18 and conformally cover the second trench 17b. The first insulating layer 20 may be formed of SiN, SiOCN, SiBN or SiCN.

[0164] refer to Figure 19 The first separating insulating layer 20 can be etched isotropically to form a first separating pattern 21 retained within the first trench 17a. The upper surface of the first separating pattern 21 can be formed at a height level higher than the height level of the uppermost trench layer in the trench layer 9.

[0165] refer to Figure 20 The insulating pad 18 can be etched isotropically. Through isotropic etching, the insulating pad 18 disposed within the second trench 17b and the insulating pad 18 disposed on the mask patterns 16a and 16b can be removed. The insulating pad 18 can be retained to cover the side and bottom surfaces of the first separating pattern 21.

[0166] refer to Figure 21 A second insulating layer 23a can be formed, which covers the upper surface of the first separating pattern 21 and the insulating pad 18 and conformally covers the inner wall of the second trench 17b. The second insulating layer 23a can be formed of SiN, SiOCN, SiBN or SiCN.

[0167] refer to Figure 22 The second separating insulating layer 23a can be etched isotropically to form a preliminary separating insulating pattern 23b retained on the upper surface of the first separating pattern 21 and the insulating pad 18.

[0168] refer to Figure 23 The component isolation insulating layer can be formed on the resulting structure up to the initial separating insulating pattern 23b. The component isolation insulating layer can be planarized until the capping layer 15 is exposed, and the planarized component isolation insulating layer can be partially etched to form a component isolation insulating pattern 26 filling the lower region of the second trench 17b. The upper surface of the component isolation insulating pattern 26 can be formed at a level lower than the level of the upper surface of the stacked pattern 12. When the component isolation insulating layer is planarized until the capping layer 15 is exposed, mask patterns 16a and 16b can be removed (see...). Figure 22 The initial dividing insulating pattern 23b can be formed into a second dividing pattern 24.

[0169] refer to Figure 24A , Figure 24B and Figure 24C The sacrificial gate lines 27, 30, and 33 can be formed. Each of the sacrificial gate lines 27, 30, and 33 can extend in a first horizontal direction (X direction). Each of the sacrificial gate lines 27, 30, and 33 may include a buffer oxide layer 27, a sacrificial gate electrode layer 30 on the buffer oxide layer 27, and a sacrificial gate mask layer 33.

[0170] refer to Figure 25 , Figure 26A , Figure 26B and Figure 26C Spacer material layers 39 and 36 may be formed, which conformally cover the sacrificial gate lines 27, 30, and 33 and the surfaces exposed between the sacrificial gate lines 27, 30, and 33 through the sacrificial gate lines 27, 30, and 33. Spacer material layers 39 and 36 may include a second spacer material layer 36 and a first spacer material layer 39 on the second spacer material layer 36.

[0171] refer to Figure 25 , Figure 27A and Figure 27BThe spacer material layers 39 and 36 can be anisotropically etched to form gate spacers 42a retained on the side surfaces of the sacrificial gate lines 27, 30, and 33, and residual spacers 42b retained on the element isolation insulating pattern 26. The stacked pattern 12 can then be etched to form a source / drain recess 43. The source / drain recess 43 can extend into the protrusion 3b. The lower surface of the source / drain recess 43 can be formed at a level lower than the level of the lower surface of the stacked pattern 12. The lower surface of the source / drain recess 43 can be formed at a level lower than the level of the lower surface of the residual spacer 42b. A portion of the element isolation insulating pattern 26 can be etched during the formation of the source / drain recess 43. During the formation of the source / drain recess 43, a second partition pattern 24 disposed on the first partition pattern 21 between the protrusions 3b can be etched and removed, and the first partition pattern 21 and the insulating pad 18 can be partially etched to lower their upper surfaces.

[0172] refer to Figure 28 and Figure 29 This allows for partial etching of the insulating pad 18. Therefore, in situations such as... Figure 28 In the plan view shown, the insulating pad 18 can be formed to have two concave side surfaces in the second horizontal direction (Y direction), and as shown in the figure... Figure 29 In the cross-sectional view shown, the insulating pad 18 can be formed with a concave upper surface. In the second horizontal direction (Y direction), the width of the insulating pad 18 can be smaller than the width of each stacked pattern 12.

[0173] refer to Figure 30 , Figure 31A , Figure 31B and Figure 31C ,like Figure 18 and Figure 29 As shown, after partially etching the insulating pad 18, a spacer material layer 44 can be conformally formed. The spacer material layer 44 may include at least one of SiN, SiOCN, SiOC, SiBN, or SiCN.

[0174] refer to Figure 32A and Figure 32B A third partition pattern 50 can be formed. The third partition pattern 50 can penetrate the spacer material layer 44 and the sacrificial gate lines 27, 30 and 33 and can contact the second partition pattern 24, and can penetrate the spacer material layer 44 between the sacrificial gate lines 27, 30 and 33 and can contact the first partition pattern 21. Therefore, a partition structure 51 including the first partition pattern 21, the second partition pattern 24 and the third partition pattern 50 can be formed respectively.

[0175] Together Figure 1A , Figure 1B , Figure 2A and Figure 2B refer to Figure 33A and Figure 33B The spacer material layer 44 can be etched isotropically to form the insulating spacer 45 (see [reference]). Figure 1B and Figure 2B Then, a source / drain formation process can be performed to form source / drain regions 54 and 57 within the source / drain recess 43. Forming source / drain regions 54 and 57 may include using a selective epitaxial growth process. Insulating spacer 45 (see [link to documentation]). Figure 1B and Figure 2B This can prevent bridging failures between source / drain regions 54 and 57 that are adjacent to each other in the second horizontal direction (Y direction) and adjacent to the separation structure 51.

[0176] refer to Figure 34 The sacrificial gate lines 27, 30, and 33 can be removed to form the gate trench 66. The sacrificial layer 6 exposed by the gate trench 66 can be selectively removed to form an empty space 69.

[0177] refer to Figure 35 After forming the gate trench 66 and the empty space 69, an insulating pattern 172 can be formed. The insulating pattern 172 can be formed by partially etching the insulating pad 18 located at a level higher than the protrusion 3b.

[0178] Figure 35 It shows the formation Figure 7 and Figure 12 The insulating pattern 172 described herein is not limited to this embodiment. For example, the insulating pad 18 disposed at a level higher than the protrusion 3b can be partially etched to form an insulating pattern such as... Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 5A and Figure 5B The insulation pattern 172 shown is as follows: Figure 8 The insulation pattern shown is 272, or as shown in the figure. Figure 9 The insulation pattern shown is 372.

[0179] In one or more embodiments, the insulating pad 18 disposed at a level higher than the level of the protrusion 3b can be removed to form a space between the channel layer 9 and the partition structure 51. Figure 10 The empty space shown or as Figure 11 The empty space shown.

[0180] Then, a first gate dielectric layer 75 can be formed. Forming the first gate dielectric layer 75 may include: oxidizing the exposed surfaces of the channel layer 9 and the protrusion 3b; forming an oxide layer; performing a process to densify at least a portion of the oxide layer; and etching a portion of the densified oxide layer. Therefore, the first gate dielectric layer 75 can be formed to include a first dielectric portion 75a and a second dielectric portion 75b, such as... Figure 5B As shown.

[0181] Refer again Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4 , Figure 5A and Figure 5B After forming the first gate dielectric layer 75, a second gate dielectric layer 77 can be formed, which conformally covers the inner walls of the gate trench 66 and the empty space 69. Next, gate electrodes 81 and 82 can be formed on the second gate dielectric layer 77, which fill the empty space 69 and partially fill the gate trench 66, and a gate capping pattern 84 can be formed on the gate electrodes 81 and 82.

[0182] A gate separator pattern 86 may be formed, which extends through the gate cap pattern 84, passes between the gate electrode 81 of the second transistor structure T2 and the gate electrode 82 of the third transistor structure T3, and through the gate dielectric structure 79, and extends into the element isolation insulating pattern 26. The gate separator pattern 86 may include a nitride-based insulating material.

[0183] According to one or more embodiments, a semiconductor device including a separator structure and a transistor structure can be provided.

[0184] In one or more embodiments, the transistor structure may include insulating spacers spaced apart from each other between source / drain regions adjacent to the partition structure. The insulating spacers prevent leakage current between source / drain regions adjacent to the partition structure and prevent bridging faults that connect the source / drain regions to each other.

[0185] In one or more embodiments, the insulating spacer can prevent leakage current from occurring between the edge of the gate electrode of the transistor structure adjacent to the partition structure and the source / drain region.

[0186] In one or more embodiments, the distance between the gate electrode and the separator structure of the transistor structure can be smaller than the distance between the channel layer and the separator structure of the transistor structure. Therefore, since the area where the gate electrode and the channel layer face each other can be increased, the gate control capability of the transistor including the gate electrode and the channel layer can be improved.

[0187] Each embodiment described above is not excluded from being associated with one or more features of another example or embodiment also provided herein or not provided herein but consistent with this disclosure.

[0188] Although this disclosure has been specifically shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: Separation structure; as well as The transistor structure is located on the side surface of the partition structure. The transistor structure includes: First source / leakage region; The second source / drain region is spaced apart from the first source / drain region; A channel layer, connected to the first source / drain region and the second source / drain region, the channel layers being spaced apart in a first direction; Gate electrodes, covering each of the channel layers; A gate dielectric structure is provided between the first source / drain region and the second source / drain region and the gate electrode, between the channel layer and the gate electrode, and between the partition structure and the gate electrode; and The first insulating spacer and the second insulating spacer are spaced apart from each other, adjacent to the separation structure, and located between the first source / drain region and the second source / drain region.

2. The semiconductor device according to claim 1, wherein, The transistor structure also includes gate spacers on the side surface of the gate electrode, and Each of the first insulating spacer and the second insulating spacer is spaced apart from the gate spacer at a level lower than the level of the upper surface of the uppermost channel layer in the channel layer.

3. The semiconductor device according to claim 1, wherein, The first insulating spacer contacts the first source / drain region, and The second insulating spacer contacts the second source / drain region.

4. The semiconductor device according to claim 3, wherein, The first insulating spacer and the second insulating spacer are in contact with the separation structure.

5. The semiconductor device according to claim 1, wherein, Each of the channel layers includes a first side surface facing the partition structure and a second side surface opposite to the first side surface. The gate electrode covers the lower surface, upper surface, and first side surface of each of the channel layers, and... The gate electrode includes: The lower electrode portion is located below the lower surface of the lowest channel layer in the first direction; The upper electrode portion is located on the uppermost surface of the channel layer in the first direction; and The intermediate electrode portion is located between adjacent channel layers in the first direction within the channel layer.

6. The semiconductor device according to claim 5, wherein, The distance between the channel layer and the partition structure is greater than the distance between the intermediate electrode portion and the partition structure.

7. The semiconductor device according to claim 5, wherein, The intermediate electrode portion includes: The first electrode portion between the channel layers adjacent to each other in the first direction; and The second electrode portion extends from the first electrode portion in a second direction toward the orientation of the separating structure, and In the intermediate electrode portion, the thickness of the second electrode portion in the first direction is greater than the thickness of the first electrode portion in the first direction.

8. The semiconductor device according to claim 5, further comprising an insulating pattern, in, The insulating pattern includes a first portion and a second portion extending from the first portion. Wherein, the first portion of the insulating pattern is between the channel layer and the separator structure, and The second portion of the insulating pattern is located between the lower electrode portion and the partition structure, between the intermediate electrode portion and the partition structure, and between the upper electrode portion and the partition structure.

9. The semiconductor device according to claim 8, wherein, The channel layer faces the partition structure on a third direction intersecting the first direction. The first source / drain region and the second source / drain region are spaced apart from each other in a fourth direction perpendicular to the third direction. Wherein, the first insulating spacer and the second insulating spacer are spaced apart from each other in the fourth direction, and In the insulating pattern, the thickness of each of the first portions in the third direction is greater than the thickness of each of the second portions in the third direction.

10. The semiconductor device of claim 5, further comprising an insulating pattern between the channel layer and the separation structure, the insulating pattern being spaced apart in the first direction.

11. The semiconductor device according to claim 10, wherein, The partition structure includes a first insulating material, and The insulating pattern includes a second insulating material that is different from the first insulating material.

12. The semiconductor device according to claim 1, wherein, The partition structure includes: A first separation region is adjacent to the gate electrode, the gate dielectric structure, and the channel layer; and The second partition region is adjacent to the first source / drain region and the second source / drain region, and The first partition region of the partition structure includes: A first dividing pattern, wherein the lower surface of the first dividing pattern is horizontally lower than the level of the lowest channel layer in the channel layers, and the upper surface of the first dividing pattern is horizontally higher than the level of the uppermost channel layer in the channel layers; and The second dividing pattern covers the upper surface of the first dividing pattern and has a width greater than that of the first dividing pattern.

13. The semiconductor device according to claim 12, wherein, The first partition region is spaced apart from the channel layer, and The second separation region contacts the first source / drain region and the second source / drain region.

14. A semiconductor device, comprising: A partition structure having a first side surface and a second side surface opposite to the first side surface in a first direction; A first transistor structure is located on the first side surface of the partition structure; as well as The second transistor structure is located on the second side surface of the partition structure. Each of the first transistor structure and the second transistor structure includes: The channel layers are stacked and spaced apart from each other in a second direction intersecting the first direction, and each has a first side surface facing the partition structure and a second side surface opposite to the first side surface; Gate electrodes covering the upper surface, lower surface, and first side surface of each of the channel layers; and A gate dielectric structure is located between the channel layer and the gate electrode, and between the partition structure and the gate electrode. In each of the first transistor structure and the second transistor structure, the gate electrode includes: The lower electrode portion is located below the lower surface of the lowest channel layer in the channel layer in the second direction; The upper electrode portion is located on the uppermost surface of the channel layer in the second direction; and The intermediate electrode portion is located between adjacent channel layers in the second direction within the channel layer, and Wherein, the distance between the middle electrode portion of the gate electrode of the first transistor structure and the middle electrode portion of the gate electrode of the second transistor structure is less than the distance between the uppermost channel layer of the first transistor structure and the uppermost channel layer of the second transistor structure.

15. The semiconductor device according to claim 14, wherein, Each of the first transistor structure and the second transistor structure includes: The first source / drain region and the second source / drain region are spaced apart from each other in a third direction perpendicular to the first direction; and The first insulating spacer and the second insulating spacer are adjacent to the separation structure between the first source / drain region and the second source / drain region, and are spaced apart from each other in the third direction. In each of the first transistor structure and the second transistor structure, the channel layer is located between the first source / drain region and the second source / drain region.

16. The semiconductor device according to claim 15, wherein, Each of the first transistor structure and the second transistor structure further includes an insulating pattern between the first insulating spacer and the second insulating spacer, and The materials of the first insulating spacer and the second insulating spacer are different from the material of the insulating pattern.

17. A semiconductor device, comprising: A partition structure having a first side surface and a second side surface opposite to the first side surface in a first direction; A first transistor structure is located on the first side surface of the partition structure; as well as The second transistor structure is located on the second side surface of the partition structure. Each of the first transistor structure and the second transistor structure includes: The first source / drain region and the second source / drain region are spaced apart from each other in a second direction perpendicular to the first direction; A channel layer, connected to the first source / drain region and the second source / drain region, the channel layers being spaced apart from each other in a third direction intersecting the first direction and the second direction, and each having a first side surface facing the separation structure and a second side surface opposite to the first side surface; Gate electrodes covering the upper surface, lower surface, and first side surface of each of the channel layers; and A gate dielectric structure is provided between the first source / drain region and the second source / drain region and the gate electrode, between the channel layer and the gate electrode, and between the separator structure and the gate electrode. The separation structure includes a first separation region between the gate electrode of the first transistor structure and the gate electrode of the second transistor structure, and The first partition includes: A first separating pattern is located between the channel layers of the first transistor structure and the second transistor structure, and has a first width; and The second dividing pattern is located at a level higher than the channel layer, on top of the first dividing pattern, and has a second width greater than the first width.

18. The semiconductor device according to claim 17, wherein, The side surface of the second dividing pattern includes a curved portion between a first side surface extending from the upper surface of the second dividing pattern and a second side surface extending from the first side surface and inclined. The height difference between the curved portion and the upper surface of the uppermost channel layer is greater than the distance between the channel layer and the partition structure.

19. The semiconductor device according to claim 17, wherein, In each of the first transistor structure and the second transistor structure The gate electrode includes an intermediate electrode portion within the channel layers, located between channel layers adjacent to each other in the third direction, and The distance between the intermediate electrode portion and the partition structure is less than the distance between the channel layer and the partition structure.

20. The semiconductor device of claim 17, further comprising an insulating pad covering a lower region of the first side surface and the second side surface of the separating structure. in, The first source / drain region and the second source / drain region contact the separating structure and the upper surface of the insulating pad, and The channel layer is spaced apart from the partition structure.

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