Wafer film repairing method and device for process interruption, electronic equipment and storage medium

Abstract

The present application relates to the technical field of semiconductor chip manufacturing, and in particular to a wafer film repairing method and device for process interruption, electronic equipment and storage medium. The technical scheme core is: after interruption triggering, three types of anchor point data of mechanical cavity posture, formula execution pointer and equivalent process progress are synchronously captured, reliable storage is realized through WAL mechanism combined with double submission mark and verification; before resuming work, the equivalent cavity steady state is reconstructed, the film repairing parameters are calculated based on the anchor point data, and the constrained compensation formula is generated; the precise resending is realized through PathID multiplexing historical track, the closed loop verification is formed by cooperating with online measurement, and the repair quality and production continuity are guaranteed by combining double release thresholds and double queue scheduling. The present application can reduce the direct scrappage rate after interruption from 8.0% to 1.5%, reduce the daily loss of production capacity by 80%, and improve the good product rate to 97.8%, thereby significantly reducing the production cost, improving the process stability, realizing the full link traceability, and being suitable for the precise machining scene such as semiconductor film deposition.

Description

Technical Field

[0001] This invention relates to the field of semiconductor chip manufacturing technology, and more specifically to a wafer resurfacing method, apparatus, electronic device, and storage medium for process interruption. Background Technology

[0002] In the field of integrated circuit manufacturing, thin film deposition processes (such as CVD, PECVD, ALD, PVD, etc.) are the core technologies for forming dielectric layers, barrier layers, conductive layers, and passivation layers. Mass production typically employs a cluster-style equipment structure (EFEM + Loadlock + multiple PM chambers), executing the complete process flow step-by-step according to a recipe. This includes pretreatment (vacuuming, heating, surface activation), the main deposition stage (plasma treatment, precursor pulse, holding pressure, etc.), and post-treatment (cooling, degassing, wafer unloading), ensuring the precise construction of the chip's multi-layered structure.

[0003] In actual production, the deposition process is highly susceptible to interruptions (such as alarms, aborts, and interlocks) due to various factors including equipment, processes, and production organization. Typical causes include equipment-side failures (MFC / pressure control instability, plasma extinction, power supply anomalies, etc.), process-side fluctuations (precursor pressure drop, out-of-range formulation parameters, cavity memory effect), and production-side adjustments (batch switching, MES communication outages, etc.). When an interruption occurs, the wafer is often in a "partially deposited / semi-finished" state, and its surface chemical state and cavity environment have deviated from their initial state, posing a significant challenge to subsequent processing.

[0004] The traditional methods for handling interrupted wafers in current mass production lines have significant drawbacks: direct scrapping is simple to operate but costly and can easily lead to large fluctuations in yield and capacity; manually removing the wafers and restarting the entire process is not feasible due to the lack of a "process odometer" to accurately locate the interruption, and temporary restarts can cause process parameter drift and interface connection errors, increasing the risk of invalid processing and defects; attempting to restore wafers in the same or different cavities faces problems such as difficulty in reproducing the cavity state, missing film replenishment metering, and poor batch consistency, which can result in uneven film thickness or even electrical performance mismatch, failing to meet the requirements of advanced processes.

[0005] In multi-cavity concurrent production scenarios, a single cavity interruption can trigger a chain reaction: robot / Loadlock scheduling limitations cause other cavities to slow down and stop; cross-cavity migration requires additional time for cavity calibration and status adjustment; and passive changes in batch strategies further amplify systemic capacity losses. Taking the 12-inch PECVDSiN process as an example, the actual losses caused by traditional handling methods are significant: the wafer scrap rate after an interruption is about 8%, with a direct economic loss of 40,000 yuan per batch; a single interruption adds 10 minutes of time, and an average of 5 interruptions per day can result in a daily capacity loss of 37.5 wafers; forced recovery without parameter compensation reduces the yield rate from 98% to 95%, resulting in an additional 300 defective wafers when producing 10,000 wafers per month.

[0006] A thorough analysis of the underlying technical issues reveals five core problems: lack of measurable progress anchors directly related to film thickness, making it impossible to accurately estimate the amount of material deposited; the cavity memory effect after interruption leads to irreproducible reaction rates; the irreversible chemical state of the wafer surface makes continued deposition prone to forming interlayer defects; the lack of model support for cross-cavity consistency makes it difficult to guarantee batch uniformity when switching cavities; and the lack of decoupling between scheduling and process, leaving only a binary solution of stopping the line or restarting the entire process.

[0007] Existing remedial solutions have failed to achieve effective breakthroughs: manual experience-based film repair suffers from poor consistency and lacks traceability; offline metrology combined with reprocessing increases contamination risks and turnaround time; fixed bias compensation is insufficiently adaptable to cavity and batch differences; process-level anomaly recovery can only achieve "continue running," failing to guarantee "equivalent compliance." Meanwhile, while industry standards support basic functions such as wafer tracking and process pause / resumption, they lack a solidified metrology model and execution loop for "equivalent film repair"; online metrology technology, while capable of real-time thickness monitoring, cannot address post-interruption state reconstruction and interface repair issues; the cycle-count thickness controllability advantage of ALD processes is also hampered by the lack of an interruption handling mechanism. These technological bottlenecks prevent existing solutions from meeting the stringent requirements of advanced processes for film thickness, stress, and interface electrical properties, becoming key bottlenecks restricting chip manufacturing yield, capacity, and cost control. Summary of the Invention

[0008] The purpose of this invention is to propose a wafer film repair method, device, electronic device, and storage medium for process interruptions. Without affecting the normal production of other cavities, it constructs an integrated film repair capability of "interruption location - state reconstruction - parameter adaptive compensation - concurrent scheduling and coordination - measurement closed-loop release", ensuring that the interrupted wafer achieves equivalent levels to the original design requirements in key performance indicators such as film thickness, refractive index, chip resistance, and stress.

[0009] According to a first aspect of the present disclosure, a wafer resurfacing method for process interruptions is provided, comprising the following steps: After a process interruption is triggered, three types of anchor point data with the same timestamp are collected and frozen simultaneously within a preset time limit to form three-dimensional anchor points for resuming process calculations; the three types of anchor point data include mechanical cavity posture, formula execution pointer, and equivalent process progress. The 3D anchor point snapshot is persisted in a transactional manner to ensure that it is rolled back to the most recent consistent data point after an abnormal reset or power failure. The wafer is moved out of the process cavity and returned to the designated slot according to the low-contamination trajectory. At the same time, the pending recovery status is written into the scheduling / MES system, and the target cavity identifier and snapshot identifier are bound. Before resuming work, the target cavity is reconstructed. Resuming work is only allowed when the cavity state enters a preset stable window and meets the threshold. When the original cavity is unavailable, the equivalent cavity and the corresponding calibration file are called. Based on the equivalent process progress data in the three-dimensional anchor points, combined with the deposition rate or growth per cycle under the equivalent cavity state ECS, the amount of film replenishment is obtained and a constrained compensation segment is automatically generated. Historical path information is called for retransmission along the same path. The cavity positioning meets the preset tolerance requirements. If the tolerance is exceeded, a second alignment is performed. After the compensation phase is executed, the film-forming effect is confirmed by online measurement equipment. If the deviation exceeds the threshold, the parameters are fine-tuned within a limited number of times within the safety constraints. Establish an independent recovery queue to operate decoupled from the regular production queue, ensuring that other cavities can continue production without line stoppage when a single cavity is interrupted; when consecutive recovery failures reach a threshold, automatically execute a degradation strategy and leave a record. The process and results of wafer recovery are subject to dual release thresholds. When the thresholds are met, the entire data chain is archived to enable traceability and auditing.

[0010] In one embodiment, the mechanical cavity attitude includes r, z, θ, chuck eccentricity, and Notch orientation; the recipe execution pointer includes recipe_id, version hash, step_idx, substep_idx, execution time within a step, and current gas path plasma state; the equivalent process progress includes online thickness estimation, equivalent deposition dose (EDD), or number of completed ALD cycles.

[0011] In one embodiment, the online thickness estimate is obtained as follows: T̂_int=T̂_base+Σ_k(v_ref,k×t_eff,k×K_sense,k) where T̂_base is the reference film thickness, Σ_k is the cumulative summation of multiple deposition-related process segments k; v_ref,k is the calibration rate of this segment under the reference steady state, t_eff,k is the "effective deposition time" of this segment, and K_sense,k is a correction factor (it is recommended to limit the amplitude to suppress noise).

[0012] In one embodiment, the amount of film replenishment includes the required film thickness, the compensation duration, and the number of compensation cycles; The required film thickness is: ΔT = max(0, T0 - T̂_int) The compensation time is: t_comp=clamp(ΔT / v_ECS,0,η·t_step_nom) Compensation cycle number: N_comp=ceil(ΔT / GPC_ECS) where T0 is the target film thickness, T̂_int is the estimated current deposited thickness; v_ECS is the real-time rate or equivalent rate after ECS windowing, η is the compensation upper limit coefficient, t_step_nom is the standard duration of this step in the original Recipe; GPC_ECS is the growth per cycle under ECS conditions; when recovering across cavities, equivalent correction is performed using GPC_ECS=GPC_ref×K_chamber, where GPC_ref is the reference growth per cycle; K_chamber is the cavity state correction coefficient, which comes from the cavity mapping table or calibration file.

[0013] In one embodiment, the equivalent deposition dose (EDD) is suitable for estimating the amount of work done in scenarios where direct thickness measurement is not possible, specifically: EDD = Σ_k(P_RF,k^α·F_prec,k^β·exp(-Ea / (R·T_chuck,k))·Δt_k). Where P_RF,k is the RF power, F_prec,k is the reactant gas flow rate, T_chuck,k is the chuck temperature, Ea is the equivalent activation energy parameter, α and β are empirical exponents; Δt_k is the time increment of the kth process segment; the EDD and film thickness are approximately linearly correlated by calibrating the wafer fitting.

[0014] In one embodiment, the historical path is obtained as follows: PathID=Hash(tool_id||module_id||from_station||to_station||waypoints||v_profile||pose), where tool_id is the machine identifier, module_id is the module identifier, from_station and to_station are the starting station and the target station, respectively, waypoints is the set of key points of the path, v_profile is the motion curve parameter, and pose is the attitude parameter; The historical path PathID and its corresponding timestamp information are synchronously written into the 3D anchor point snapshot to jointly complete the atomic disk storage.

[0015] In one embodiment, the process thresholds include ECS window entry, interlock satisfaction, and compensation segment not exceeding the upper limit; the result thresholds include online thickness and uniformity index.

[0016] According to a second aspect of the present disclosure, a wafer resurfacing system for process interruptions is provided, comprising: The three-dimensional anchor point snapshot acquisition module, after a process interruption is triggered, synchronously acquires and freezes three types of anchor point data with the same timestamp within a preset time limit to form three-dimensional anchor points for resuming process calculations; the three types of anchor point data include mechanical cavity posture, formula execution pointer, and equivalent process progress. The transactional persistent storage module persists the 3D anchor point snapshot in a transactional manner, ensuring that it can be rolled back to the most recent consistent data point after an abnormal reset or power failure. The low-contamination rollback and status marking module moves the wafer out of the process cavity and back to the designated slot according to the low-contamination trajectory, while writing the status to be restored in the scheduling / MES system and binding the target cavity identifier and snapshot identifier. The equivalent cavity state reconstruction and gating module reconstructs the state of the target cavity before resuming operation. It allows resuming operation only when the cavity state enters a preset stable window and meets the threshold. When the original cavity is unavailable, it calls the equivalent cavity and the corresponding calibration file. The film replenishment amount calculation and compensation segment generation module, based on the equivalent process progress data in the three-dimensional anchor points, combined with the deposition rate or growth per cycle under the equivalent cavity state ECS, obtains the film replenishment amount and automatically generates a constrained compensation segment. The same path retransmission and fine positioning module calls historical path information to perform same path retransmission. The cavity positioning meets the preset tolerance requirements. If the tolerance is exceeded, a second alignment is performed. The online confirmation and fine-tuning closed-loop module confirms the film-making effect after the compensation section is executed through online measurement equipment. When the deviation exceeds the threshold, the parameters are fine-tuned within a limited number of times within the safety constraints. The concurrent scheduling isolation and exception fallback module establishes an independent recovery queue and decouples it from the regular production queue to ensure that other cavities can continue to produce normally without line stoppage when a single cavity is interrupted; when continuous recovery failures reach a threshold, a degradation strategy is automatically executed and a record is kept. The end-to-end traceability and dual release module sets dual release thresholds for the recovery wafer process and results. When the thresholds are met, the end-to-end data is archived to achieve traceable auditing.

[0017] According to a third aspect of the present disclosure, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory and running on the memory, wherein the processor executes the program to implement the aforementioned wafer patching method for process interruption.

[0018] According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the aforementioned wafer patching method for process interruption.

[0019] The advantages of the above technical solutions adopted in this invention compared with the prior art are as follows: 1. By capturing the interruption state through 3D interruption anchor points and combining it with ECS state reconstruction and constrained compensation segment generation, precise film replacement of interrupted wafers can be achieved, significantly reducing the scrap rate. Simultaneously, it reduces the direct economic losses caused by interruptions in each batch of wafers, effectively controlling production costs and improving production efficiency.

[0020] 2. Relying on a concurrent scheduling and isolation mechanism, an independent recovery queue is established and decoupled from the regular production queue. An interruption in a single chamber does not affect the normal production of other chambers, avoiding a complete line shutdown or speed reduction. In a scenario with a rated equipment capacity of 45 pieces / hour and an average of 5 interruptions per day, this significantly reduces daily lost capacity, ensuring production continuity and overall capacity output.

[0021] 3. By utilizing the process progress data provided by 3D interruption anchor points and combining it with ECS state reconstruction to ensure the stability of the cavity environment, and with the generation of constrained compensation sections and online measurement fine-tuning closed loop, the intra-batch film thickness fluctuation is effectively reduced, and film thickness uniformity is improved. Simultaneously, the yield is significantly improved, and the number of defective wafers caused by process interruptions is reduced.

[0022] 4. This invention constructs a complete closed loop of "interruption location—state reconstruction—compensation execution—quality verification" through the synergistic effect of core technologies such as three-dimensional interruption anchor points, ECS state reconstruction, constrained compensation segment generation, and concurrent scheduling isolation. Combined with dual release thresholds for both process and results, and end-to-end data archiving, it achieves traceability and auditability of the film-making process, meeting stringent quality control requirements and improving the controllability and reliability of the production process. Attached Figure Description

[0023] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments of this application and their descriptions are used to explain this application and do not constitute an undue limitation of this application.

[0024] Figure 1 This is a flowchart of a wafer resurfacing method for addressing process interruptions. Detailed Implementation

[0025] The present disclosure will be further described below with reference to the accompanying drawings and embodiments.

[0026] It should be noted that the following detailed descriptions are exemplary and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0027] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0028] It should be noted that the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of methods and systems according to various embodiments of this disclosure. It should be noted that each block in a flowchart or block diagram may represent a module, segment, or portion of code, which may include one or more executable instructions for implementing the logical functions specified in the various embodiments. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutively represented blocks may actually be executed substantially in parallel, or they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, may be implemented using a dedicated hardware-based system that performs the specified functions or operations, or using a combination of dedicated hardware and computer instructions.

[0029] Example 1: like Figure 1 As shown, this embodiment provides a wafer resurfacing method for process interruptions, including the following steps: S1. After a process interruption is triggered, three types of anchor point data with the same timestamp are collected and frozen simultaneously within a preset time limit to form three-dimensional anchor points for resuming process calculation; the three types of anchor point data include mechanical cavity posture, formula execution pointer and equivalent process progress. Specifically, when a process interruption event such as Alarm, Abort, Interlock, plasma extinguishing, cavity pressure deviation, or manual pause occurs, three types of anchor point data at the same timestamp are synchronously collected and frozen within a preset time limit (e.g., ≤50ms). These include: ① Mechanical cavity attitude data, covering parameters such as r, z, θ, chuck eccentricity, and Notch orientation; ② Recipe execution pointer data, including recipe_id, version / hash, step_idx, substep_idx, execution time within the step, and current gas path / plasma status; ③ Equivalent process progress data, which can be selected from one or more of the online thickness estimation value T̂_int, equivalent deposition dose EDD, or number of completed ALD cycles N_int.

[0030] S2. Persist in storing the 3D anchor point snapshot in a transactional manner to ensure that after an abnormal reset or power failure, it will be rolled back to the most recent consistent data point; Specifically, the 3D anchor point snapshots collected in step S1 are written to NVRAM or industrial SSDs using a write-alive (WAL) mechanism. The atomicity and consistency of data storage are ensured through a combination of "double commit markers + CRC / hash check". When the system encounters an abnormal reset or power failure, the log is replayed to automatically roll back to the most recently successfully committed snapshot and the corresponding recipe pointer, ensuring that the recovery process can accurately return to a consistent data point, rather than relying solely on volatile memory cache for temporary storage.

[0031] S3. Move the wafer out of the process cavity and back to the designated slot according to the low-contamination trajectory, and write the pending recovery status into the scheduling / MES system, and bind the target cavity identifier and snapshot identifier; Specifically, the wafer is moved out of the process cavity and returned to its original FOUP slot or a dedicated "to be recovered" slot according to a preset low-contamination trajectory (e.g., raising ΔZ, reducing operating speed, avoiding dust and deposition areas). At the same time, the WAIT_RECOVER status is written into the scheduling / MES system, and the unique identifier of the target cavity and the snapshot identifier are bound to form a strong correlation between "slot-status-cavity-snapshot", which effectively avoids cross-contamination and repeated processing problems.

[0032] S4. Before resuming work, the target cavity is reconstructed. Resuming work is only allowed when the cavity state enters the preset stable window and meets the threshold. When the original cavity is unavailable, the equivalent cavity and the corresponding calibration file are called. Specifically, before resuming the process, the target cavity is reconstructed. The process is only allowed to start when the cavity's temperature, pressure, key gas paths, plasma, and other parameters enter the preset quantitative stability window (e.g., temperature fluctuation ≤ ±1.0°C, pressure fluctuation ≤ ±0.2 mTorr, key gas flow rate stabilization time ≥ 3s, OES spectral line intensity fluctuation ≤ ±5%) and continuously meet the threshold requirements. If the original cavity is unavailable, the equivalent cavity mapping table is called to select a suitable alternative cavity, and the equivalent calibration file corresponding to the alternative cavity is loaded. The deposition rate and related process parameters are then specifically modified to ensure consistency across cavities.

[0033] S5. Based on the equivalent process progress data in the three-dimensional anchor points, combined with the deposition rate or growth per cycle under the equivalent cavity state ECS, the amount of film replenishment is obtained and a constrained compensation segment is automatically generated. Specifically, based on the online thickness estimate T̂_int from the 3D anchor point snapshot, the equivalent deposition dose EDD, or the number of completed ALD cycles N_int, combined with the deposition rate v_ECS or growth per cycle GPC_ECS under the equivalent cavity state (ECS), the required film thickness ΔT and the duration or number of compensation cycles are calculated, and a "constrained compensation segment" is automatically generated. The compensation duration, RF power fine-tuning, and MFC flow fine-tuning of this constrained compensation segment are all subject to preset upper limits, such as compensation duration ≤ 30% of the original step size, and power and flow not exceeding the equipment's rated values. The compensation segment can be added to the original recipe as an insert segment (keeping the original recipe_id unchanged and recording the compensation version number), or a Recover-Recipe containing only the compensation segment can be generated independently for the scheduler to call as needed.

[0034] Taking PECVD process as an example, assuming the target film thickness T0 = 80nm, if the online thickness estimate in the 3D anchor snapshot is T̂_int = 63nm, and the deposition rate in the equivalent chamber state (ECS) is v_ECS = 1.20nm / s, then the required film thickness ΔT = T0 - T̂_int = 17nm, corresponding to a compensation segment duration t_comp = ΔT / v_ECS ≈ 14.2s. Setting the compensation upper limit coefficient η = 0.30, and the original process step size t_step_nom = 60s, the upper limit of the compensation duration can be calculated as η・t_step_nom = 18s. Since 14.2s < 18s, and the relevant power and flow parameters of the compensation segment do not exceed the equipment's rated values, this compensation segment meets the constraints and can be executed normally.

[0035] S6. Call historical path information to resend along the same path. The cavity positioning meets the preset tolerance requirements. If the tolerance is exceeded, perform secondary alignment. Specifically, the historical path identifier (PathID) and corresponding attitude parameters (including r, z, θ, and Notch orientation) recorded in the 3D anchor point snapshot are invoked to complete the wafer retransmission according to the same path and attitude as before the interruption. The wafer cavity positioning must meet the preset plane height tolerance and orientation tolerance (e.g., plane height tolerance ΔZ≤±0.1mm, orientation tolerance Δθ≤±0.2°). If the positioning accuracy exceeds the tolerance range, a secondary alignment operation (such as secondary Notch alignment or edge alignment) is triggered first. The re-processing process is started only after the positioning is qualified. The path identifier (PathID) is obtained by hashing the key elements of the path to obtain a unique corresponding PathID. This PathID and the corresponding timestamp information are synchronously written into the 3D anchor point snapshot collected in step S1 to complete the atomic disk storage. In the re-processing recovery stage, only this PathID needs to be referenced to directly reuse the same motion trajectory before the interruption, effectively avoiding the attitude deviation introduced by path replanning and ensuring the consistency of wafer positioning.

[0036] S7. After the compensation section is executed, the film-making effect is confirmed by online measurement equipment. If the deviation exceeds the threshold, the parameters are fine-tuned within a limited number of times within the safety constraints. Specifically, after the compensation stage is completed, the wafer thickness or equivalent process endpoint after film compensation is quickly detected and confirmed using one or more combinations of an online quartz crystal microbalance (QCM), ellipsometry, or optical emission spectrometer (OES), and the deviation between the measured value and the target value is calculated as e=T0-T_meas. When the absolute value of the deviation |e| exceeds the preset threshold (e.g., (|e|>0.5nm), the compensation parameters (such as compensation duration Δt or RF power, mass flow controller MFC parameters) are automatically fine-tuned within the preset safety constraints. At the same time, the number of iterations for parameter fine-tuning is limited (e.g., the number of iterations ≤2 times) to ensure the convergence of film compensation accuracy and controllable production cycle.

[0037] S8. Establish an independent recovery queue to operate decoupled from the regular production queue, ensuring that other cavities can continue production normally without line stoppage when a single cavity is interrupted; when continuous recovery failures reach a threshold, automatically execute a degradation strategy and leave a record. Specifically, an independent "recovery queue" is established, operating decoupled from the regular production queue. Wafers awaiting recovery prioritize occupying the available time window of the target cavity without blocking the normal production process of other cavities. When the number of consecutive recovery failures reaches a preset threshold (e.g., 2 times), the system automatically initiates a degradation strategy, which includes performing secondary compensation with stricter upper limit constraints, adjusting the process to offline measurement, or directly rejecting the wafer. The system also records and archives the reasons for failure and the trigger threshold throughout the entire process, enabling traceable management of abnormal situations.

[0038] S9. Set dual release thresholds for the recovery process and results of the wafer, and archive the entire chain of data when the thresholds are met to achieve traceability and auditability.

[0039] Specifically, a dual release threshold is set for the wafer recovery process and results: the process threshold covers three core requirements: the equivalent cavity state (ECS) enters a stable window, the equipment interlock conditions are met, and the compensation section parameters do not exceed the preset upper limit; the result threshold includes two key indicators: online thickness and thickness uniformity. Thickness uniformity can be defined and evaluated as follows: Method 1: Calculate based on the ratio of extreme value difference to average value, with the formula: U=(T_max-T_min) / T_avg, where T_max is the measured maximum thickness, T_min is the measured minimum thickness, and T_avg is the measured average thickness. Method 2: Calculate the standard deviation based on the thickness measurement results from multiple points. The formula is σ=sqrt(Σ_i(T_i-T_avg)^2 / (m-1)), where T_i is the thickness value of the i-th measurement point and m is the number of measurement points. Only when all process thresholds are met, and the thickness value and uniformity index (U and σ) in the result threshold both meet the preset specifications, can the restored wafer be judged as released. At the same time, the three-dimensional anchor point snapshot, compensation plan, parameter change record, online measurement results and release conclusion are fully archived to achieve traceability and auditability of the film repair process.

[0040] Table 1. Quantitative Comparison of Traditional Methods and Methods Introducing Membrane Replacement Function Example 2: This embodiment provides a wafer resurfacing system for process interruptions, including: The 3D anchor point snapshot acquisition module, after a process interruption is triggered, synchronously acquires and freezes three types of anchor point data at the same timestamp within a preset time limit to form 3D anchor points for resuming process calculations; the three types of anchor point data include mechanical cavity posture, recipe execution pointer, and equivalent process progress; preferably, the mechanical axis position, chuck working status, valve / power / mass flow controller (MFC) feedback data, and online sensor data are acquired in real time through fieldbus or drive interface; The transactional persistent storage module persists the 3D anchor point snapshot in a transactional manner, ensuring that it can be rolled back to the most recent consistent data point after abnormal reset or power failure. Preferably, the 3D anchor point snapshot is first written to the non-volatile random access memory (NVRAM) ring buffer, and then appended to the industrial solid-state drive (SSD) through the write-before-log (WAL) mechanism to ensure the real-time performance and reliability of data storage. The low-contamination rollback and status marking module moves the wafer out of the process cavity and back to the designated slot according to the low-contamination trajectory, while writing the status to be restored in the scheduling / MES system and binding the target cavity identifier and snapshot identifier. The equivalent cavity state reconstruction and gating module reconstructs the state of the target cavity before resuming operation. Resuming operation is only allowed when the cavity state enters a preset stable window and meets the threshold. When the original cavity is unavailable, the equivalent cavity and its corresponding calibration file are called. Preferably, the equivalent cavity state stable window is calculated and determined by subscribing to real-time feedback data from the temperature control system, pressure control system, gas path system, and plasma power supply. The gating signal generated by the determination is sent back to the recipe actuator via the SECS / GEM protocol or the internal interface of the device to realize the allow or prohibition control of the resuming operation process. The film replenishment amount calculation and compensation segment generation module, based on the equivalent process progress data in the three-dimensional anchor points, combined with the deposition rate or growth per cycle under the equivalent cavity state ECS, obtains the film replenishment amount and automatically generates constrained compensation segments; preferably, by reading the three-dimensional anchor point snapshot identifier and process calibration file (including deposition rate table, growth per cycle (GPC) table, and equivalent cavity mapping table), it calculates the required film replenishment thickness ΔT, compensation segment duration t_comp, or compensation cycle number N_comp, and automatically generates a compensation recipe (Recover-Recipe) and its unique version number; the generated compensation segment is synchronously written to the process database and associated with the wafer batch identifier and wafer unique identifier to ensure data traceability; The same path retransmission and fine positioning module calls historical path information for same path retransmission. The cavity positioning meets the preset tolerance requirements. If the tolerance is exceeded, a second alignment is performed. Preferably, this module supports calling historical motion trajectories by path identifier (PathID). It can be connected to notch alignment or edge alignment sensors and construct a secondary alignment control loop. The execution results (including positioning error and alignment count) are written back to the extended field of the three-dimensional anchor point snapshot to realize full-link traceability of the positioning process. The online confirmation and fine-tuning closed-loop module confirms the film-compensation effect through online measurement equipment after the compensation section is executed. If the deviation exceeds the threshold, parameter fine-tuning is performed within a limited number of times within safety constraints. Preferably, this module can integrate a quartz crystal microbalance (QCM), an online ellipsometer, or an optical emission spectrometer (OES) acquisition card, and be deployed on an industrial personal computer (IPC) or an independent measurement controller. The measured process parameter results are uploaded to the compensation section via high-speed Ethernet or equipment automation (EDA) interface, triggering a parameter fine-tuning iteration process with a preset number of iterations. The concurrent scheduling isolation and exception fallback module establishes an independent recovery queue and a decoupled operation from the regular production queue, ensuring that other cavities can continue production without line stoppage when a single cavity is interrupted; when continuous recovery failures reach a threshold, a degradation strategy is automatically executed and a record is kept; preferably, this module maintains two independent state machines for the production queue and the recovery queue to achieve decoupled scheduling of the two types of tasks; recovery tasks only occupy the idle time window of the target cavity and do not forcibly pause the normal production process of other cavities; exception fallback strategies and corresponding threshold configuration parameters are uniformly stored in the process formula library or production database to ensure configuration consistency and traceability.

[0041] The end-to-end traceability and dual release module sets dual release thresholds for the recovery wafer process and results. When the thresholds are met, the end-to-end data is archived to achieve traceability and auditability. Preferably, the module comprehensively judges the process thresholds (equivalent cavity status window, equipment interlock conditions, upper limit constraints of compensation parameters) and the result thresholds (measured thickness T_meas, uniformity U, standard deviation σ, etc.) and generates corresponding wafer release records. The end-to-end data (including 3D anchor point snapshots, compensation scheme plans, process parameter change records, online measurement curves, and release conclusions) is archived and stored according to the wafer's unique identifier, supporting end-to-end audit traceability.

[0042] The above modules can be deployed on the same device or distributed devices; the division of modules is only a functional logic description and does not limit the specific physical boundaries or implementation order.

[0043] Example 3: An electronic device is provided for running the aforementioned "Wafer Film Repair Method for Process Interruption". The electronic device includes a processor, a memory, and optional communication interfaces / display devices / input devices, etc.; the memory stores a computer program that can run on the processor, and when the processor executes the program, it implements steps S1 to S9 of the method described in Embodiment 1, specifically including but not limited to: S1. After a process interruption is triggered, three types of anchor point data with the same timestamp are collected and frozen simultaneously within a preset time limit to form three-dimensional anchor points for resuming process calculation; the three types of anchor point data include mechanical cavity posture, formula execution pointer and equivalent process progress. S2. Persist in storing the 3D anchor point snapshot in a transactional manner to ensure that after an abnormal reset or power failure, it will be rolled back to the most recent consistent data point; S3. Move the wafer out of the process cavity and back to the designated slot according to the low-contamination trajectory, and write the pending recovery status into the scheduling / MES system, and bind the target cavity identifier and snapshot identifier; S4. Before resuming work, the target cavity is reconstructed. Resuming work is only allowed when the cavity state enters the preset stable window and meets the threshold. When the original cavity is unavailable, the equivalent cavity and the corresponding calibration file are called. S5. Based on the equivalent process progress data in the three-dimensional anchor points, combined with the deposition rate or growth per cycle under the equivalent cavity state ECS, the amount of film replenishment is obtained and a constrained compensation segment is automatically generated. S6. Call historical path information to resend along the same path. The cavity positioning meets the preset tolerance requirements. If the tolerance is exceeded, perform secondary alignment. S7. After the compensation section is executed, the film-making effect is confirmed by online measurement equipment. If the deviation exceeds the threshold, the parameters are fine-tuned within a limited number of times within the safety constraints. S8. Establish an independent recovery queue to operate decoupled from the regular production queue, ensuring that other cavities can continue production normally without line stoppage when a single cavity is interrupted; when continuous recovery failures reach a threshold, automatically execute a degradation strategy and leave a record. S9. Set dual release thresholds for the recovery process and results of the wafer, and archive the entire chain of data when the thresholds are met to achieve traceability and auditability.

[0044] The electronic device hardware can be one of a server, personal computer, workstation, industrial controller, edge computing device, or mobile terminal; the processor can be a general-purpose CPU, GPU, NPU, FPGA, or a combination thereof; the memory can be RAM, ROM, flash memory, or disk array. The device can interact with local / remote data storage (acquiring observation data and outputting inversion results) through a communication interface. The above hardware configuration does not constitute a limitation of the present invention.

[0045] Example 4: A computer-readable storage medium storing a computer program, which, when run on a processor of an electronic device, causes the program to execute the method steps S1 to S9 described in Embodiment 1; the storage medium may be a disk, optical disk, flash memory, solid-state drive, read-only memory, random access memory, or any combination of the above media.

[0046] Those skilled in the art will understand that the modules or steps described above can be implemented using general-purpose computer devices. Optionally, they can be implemented using computer-executable program code, which can then be stored in a storage device for execution by a computer device. Alternatively, they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. This disclosure is not limited to any particular combination of hardware and software.

[0047] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0048] While the specific embodiments of this disclosure have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of this disclosure. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of this disclosure are still within the scope of protection of this disclosure.

Claims

1. A wafer resurfacing method for process interruptions, characterized in that, Includes the following steps: After a process interruption is triggered, three types of anchor point data with the same timestamp are collected and frozen simultaneously within a preset time limit to form three-dimensional anchor points for resuming process calculations; the three types of anchor point data include mechanical cavity posture, formula execution pointer, and equivalent process progress. The 3D anchor point snapshot is persisted in a transactional manner to ensure that it is rolled back to the most recent consistent data point after an abnormal reset or power failure. The wafer is moved out of the process cavity and returned to the designated slot according to the low-contamination trajectory. At the same time, the pending recovery status is written into the scheduling / MES system, and the target cavity identifier and snapshot identifier are bound. Before resuming work, the target cavity is reconstructed. Resuming work is only allowed when the cavity state enters a preset stable window and meets the threshold. When the original cavity is unavailable, the equivalent cavity and its corresponding calibration file are invoked. Based on the equivalent process progress data in the three-dimensional anchor points, combined with the deposition rate or growth per cycle under the equivalent cavity state ECS, the amount of film replenishment is obtained and a constrained compensation segment is automatically generated. Historical path information is called for retransmission along the same path. The cavity positioning meets the preset tolerance requirements. If the tolerance is exceeded, a second alignment is performed. After the compensation phase is executed, the film-forming effect is confirmed by online measurement equipment. If the deviation exceeds the threshold, the parameters are fine-tuned within a limited number of times within the safety constraints. Establish an independent recovery queue to operate decoupled from the regular production queue, ensuring that other cavities can continue production without line stoppage when a single cavity is interrupted; when consecutive recovery failures reach a threshold, automatically execute a degradation strategy and leave a record. The process and results of wafer recovery are subject to dual release thresholds. When the thresholds are met, the entire data chain is archived to enable traceability and auditing.

2. The wafer resurfacing method for process interruptions according to claim 1, characterized in that, The mechanical cavity attitude includes r, z, θ, chuck eccentricity, and Notch orientation; the recipe execution pointer includes recipe_id, version hash, step_idx, substep_idx, execution time within the step, and current gas path plasma state; the equivalent process progress includes online thickness estimation, equivalent deposition dose (EDD), or number of completed ALD cycles.

3. The wafer resurfacing method for process interruptions according to claim 2, characterized in that, The online thickness estimate is obtained as follows: T̂_int=T̂_base+Σ_k(v_ref,k×t_eff,k×K_sense,k)where, T̂_base is the reference film thickness, Σ_k is the cumulative summation of multiple deposition-related process segments k; v_ref,k is the calibration rate of this segment under the reference steady state, t_eff,k is the "effective deposition time" of this segment, and K_sense,k is the correction factor (it is recommended to limit the amplitude to suppress noise).

4. The wafer resurfacing method for process interruptions according to claim 1, characterized in that, The amount of film replenishment includes the required film thickness, the compensation duration, and the number of compensation cycles. The required film thickness is: ΔT = max(0, T0 - T̂_int) The compensation time is: t_comp=clamp(ΔT / v_ECS,0,η·t_step_nom) Number of compensation cycles: N_comp = ceil(ΔT / GPC_ECS) where, T0 is the target film thickness, T̂_int is the estimated current deposited thickness; v_ECS is the real-time rate or equivalent rate after ECS windowing, η is the compensation upper limit coefficient, t_step_nom is the standard duration of this step in the original Recipe; GPC_ECS is the growth per cycle under ECS conditions; when recovering across cavities, equivalent correction is performed using GPC_ECS=GPC_ref×K_chamber, where GPC_ref is the reference growth per cycle; K_chamber is the cavity state correction coefficient, which comes from the cavity mapping table or calibration file.

5. The wafer resurfacing method for process interruptions according to claim 2, characterized in that, The equivalent deposition dose (EDD) is applicable to the estimation of continuous deposition in scenarios where direct thickness measurement is not possible. Specifically, EDD = Σ_k(P_RF,k^α·F_prec,k^β·exp(-Ea / (R·T_chuck,k))·Δt_k). Where P_RF,k is the RF power, F_prec,k is the reactant gas flow rate, T_chuck,k is the chuck temperature, Ea is the equivalent activation energy parameter, α and β are empirical exponents; Δt_k is the time increment of the kth process segment; the EDD and film thickness are approximately linearly correlated by calibrating the wafer fitting.

6. The wafer resurfacing method for process interruptions according to claim 1, characterized in that, The historical path is obtained as follows: PathID=Hash(tool_id||module_id||from_station||to_station||waypoints||v_profile||pose), where tool_id is the machine identifier, module_id is the module identifier, from_station and to_station are the starting station and the target station, respectively, waypoints is the set of key points of the path, v_profile is the motion curve parameter, and pose is the attitude parameter; The historical path PathID and its corresponding timestamp information are synchronously written into the 3D anchor point snapshot to jointly complete the atomic disk storage.

7. The wafer resurfacing method for process interruptions according to claim 1, characterized in that, The process thresholds include ECS window entry, interlock satisfaction, and compensation segment not exceeding the upper limit; The result thresholds include online thickness and uniformity indicators.

8. A wafer resurfacing system for process interruptions, characterized in that, include: The three-dimensional anchor point snapshot acquisition module, after a process interruption is triggered, synchronously acquires and freezes three types of anchor point data with the same timestamp within a preset time limit to form three-dimensional anchor points for resuming process calculations; the three types of anchor point data include mechanical cavity posture, formula execution pointer, and equivalent process progress. The transactional persistent storage module persists the 3D anchor point snapshot in a transactional manner, ensuring that it can be rolled back to the most recent consistent data point after an abnormal reset or power failure. The low-contamination rollback and status marking module moves the wafer out of the process cavity and back to the designated slot according to the low-contamination trajectory, while writing the status to be restored in the scheduling / MES system and binding the target cavity identifier and snapshot identifier. The equivalent cavity state reconstruction and gating module reconstructs the state of the target cavity before resuming operation. It allows resuming operation only when the cavity state enters a preset stable window and meets the threshold. When the original cavity is unavailable, the equivalent cavity and its corresponding calibration file are invoked. The film replenishment amount calculation and compensation segment generation module, based on the equivalent process progress data in the three-dimensional anchor points, combined with the deposition rate or growth per cycle under the equivalent cavity state ECS, obtains the film replenishment amount and automatically generates a constrained compensation segment. The same path retransmission and fine positioning module calls historical path information to perform same path retransmission. The cavity positioning meets the preset tolerance requirements. If the tolerance is exceeded, a second alignment is performed. The online confirmation and fine-tuning closed-loop module confirms the film-making effect after the compensation section is executed through online measurement equipment. When the deviation exceeds the threshold, the parameters are fine-tuned within a limited number of times within the safety constraints. The concurrent scheduling isolation and exception fallback module establishes an independent recovery queue and decouples it from the regular production queue to ensure that other cavities can continue to produce normally without line stoppage when a single cavity is interrupted; when continuous recovery failures reach a threshold, a degradation strategy is automatically executed and a record is kept. The end-to-end traceability and dual release module sets dual release thresholds for the recovery wafer process and results. When the thresholds are met, the end-to-end data is archived to achieve traceable auditing.

9. An electronic device, comprising a memory, a processor, and a computer program stored in the memory and running thereon, characterized in that, When the processor executes the program, it implements a wafer resurfacing method for process interruption as described in any one of claims 1-7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by the processor, the program implements a wafer resurfacing method for process interruption as described in any one of claims 1-7.

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