A contact hole resistance test structure and a manufacturing method thereof

Abstract

The application relates to the technical field of semiconductors, and discloses a contact hole resistance test structure and a manufacturing method. The structure comprises a semiconductor base layer, a polysilicon layer, an interlayer dielectric layer, and a metal layer. The polysilicon layer comprises a plurality of polysilicon gates, the polysilicon gates are arranged at equal intervals along an X direction and a Y direction of a layer plane in sequence, respectively form a repeated unit matrix in the X direction and the Y direction, and a plurality of blank / gap areas are sequentially formed between adjacent polysilicon gates. The interlayer dielectric layer covers the polysilicon layer. The plurality of contact holes are connected to the semiconductor base layer in a vertical direction and are uniformly distributed in the blank / gap areas. The metal layer covers the contact holes. The structure can effectively monitor the alignment deviation problem, monitor the Spacer and SAB etching process capability, thereby providing an effective means and basis for solving the contact hole short circuit problem, and finally improving the semiconductor device yield.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a contact hole resistance testing structure and fabrication method. Specifically, it can be applied to logic elements, mixed-signal elements, embedded memories, BCD (bipolar-complementary metal-oxide-semiconductor-double-diffused metal-oxide-semiconductor), trench transistors (trench MOSFETs), and high-voltage components (such as power management integrated circuits) and related products and processes. Background Technology

[0002] As large-scale integrated circuit manufacturing progresses towards higher integration levels, smaller critical dimensions, and increasingly complex device structures, the requirements for the precision and repeatability of integrated circuit manufacturing processes are becoming increasingly stringent. To meet the overall electrical performance requirements of integrated circuits, circuits with different structures are often stacked layer by layer during chip manufacturing. Among these, the stacking in the front-end manufacturing process of integrated circuits mainly involves gates and contact holes.

[0003] Contact via technology refers to the formation of numerous tiny vertical vias on the interlayer dielectric (ILD) layer. These vias serve as connection channels between the transistor gate, source / drain, and metal layer 1, and are filled with tungsten. Traditional contact via resistance testing structures can only reflect process variations in the contact via portion, such as via size, ILD layer thickness, and via filling conditions. However, factors actually affecting contact via resistance include alignment deviations between exposure and preceding layers (such as silicon nitride and polysilicon), spacer thickness, residual silicon dioxide thickness after etching, SAB thickness, and polysilicon linewidth dimensions. Existing structures cannot meet the requirements for electrical monitoring feedback.

[0004] Therefore, there is a need to improve the existing technology for the structure and manufacturing method of contact hole resistance testing. Summary of the Invention

[0005] In view of this, the purpose of this invention is to provide a contact hole resistance testing structure and manufacturing method. The contact hole structure of this invention can effectively monitor whether there is a good electrical connection between the metal contact hole and the diffusion layer, can detect alignment deviations in multilayer structures, and can detect insufficient gate spacer and SAB process window issues, thereby providing analytical means and basis for reducing the risk of contact hole open circuits and improving the yield of semiconductor devices.

[0006] To achieve the above objectives, embodiments of the present invention provide a contact hole resistance testing structure, comprising: The semiconductor base layer has a low-resistivity active / diffusion region formed based on the semiconductor manufacturing process; The polysilicon layer includes multiple polysilicon gates, which are arranged at equal intervals along the X and Y directions of the layer plane. The X and Y directions are perpendicular to each other, and multiple blank areas / gap areas are formed between adjacent polysilicon gates. Interlayer dielectric layer, which covers the polysilicon layer; Multiple contact holes are vertically inserted through the interlayer dielectric layer and connected to the semiconductor base layer. The multiple contact holes are evenly distributed in the blank / gap area. A metal layer covers the contact holes; The metal layer wires pass through the contact holes, and then through the contact holes on the other side of the same active / diffusion region to connect to another metal wire, and then connect to the contact holes of the next source / diffusion region. By repeating this process, a contact hole resistance chain test structure is formed. Furthermore, there are two contact hole resistance chain test structure patterns in the X and Y directions according to the polysilicon gate on the diffusion region, and more complex chain topologies are formed from these two patterns.

[0007] In some embodiments, the multiple contact holes are evenly distributed within the blank / gap area, including: In the Y direction, multiple contact holes are evenly spaced in the blank / gap area, and in the X direction, contact holes are provided every other blank / gap area.

[0008] In some embodiments, the metal layer includes multiple metal regions, each metal region being disposed along the X or Y direction, and each metal region arbitrarily covering two adjacent contact holes.

[0009] In some implementations, the semiconductor base layer includes a substrate layer and a diffusion layer.

[0010] In some implementations, the width of the polysilicon gate ranges from 0.1 μm to 0.5 μm, and the length ranges from 1 μm to 10 μm.

[0011] In some implementations, the spacing between the polysilicon gate and the contact hole is 0.1 μm to 0.5 μm.

[0012] In some embodiments, the contact hole is square in shape and has a size of 0.1 μm to 0.5 μm.

[0013] In another aspect, the present invention provides a method for forming a contact hole resistance testing structure, comprising the following steps: S1 provides a semiconductor base layer, on which a polysilicon layer is grown, and the polysilicon layer is etched to form multiple spaced polysilicon gates. S2 deposits an interlayer dielectric layer on the semiconductor base layer. The thickness of the interlayer dielectric layer is greater than the thickness of the polysilicon layer. The interlayer dielectric layer is then planarized. S3 etches the interlayer dielectric layer down to the semiconductor base layer to form contact holes.

[0014] In some embodiments, in S1, etching the polysilicon layer to form a plurality of spaced polysilicon gates includes: Photoresist is formed on a polysilicon layer, and the photoresist is exposed and developed to form polysilicon gates arranged at equal intervals along the X and Y directions.

[0015] In some embodiments, in S3, etching down to the semiconductor base layer on the interlayer dielectric layer to form a contact hole includes: Photoresist is formed on the interlayer dielectric layer. The photoresist is exposed and developed to form the photoresist pattern of the contact hole. Etching is performed according to the photoresist pattern until the surface of the semiconductor base layer is exposed to form the contact hole.

[0016] The present invention has at least the following beneficial technical effects: This invention provides a test bond arrangement structure for wafer contact vias. A diffusion layer and a polysilicon layer are sequentially formed on a substrate. The polysilicon layers are spaced out on the diffusion layer to form blank / gap regions. The contact hole positions are defined in the blank / gap regions. A metal layer is then covered to form a new arrangement structure. This complex design is closer to the actual circuit arrangement structure and can effectively monitor whether there is a good electrical connection between the metal contact hole and the diffusion layer. It can detect alignment deviations in multilayer structures and detect insufficient windows in the gate spacer and SAB process. This provides analytical means and basis for reducing the risk of contact hole open circuits and improving the yield of semiconductor devices.

[0017] Compared to the connection between the contact hole and the underlying bulk diffusion layer, this invention incorporates polysilicon in a simpler structure, which more effectively reflects the impact of different manufacturing processes on the contact conductivity between the contact hole and the diffusion layer: increasing the gate pattern, thus addressing the connection conductivity issues between the contact hole and the bottom diffusion region caused by process variations such as the alignment accuracy between the gate and the diffusion region, the width of the polysilicon gate size, the polysilicon gate spacer, and the formation of salicide metal silicides. Specifically, this invention is applicable to logic elements, mixed-signal elements, embedded memories, BCD (bipolar-complementary metal-oxide-semiconductor-double-diffused metal-oxide-semiconductor), trench MOSFETs, and high-voltage components (such as power management integrated circuits) and related products and processes. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of an embodiment of the contact hole resistance testing structure provided by the present invention; Figure 2 The present invention provides a basis for Figure 1 A cross-sectional view in the X direction; Figure 3 The present invention provides a basis for Figure 1 A cross-sectional view in the Y direction; Figure 4 The present invention provides a basis for Figure 1 Schematic diagrams of different test structure embodiments.

[0020] Explanation of reference numerals in the attached figures: 10. Semiconductor base layer; 11. Substrate; 12. Trench; 20. Diffusion layer; 30. Polysilicon layer; 31. Polysilicon gate; 40. Interlayer dielectric layer; 50. Contact hole; 60. Metal layer. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. For example, terms such as “length,” “width,” “upper,” “lower,” “left,” “right,” “front,” “rear,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer” indicate orientations or positions based on the orientations or positions shown in the accompanying drawings and are for ease of description only, and should not be construed as limiting the technical solution.

[0023] The terms "comprising" and "having," and any variations thereof, used in the specification, claims, and accompanying drawings of this invention are intended to cover non-exclusive inclusion; the terms "first," "second," etc., used in the specification, claims, and accompanying drawings are used to distinguish different objects, not to describe a particular order. "A plurality of" means two or more, unless otherwise explicitly specified.

[0024] In the description and claims of this invention and the foregoing drawings, when an element is referred to as "fixed to," "mounted to," "disposed on," or "connected to" another element, it can be located directly or indirectly on that other element. For example, when an element is referred to as "connected to" another element, it can be directly or indirectly connected to that other element.

[0025] Furthermore, the reference to "embodiment" herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0026] like Figure 1 The figure shown is a plan view of the contact hole resistance testing structure provided by the present invention. Figure 2 The present invention provides a basis for Figure 1 A cross-sectional view in the X direction. Figure 3 The present invention provides a basis for Figure 1 A cross-sectional view in the Y direction, the structure includes: Semiconductor base layer 10; The polysilicon layer 30 includes a plurality of polysilicon gates 31, which are arranged at equal intervals along the X and Y directions of the layer plane. The X and Y directions are perpendicular to each other, and a plurality of blank areas / gap areas are formed between adjacent polysilicon gates. Interlayer dielectric layer 40 covers polysilicon layer 30; Multiple contact holes 50 are vertically connected to the semiconductor base layer 10 through the interlayer dielectric layer 40. The multiple contact holes 50 are uniformly distributed in the blank area / gap area. Metal layer 60 covers contact hole 50; The metal layer wires pass through the contact holes, and then through the contact holes on the other side of the same active / diffusion region to connect to another metal wire, and then connect to the contact holes of the next source / diffusion region. By repeating this process, a contact hole resistance chain test structure is formed. Furthermore, there are two contact hole resistance chain test structure patterns in the X and Y directions according to the polysilicon gate on the diffusion region, and more complex chain topologies are formed from these two patterns.

[0027] Furthermore, multiple contact holes 50 are evenly distributed within the blank / gap area, including: In the Y direction, multiple contact holes 50 are evenly spaced within the blank / gap area; in the X direction, a contact hole 50 is provided every other blank / gap area. For example... Figure 1 The diagram shown is a partial plan view of the structure. The overall structure includes... Figure 1 Multiple repeating units. In some embodiments, the polysilicon gates 31 are evenly spaced in the X and Y directions, with two adjacent polysilicon gates forming a group. Each group of polysilicon gates has two contact holes 50, and these are repeated to form a pattern. Figure 1 The structure shown.

[0028] Furthermore, the metal layer 60 includes multiple metal regions, each metal region being disposed along the X or Y direction, and each metal region arbitrarily covering two adjacent contact holes 50. The metal layer is mainly used for signal transmission and interconnection between various devices. The arrangement direction of the metal layer can be selected in different ways, and any covering structure that can arbitrarily cover two adjacent contact holes is within the protection scope of this invention.

[0029] Furthermore, the semiconductor base layer 10 includes a substrate layer 11 and a diffusion layer 20. Multiple trenches 12 are also formed on the substrate to achieve electrical isolation between different active regions. The diffusion layer is mainly used to form key areas of active devices such as transistors, including the source and drain. By introducing impurity atoms into specific regions of the substrate, the electrical properties of these regions are changed, enabling them to function as active regions to control current flow. A polysilicon layer is subsequently deposited to form the gate, followed by the deposition of an interlayer dielectric (ILD) for electrical isolation. The main function of the ILD is to achieve electrical isolation between different conductive layers. In semiconductor device manufacturing, with the advancement of technology, multiple conductive layers are stacked together, such as polysilicon layers and metal layers. The ILD can prevent short circuits between these conductive layers, ensuring that each conductive layer can operate independently. For example, in a multilayer wiring integrated circuit, the ILD isolates the various metal wiring layers, much like wrapping insulation between wires, preventing current from flowing between different layers.

[0030] Furthermore, the width of the polysilicon gate 31 ranges from 0.1μm to 0.5μm, and the length ranges from 1μm to 10μm. The width of the polysilicon gate can be selectively adjusted to the minimum linewidth allowed by the process platform.

[0031] Furthermore, the spacing between the polysilicon gate and the contact hole is 0.1μm to 0.5μm, which can be selectively adjusted to the minimum size allowed by the support.

[0032] Furthermore, the contact hole is square in shape, with a size of 0.1μm to 0.5μm. For square contact holes, the edges of the pattern are relatively regular. Compared to circular or other irregular shapes, square patterns are easier to transfer at high resolution during photolithography. In addition, the photolithography process window for square patterns is relatively wide, which means that there is better tolerance for changes in parameters such as exposure dose and depth of focus during the photolithography process.

[0033] Furthermore, such as Figure 4 The image shown is based on the present invention. Figure 1 The diagram illustrates different chain-type topology test structure embodiments. The relative orientation of the three layers on the semiconductor base layer (diffusion region, light yellow area in the figure), polysilicon layer (blue striped area), and metal layer (green striped area) can include four types as shown in the figure. Figure 4 -a and 4-c are examples of polysilicon gates arranged at equal intervals along the X-direction on the layer plane, while 4-b and 4-d are examples of polysilicon gates arranged at equal intervals along the Y-direction on the layer plane. These are combined with different orientations of the metal layer to sequentially cover two adjacent contact holes (red square areas). Metal layer wires pass through these contact holes, then through contact holes on the other side of the same active / diffusion region to connect to another metal wire, and then to the contact hole of the next source / diffusion region. This process is repeated to form a contact hole resistance chain test structure. Those skilled in the art should understand that... Figure 4 The structures described are merely examples and do not constitute a limitation on all structures of the present invention.

[0034] In another aspect, the present invention provides a method for forming a contact hole resistance testing structure, comprising the following steps: S1 provides a semiconductor base layer, on which a polysilicon layer is grown, and the polysilicon layer is etched to form multiple spaced polysilicon gates. S2 deposits an interlayer dielectric layer on the semiconductor base layer. The thickness of the interlayer dielectric layer is greater than the thickness of the polysilicon layer. The interlayer dielectric layer is then planarized. S3 etches the interlayer dielectric layer down to the semiconductor base layer to form contact holes.

[0035] Further, in S1, a semiconductor base layer is provided, specifically including a substrate and a diffusion layer. Etching the polysilicon layer to form multiple spaced polysilicon gates includes: A polysilicon layer of a certain thickness is grown using chemical vapor deposition (CVD). Photoresist is then formed on the polysilicon layer, and the photoresist is exposed and developed to form polysilicon gates arranged at equal intervals along the X and Y directions. After forming the polysilicon layer structure, an interlayer dielectric layer is deposited to isolate the different conductive layers. Chemical mechanical polishing (CMP) is then used to planarize the dielectric layer, polishing the ILD layer surface to a very smooth degree, providing excellent surface conditions for subsequent contact hole photolithography and etching processes.

[0036] Furthermore, in S3, etching down to the semiconductor base layer on the interlayer dielectric layer to form contact holes includes: Photoresist is formed on the interlayer dielectric layer. The photoresist is exposed and developed to form the photoresist pattern of the contact hole. Etching is performed according to the photoresist pattern until the surface of the semiconductor base layer is exposed to form the contact hole.

[0037] Blank Area / Gap Area Blank Area / Gap Area Blank Area / Gap Area The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this invention as defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.

[0038] It should be understood that, as used herein, the singular form “a” is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, “and / or” refers to any and all possible combinations of one or more of the associated listed items.

[0039] The embodiment numbers disclosed in the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0040] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A contact hole resistance testing structure, characterized in that, include: A semiconductor base layer having a low-resistivity active / diffusion region formed based on a semiconductor fabrication process; A polysilicon layer, the polysilicon layer including a plurality of polysilicon gates, the polysilicon gates being arranged at equal intervals along the X and Y directions of the layer plane, the X direction being perpendicular to the Y direction, and a plurality of blank areas / gap areas being formed sequentially between adjacent polysilicon gates; An interlayer dielectric layer, which covers the polysilicon layer; Multiple contact holes are provided, which penetrate the interlayer dielectric layer in a vertical direction and connect to the semiconductor base layer. The multiple contact holes are uniformly distributed in the blank area / gap area. A metal layer covering the contact hole; The metal layer conductors pass through the contact holes, and then through the contact holes on the other side of the same active / diffusion region to connect to another metal wire, and then connect to the contact holes of the next source / diffusion region. By repeating this process, a contact hole resistance chain test structure is formed. Furthermore, there are two contact hole resistance chain test structure patterns in the X and Y directions according to the polysilicon gate on the diffusion region, and more complex chain topologies are formed from these two patterns.

2. The contact hole resistance testing structure according to claim 1, characterized in that, The plurality of contact holes are evenly distributed within the blank / gap area, including: In the Y direction, the plurality of contact holes are evenly spaced in the blank / gap area, and in the X direction, the contact holes are provided at intervals of one blank / gap area.

3. The contact hole resistance testing structure according to claim 1, characterized in that, The metal layer includes multiple metal regions, each of which is arranged along the X or Y direction, and each of which arbitrarily covers two adjacent contact holes.

4. The contact hole resistance testing structure according to claim 1, characterized in that, The semiconductor base layer includes a substrate layer and a diffusion layer.

5. The contact hole resistance testing structure according to claim 1, characterized in that, The width of the polysilicon gate ranges from 0.1 μm to 0.5 μm, and the length ranges from 1 μm to 10 μm.

6. The contact hole resistance testing structure according to claim 1, characterized in that, The distance between the polysilicon gate and the contact hole is 0.1 μm to 0.5 μm.

7. The contact hole resistance testing structure according to claim 1, characterized in that, The contact hole is square in shape and has a size of 0.1μm to 0.5μm.

8. A method for forming a contact hole resistance testing structure, used to form the structure as described in any one of claims 1 to 7, characterized in that, include: S1 provides a semiconductor base layer, on which a polysilicon layer is grown, and the polysilicon layer is etched to form a plurality of spaced polysilicon gates. S2 deposits an interlayer dielectric layer on the semiconductor base layer, the thickness of the interlayer dielectric layer being greater than the thickness of the polysilicon layer, and performs planarization processing on the interlayer dielectric layer; S3 etches the interlayer dielectric layer down to the semiconductor base layer to form a contact hole.

9. The method for forming the contact hole resistance testing structure according to claim 8, characterized in that, In S1, etching the polysilicon layer to form a plurality of spaced polysilicon gates includes: Photoresist is formed on the polysilicon layer, and the photoresist is exposed and developed to form polysilicon gates arranged at equal intervals along the X and Y directions.

10. The method for forming the contact hole resistance testing structure according to claim 8, characterized in that, In S3, etching the interlayer dielectric layer down to the semiconductor base layer to form a contact hole includes: A photoresist is formed on the interlayer dielectric layer. The photoresist is exposed and developed to form a photoresist pattern for the contact hole. The photoresist pattern is etched until the surface of the semiconductor base layer is exposed to form the contact hole.

Images