A method of manufacturing a semiconductor device
By forming and processing stop layers and hard mask layers during semiconductor device manufacturing to control the high uniformity of the gate structure, the problem of high inconsistency in the gate planarization process is solved, improving the process window and the execution of subsequent processes.
Patent Information
- Application Number
- CN202510099543.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-21
- Publication Date
- 2026-07-24
AI Technical Summary
In the prior art, due to the different trench densities in different regions, the gate structure height in different regions is inconsistent after the gate planarization process, which is difficult to control and thus affects the subsequent processes.
After forming a stop layer and a patterned hard mask layer covering the gate structure on the substrate, trenches are etched and filled with a dielectric layer. Subsequently, the stop layer and hard mask layer are removed by grinding to ensure surface planarization and control the uniformity of the gate structure height.
By controlling the high consistency of the gate structure, the process window is widened, improving the subsequent dummy gate removal and metal gate filling processes. It also has good compatibility with existing processes, and is cost-effective and stable.
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Figure CN122458766A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more specifically to a method for manufacturing a semiconductor device. Background Technology
[0002] Currently, for semiconductor devices such as 3D transistors, after forming the fins and gate structure (pseudo-gate), a single-diffusion break (SDB) process is generally required to form trenches to achieve isolation of the active region. In this process, a hard mask layer needs to be formed, which is used as a mask to form the trench. After the trench is formed, a multilayer dielectric layer is formed to fill the trench. Then, a gate planarization process is performed to expose the pseudo-polysilicon in the pseudo-gate structure.
[0003] However, in the gate planarization process of related technologies, due to the different densities of the trenches formed by the SDB process in different regions, and the differences in the height of the front gate structure in different regions, it is difficult to control the consistency of the gate structure height in different regions after the gate planarization process. That is, it is difficult to control the gate heightloading in different regions, which leads to a narrowing of the process window and is not conducive to subsequent processes such as pseudo-gate removal and metal gate filling.
[0004] Therefore, improvements are needed to at least partially address the aforementioned problems. Summary of the Invention
[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.
[0006] To address the existing problems, this application provides a method for manufacturing a semiconductor device, comprising:
[0007] A substrate is provided on which a gate structure is formed, wherein the substrate includes at least a first region and a second region;
[0008] A stop layer covering the gate structure and a patterned hard mask layer are sequentially formed on the substrate;
[0009] Using the patterned hard mask layer as a mask, a portion of the stop layer, a portion of the gate structure, and a portion of the substrate are etched away to form trenches, wherein the density of the trenches in the first region is less than the density of the trenches in the second region;
[0010] A dielectric layer is formed to fill the trench and cover the hard mask layer;
[0011] Grinding removes the dielectric layer and the hard mask layer located on the stop layer;
[0012] Remove the stop layer to expose the top surface of the gate structure.
[0013] For example, the gate structure includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer;
[0014] A dielectric layer is also formed between adjacent gate electrode layers, and a contact hole etch stop layer and a gate spacer layer are also formed between the dielectric layer and the gate electrode layer.
[0015] Exemplarily, after removing the stop layer to expose the top surface of the gate structure, the method further includes:
[0016] Remove a portion of the gate electrode layer to make the remaining gate electrode layer the thickness of a preset thickness.
[0017] For example, a polishing process is performed to remove the stop layer and a portion of the gate electrode layer so that the remaining gate electrode layer has the same thickness as the preset thickness.
[0018] For example, before performing the grinding process, the method further includes: measuring the total thickness of the stop layer and the gate electrode layer to obtain a first thickness; and based on the first thickness and the preset thickness, obtaining the time required to grind the gate electrode layer to the preset thickness, denoted as the preset time.
[0019] Performing the grinding process includes:
[0020] The grinding process is performed for the preset duration to remove the stop layer and a portion of the gate electrode layer so that the remaining gate electrode layer has the preset thickness.
[0021] For example, the material of the stop layer is the same as the material of the gate electrode layer; and / or
[0022] The thickness of the stop layer ranges from 10 angstroms to 60 angstroms.
[0023] For example, the material of the stop layer and the material of the gate electrode layer both include silicon.
[0024] For example, a plurality of gate structures are formed on the substrate, and the plurality of gate structures extend along a first direction;
[0025] The substrate is further provided with a plurality of fins extending along a second direction that intersects the first direction. The gate structure spans the fins. The regions on both sides of the gate structure of the fins are respectively formed as active and drain regions. The trench penetrates the fins.
[0026] Exemplarily, the dielectric layer includes a first dielectric layer, a second dielectric layer, and a third dielectric layer, forming a dielectric layer that fills the trench and covers the hard mask layer, comprising:
[0027] A first dielectric layer is formed, which covers the bottom and sidewalls of the trench and the hard mask layer;
[0028] A second dielectric layer is formed, which fills the remaining portion of the trench and covers the first dielectric layer;
[0029] A third dielectric layer is formed that covers the second dielectric layer.
[0030] For example, forming the patterned hard mask layer includes:
[0031] Form a hard mask layer;
[0032] A spin-coated carbon layer, an anti-reflective coating, and a patterned photoresist layer are sequentially formed on the hard mask layer;
[0033] Using the patterned photoresist layer as a mask, the anti-reflective coating, the spin-coated carbon layer, and the hard mask layer are etched to obtain the patterned hard mask layer.
[0034] The semiconductor device manufacturing method of this application embodiment forms a stop layer, first grinds to remove the dielectric layer and hard mask layer located on the stop layer to obtain a flat surface, and then removes the stop layer to expose the top surface of the gate structure, thus completing gate planarization. It can inherit the surface flatness of the previous grinding step, thereby effectively controlling the consistency of the gate structure height in different regions, that is, it can effectively control the gate height load in different regions, eliminating the influence of trench density differences and previous gate height differences on gate planarization, and widening the process window to facilitate subsequent processes such as dummy gate removal and metal gate filling. Attached Figure Description
[0035] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions to explain the principles of the invention.
[0036] In the attached image:
[0037] Figures 1A-1C A cross-sectional schematic diagram of trench formation and gate planarization in semiconductor devices in related technologies is shown;
[0038] Figure 2 A flowchart illustrating a method for manufacturing a semiconductor device according to a specific embodiment of this application is shown;
[0039] Figures 3A-3E The diagram shows a cross-sectional view of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of this application.
[0040] Explanation of reference numerals in the attached figures:
[0041] 110 - Trench, 120 - Hard mask layer, 130 - Pseudo-polysilicon, 140 - Dielectric layer, 150 - Recess;
[0042] 300-Substrate, 301-Gate electrode layer, 302-Gate dielectric layer, 303-Fin, 304-Source region, 305-Drain region, 306-Dielectric layer, 307-Contact hole etch stop layer, 308-Gate spacer layer, 3081-First sub-spacer layer, 3082-Second sub-spacer layer, 3083-Third sub-spacer layer, 309-Stop layer, 310-Hard mask layer, 3101-First sub-hard mask layer, 3102-Second sub-hard mask layer, 311-Spin-coated carbon layer, 312-Anti-reflective coating, 313-Photoresist layer, 314-Trench, 315-First dielectric layer, 316-Second dielectric layer, 317-Third dielectric layer. Detailed Implementation
[0043] The present application will now be described more fully with reference to the accompanying drawings, in which embodiments of the present application are illustrated. However, the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.
[0044] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.
[0045] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0046] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0047] Embodiments of the application are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures). Thus, variations from the shapes shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the application.
[0048] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms as defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the relevant field and / or the context of this specification, and not as in an ideal or overly formal sense, unless expressly defined herein.
[0049] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.
[0050] like Figures 1A to 1C As shown, the SDB process in the related technology uses a hard mask layer 120 as a mask to form a trench 110, then fills the trench 110 with multiple dielectric layers, and finally performs a planarization process using chemical mechanical polishing (CMP) to expose the pseudo-polysilicon 130 in the pseudo-gate structure. Among these, Figure 1A (a) Figure 1B (a) and Figure 1C (a) shows a schematic cross-sectional view of a region with low trench density in a semiconductor device. Figure 1A (b) Figure 1B (b) and Figure 1C (b) shows a cross-sectional schematic diagram of a region with high trench density in a semiconductor device.
[0051] The inventors of this application discovered that in the gate planarization process of related technologies, pseudo-polysilicon 130 is generally used as a stop layer for chemical mechanical polishing. However, a topography / filled gap (not shown) is formed on the top surface of the dielectric layer in the trench 110 region. The density of this filled gap affects the polishing rate of the chemical mechanical polishing process. The higher the density of the filled gap, the faster the polishing rate. Conversely, the higher the trench density, the higher the density of the filled gap. That is, the region with high trench density will contact the pseudo-polysilicon 130 first. At this time, the region with low trench density still has a hard mask layer 120 remaining. The remaining hard mask layer 120 will cause abnormalities in the subsequent pseudo gate removal and metal gate filling steps. Figure 1C As shown, in order to ensure the complete removal of the hard mask layer 120, the exposed pseudo polysilicon 130 in the high trench density area will be ground down to remove some of its height. This results in the height of the pseudo polysilicon 130 in the high trench density area after the gate planarization process being significantly lower than the height of the pseudo polysilicon 130 in the low trench density area.
[0052] Due to the different trench densities and the varying heights of the front-layer pseudo-polysilicon 130 in different regions, it is difficult to control the consistency of the gate structure height in different regions after the gate planarization process. This makes it difficult to control the gate height load in different regions, which in turn narrows the process window and hinders subsequent processes such as pseudo-gate removal and metal gate filling.
[0053] Therefore, in view of the aforementioned technical problems, this application proposes a method for manufacturing a semiconductor device, such as... Figure 2 As shown, it mainly includes the following steps:
[0054] Step S1: Provide a substrate on which a gate structure is formed, wherein the substrate includes at least a first region and a second region;
[0055] Step S2: A stop layer covering the gate structure and a patterned hard mask layer are sequentially formed on the substrate;
[0056] Step S3: Using a patterned hard mask layer as a mask, a portion of the stop layer, a portion of the gate structure, and a portion of the substrate are etched away to form trenches, wherein the trench density in the first region is less than the trench density in the second region.
[0057] Step S4: Form a dielectric layer that fills the trench and covers the hard mask layer;
[0058] Step S5: Grinding removes the dielectric layer and hard mask layer located on the stop layer;
[0059] Step S6: Remove the stop layer to expose the top surface of the gate structure.
[0060] The semiconductor device manufacturing method of this application involves forming a stop layer, first grinding to remove the dielectric layer and hard mask layer located on the stop layer to obtain a flat surface, and then removing the stop layer to expose the top surface of the gate structure, thus completing gate planarization. This method can inherit the surface flatness of the previous grinding step, thereby effectively controlling the consistency of the gate structure height in different regions. In other words, it can effectively control the gate height load in different regions, eliminating the influence of trench density differences and previous gate height differences on gate planarization. This method can also widen the process window to facilitate subsequent processes such as dummy gate removal and metal gate filling.
[0061] Below, for reference Figures 2 to 3E The method for manufacturing the semiconductor device of this application is described in detail, wherein, Figure 2 A flowchart illustrating a method for manufacturing a semiconductor device according to a specific embodiment of this application is shown. Figures 3A-3E The diagram shows a cross-sectional view of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of this application.
[0062] For example, the method for manufacturing the semiconductor device of this application includes the following steps:
[0063] First, execute step S1, as follows: Figure 3A As shown, a substrate 300 is provided, on which a gate structure is formed, wherein the substrate 300 includes at least a first region and a second region.
[0064] The semiconductor device in this application can be any suitable device known to those skilled in the art. In this embodiment, the technical solution of this application is explained and illustrated mainly by taking the case of a three-dimensional transistor as the semiconductor device.
[0065] In one example, substrate 300 is a silicon substrate, which may include at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors. Alternatively, substrate 300 may also include silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), or germanium-on-insulator (GeOI). Although several examples of materials that can form substrate 300 have been described herein, any material that can serve as substrate 300 falls within the spirit and scope of this application.
[0066] In one example, gate structures are formed on the substrate 300 in both the first and second regions. The substrate 300 may also include other regions besides the first and second regions; this application does not impose any limitations on this. For example, Figures 3A-3EFigure (a) shows a cross-sectional view of the first region. Figures 3A-3E Figure (b) shows a cross-sectional view of the second region.
[0067] In one example, such as Figure 3A As shown, the gate structure includes a gate dielectric layer 302 and a gate electrode layer 301 located on the gate dielectric layer. Exemplarily, the gate structure is a pseudo-gate structure, and the gate electrode layer 301 is a pseudo-gate electrode layer. The material of the gate electrode layer 301 can be a semiconductor material commonly used in the art, such as silicon. Specifically, the silicon can be amorphous silicon or polycrystalline silicon. The material of the gate electrode layer 301 is not limited to any one type, and will not be listed here. Exemplarily, the gate dielectric layer 302 serves an isolation function, and the material of the gate dielectric layer 302 includes, but is not limited to, silicon oxide.
[0068] In one example, such as Figure 3A As shown, a plurality of gate structures are formed on the substrate 300, and the plurality of gate structures extend along a first direction; as Figure 3A As shown, a plurality of fins 303 extending along a second direction intersecting the first direction are also formed on the substrate 300. A gate structure spans the fins 303, meaning that gate structures are formed on both the upper surface and side surfaces of the fins 303. Source regions 304 and drain regions 305 are formed on the regions of the fins 303 located on both sides of the gate structure, respectively. Exemplarily, the source regions 304 and drain regions 305 are epitaxial layers. Grooves can be formed in the predetermined regions for forming source regions 304 and drain regions 305 by etching the fins 303 on both sides of the gate structure, and then the epitaxial layer can be selectively grown in the grooves; alternatively, ion implantation can be performed on the fins 303 to form source regions 304 and drain regions 305. Exemplarily, the second direction is perpendicular to the first direction. Exemplarily, Figures 3A to 3E The diagrams shown are schematic cross-sectional views of the semiconductor device along the second direction.
[0069] In one example, the method for forming fin 303 includes the following steps: forming a patterned mask layer on the surface of a substrate 300, the patterned mask layer defining a pattern of fin 303, including the width, length, and position of fin 303; etching the substrate 300 using the patterned mask layer as a mask to form fin 303; and then removing the mask layer. It should be noted that the method for forming fin 303 is merely exemplary and is not limited to the methods described above.
[0070] In one example, such as Figure 3AAs shown, a dielectric layer 306 is formed between adjacent gate electrode layers 301, and a contact etch stop layer (CESL) 307 and a gate spacer layer 308 are formed between the dielectric layer 306 and the gate electrode layer 301. The dielectric layer 306 can be made of common insulating materials, such as silicon oxide, and this application does not limit its material composition. Exemplarily, the top surface of the dielectric layer 306 is flush with the top surface of the gate electrode layer 301. Exemplarily, the gate spacer layer 308 is located on both sides of the gate electrode layer 301, and the contact etch stop layer 307 is located between the gate spacer layer 308 and the dielectric layer 306. Exemplarily, the contact etch stop layer 307 and the gate spacer layer 308 can be made of common insulating materials; for example, the contact etch stop layer 307 can be made of silicon nitride, and the gate spacer layer 308 can be made of one or more of silicon oxide, silicon nitride, and silicon oxynitride, and this application does not limit its material composition. In this embodiment, as... Figure 3A As shown, the gate spacer layer 308 is a three-layer structure including a first sub-spacer layer 3081, a second sub-spacer layer 3082, and a third sub-spacer layer 3083; in other embodiments, the gate spacer layer 308 may also be a single-layer, double-layer, or three-layer or more structure, and this application does not limit it in this regard.
[0071] In one example, various deposition processes commonly used in the art can be employed to form the contact hole etch stop layer 307 and the gate spacer layer 308. The contact hole etch stop layer 307 is used to relieve stress and increase carrier mobility, thereby improving device performance. The gate spacer layer 308 is used to protect the gate structure and reduce the capacitance between the gate structure and the surrounding structure, thereby reducing resistance-capacitance delay.
[0072] Next, proceed to step S2, as follows: Figure 3A As shown, a stop layer 309 covering the gate structure and a patterned hard mask layer 310 are sequentially formed on the substrate 300.
[0073] In one example, the hard mask layer 310 includes a first sub-hard mask layer 3101 and a second sub-hard mask layer 3102. The first sub-hard mask layer 3101 includes a nitride layer, for example, the material of the first sub-hard mask layer 3101 can be silicon nitride; the second sub-hard mask layer includes an oxide layer, for example, the material of the second sub-hard mask layer 3102 can be silicon oxide. Exemplarily, various deposition processes commonly used in the art can be employed to form the stop layer 309 and the hard mask layer 310 covering the gate structure, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Exemplarily, the patterned hard mask layer 310 exposes the stop layer 309 in the region where a trench is to be formed. Exemplarily, as... Figure 3A As shown, the hard mask layer 310 also covers the dielectric layer 306, the contact hole etch stop layer 307, and the gate spacer layer 308.
[0074] In some examples, the material of the stop layer 309 is the same as that of the gate electrode layer 301. Exemplarily, both the material of the stop layer 309 and the gate electrode layer 301 include silicon; specifically, the silicon can be polycrystalline silicon or amorphous silicon. Exemplarily, the material of the stop layer 309 can also be different from that of the gate electrode layer 301, as long as it satisfies the requirement of serving as a polishing stop layer in the subsequent polishing step to remove the dielectric layer and hard mask layer located on the stop layer 309 (i.e., step S5). That is, in this polishing step, the stop layer 309 should be more difficult to polish than the dielectric layer and hard mask layer.
[0075] In one example, such as Figure 3A As shown, forming a patterned hard mask layer 310 includes: forming a hard mask layer 310; sequentially forming a spin-coated carbon (SOC) layer 311, an anti-reflective coating 312, and a patterned photoresist layer 313 on the hard mask layer 310; using the patterned photoresist layer 313 as a mask, sequentially etching the anti-reflective coating 312, the spin-coated carbon layer 311, and the hard mask layer 310 to obtain the patterned hard mask layer 310. The spin-coated carbon layer 311 and the anti-reflective coating 312 can reduce light reflection and suppress standing wave effects during the formation of the patterned photoresist layer 313, thereby improving the stability and pattern quality of the patterned photoresist layer 313. Exemplarily, the anti-reflective coating 312 includes a silicon-containing anti-reflective coating. Exemplarily, the spin-coated carbon layer 311 can also improve the flatness of the film layer.
[0076] For example, taking the case where both the stop layer 309 and the gate electrode layer 301 are made of polysilicon, in the basic process of related technologies, the polysilicon gate electrode layer 301 serves as the etching stop layer for etching a patterned hard mask layer 310 using a patterned photoresist layer 313 as a mask. In this application, the stop layer 309, also made of polysilicon, is used as the etching stop layer for etching a patterned hard mask layer 310 using a patterned photoresist layer 313 as a mask. The thickness and material of the hard mask layer 310 can be consistent with those in the basic process. That is, the process of forming the patterned hard mask layer 310 in this application is largely compatible with the basic process, requiring no additional process development. This is very friendly to the continuity of process development and does not require adding too many steps, which is beneficial for controlling production costs and process stability.
[0077] Next, proceed to step S3, as follows: Figures 3A to 3BAs shown, using a patterned hard mask layer 310 as a mask, a portion of the stop layer 309, a portion of the gate structure, and a portion of the substrate 300 are etched away to form a trench 314. The density of trenches 314 in the first region is less than the density of trenches 314 in the second region. Exemplarily, the second sub-hard mask layer 3102 is completely consumed during the formation of the trench 314. Exemplarily, removing a portion of the gate structure refers to removing a part of the gate structure. When multiple gate structures are formed, removing a portion of the gate structure refers to removing at least a portion of a portion of the multiple gate structures. For example, when three gate structures are formed, removing a portion of the gate structure can be removing a portion of one gate structure, removing a portion of two gate structures, or removing a portion of all three gate structures. Figure 3B As shown, a portion of two gate structures was removed in the first region, and a portion of three gate structures was removed in the second region.
[0078] In one example, taking the case where both the stop layer 309 and the gate electrode layer 301 are made of polysilicon, since the stop layer 309 is very thin and has the same material as the gate electrode layer 301, the morphology of the etched trench 314 can easily be consistent with the trench morphology in the basic process of the related technology. That is, it can be well compatible with the basic process without the need for additional process development. It is very friendly to the continuity of process development and does not require adding too many steps, which is beneficial to the control of production costs and process stability.
[0079] In one example, a portion of the stop layer 309, a portion of the gate structure, and a portion of the substrate 300 can be etched away using an SDB process to form a trench 314. The trench 314 extends through the fin 303 to achieve isolation of the active region.
[0080] Next, proceed to step S4, as follows: Figure 3C As shown, a dielectric layer is formed to fill the trench 314 and cover the hard mask layer 310. Exemplarily, since the second sub-hard mask layer 3102 is consumed during the formation of the trench 314, the dielectric layer covers the first sub-hard mask layer 3101.
[0081] In one example, such as Figure 3CAs shown, the dielectric layer includes a first dielectric layer 315, a second dielectric layer 316, and a third dielectric layer 317, forming a dielectric layer that fills a trench 314 and covers a hard mask layer 310. The process includes: forming a first dielectric layer 315 that covers the bottom and sidewalls of the trench 314 and covers the hard mask layer 310 (i.e., covers a first sub-hard mask layer 3101); forming a second dielectric layer 316 that fills the remaining portion of the trench 314 and covers the first dielectric layer 315, wherein a filling gap (not shown) is formed on the top surface of the second dielectric layer 316 located in the region of the trench 314; and forming a third dielectric layer 317 that covers the second dielectric layer 316. Exemplarily, various deposition processes commonly used in the art can be selected to form the first dielectric layer 315, the second dielectric layer 316, and the third dielectric layer 317. For example, the first dielectric layer 315 and the second dielectric layer 316 can be formed by ALD deposition, and the third dielectric layer 317 can be formed by plasma-enhanced chemical vapor deposition (PECVD). Exemplarily, the third dielectric layer 317 is used to reduce the gap filling. Exemplarily, the first dielectric layer 315, the second dielectric layer 316, and the third dielectric layer 317 can be made of commonly used dielectric materials. For example, the first dielectric layer 315 and the third dielectric layer 317 can be oxides (e.g., silicon oxide), and the second dielectric layer 316 can be a nitride (e.g., silicon nitride). This application does not limit this.
[0082] In one example, as described above, the morphology of the trench 314 etched in this application can easily be consistent with the trench morphology in the basic process. Therefore, the thickness and material of the dielectric layer formed in this step can be consistent with the basic process, thereby satisfying stress matching.
[0083] Next, proceed to step S5, as follows: Figures 3C to 3D As shown, grinding removes the dielectric layer and hard mask layer 310 (i.e., the first sub-hard mask layer 3101) located on the stop layer 309.
[0084] In one example, compared to the use of pseudo-polysilicon in a pseudo-gate structure as a stop layer in related technologies, the use of stop layer 309 as the stop layer in this application, due to its larger area, significantly enhances the stopping effect and results in a flat surface.
[0085] In one example, taking the material of both the stop layer 309 and the gate electrode layer 301 as polysilicon, the basic process of related technologies uses pseudo-polysilicon in the pseudo-gate structure as the stop layer. The material of the stop layer 309 in this application is also polysilicon. Therefore, the polishing step of this application is well compatible with the basic process. For example, the same polishing slurry can be used. There is no need to develop the process, which is very friendly to the continuity of process development. There is no need to add too many steps, which is conducive to the control of production costs and process stability.
[0086] Next, proceed to step S6, as follows: Figures 3D to 3E As shown, the stop layer 309 is removed to expose the top surface of the gate structure. Exemplarily, in this step, the stop layer 309 is removed to expose the top surface of the gate electrode layer 301. Wherein, when there are differences in the height of the front gate structure in different regions, the top surface of the gate electrode layer 301 in all regions should be exposed in this step.
[0087] In one example, a flat surface can be obtained in the aforementioned polishing step. The surface flatness of the aforementioned polishing step can be inherited during the process of removing the stop layer 309 to expose the top surface of the gate structure. A highly consistent gate structure can be obtained, that is, the height consistency of the gate structure in different regions can be effectively controlled, the gate height load in different regions can be effectively controlled, the influence of trench density differences and front layer gate height differences on gate planarization can be eliminated, and the process window can be widened to facilitate subsequent processes such as pseudo-gate removal and metal gate filling.
[0088] In one example, after removing the stop layer 309 to expose the top surface of the gate structure, the process further includes removing a portion of the gate electrode layer 301 to make the remaining gate electrode layer 301 have a preset thickness. For example, if the thickness of the gate electrode layer 301 after the polishing step is 600 angstroms, the preset thickness could be 500 angstroms, meaning that after removing the stop layer 309 to expose the top surface of the gate structure, a 100-angstrom thickness of the gate electrode layer 301 is then removed.
[0089] In one example, a polishing process is performed to remove the stop layer 309 and a portion of the gate electrode layer 301 so that the remaining gate electrode layer 301 has a preset thickness. This polishing process essentially pushes the material downwards, thus effectively inheriting the surface smoothness of the previous polishing process. Exemplarily, a non-selective polishing slurry is used to perform the polishing process. Alternatively, a dry etching process can be employed to etch downwards to remove the stop layer 309 and a portion of the gate electrode layer 301 so that the remaining gate electrode layer 301 has a preset thickness.
[0090] In one example, before performing the polishing process, the method further includes: measuring the total thickness of the stop layer 309 and the gate electrode layer 301 to obtain a first thickness; and based on the first thickness and a preset thickness, determining the time required to polish the gate electrode layer 301 to the preset thickness, denoted as the preset time. Performing the polishing process includes: performing the polishing process for the preset time to remove the stop layer 309 and a portion of the gate electrode layer 301 so that the remaining thickness of the gate electrode layer 301 is the preset thickness. In one example, when the material of the stop layer 309 is the same as the material of the gate electrode layer 301, it is easier to measure the total thickness of the stop layer 309 and the gate electrode layer 301.
[0091] In one example, such as Figure 1C As shown, the gate planarization process in related technologies uses pseudo-polysilicon 130 as a stop layer, which has a poor stopping effect and is prone to over-grinding of the dielectric layer 140 between the pseudo-gate structures, resulting in the formation of a depression 150 in the dielectric layer 140. When the metal gate is filled in the subsequent process, metal is likely to remain in the depression 150, which can lead to short circuits in the device. In contrast, in this application, the dielectric layer and hard mask layer on the stop layer 309 are first ground off, and then the grinding process is performed to remove the stop layer 309 and a portion of the gate electrode layer 301 so that the remaining gate electrode layer 301 is at a predetermined thickness. This prevents the formation of a depression 150 in the dielectric layer 140, thereby avoiding short circuits caused by metal residues.
[0092] This concludes the description of the key steps in the semiconductor device manufacturing method of this application. The complete semiconductor device fabrication may also include other steps, such as dummy gate removal and metal gate filling processes, which will not be elaborated here. It is worth mentioning that the order of the above steps can be adjusted without conflict.
[0093] In summary, the semiconductor device manufacturing method of this application involves forming a stop layer, first grinding away the dielectric layer and hard mask layer located on the stop layer to obtain a flat surface, and then removing the stop layer to expose the top surface of the gate structure, thus completing gate planarization. This method inherits the surface flatness of the previous grinding step, effectively controlling the consistency of the gate structure height in different regions. This effectively controls the gate height load in different regions, eliminating the influence of trench density differences and previous gate height differences on gate planarization. It also widens the process window, facilitating subsequent processes such as dummy gate removal and metal gate filling. Furthermore, the solution of this application is highly compatible with basic processes, requiring no additional process development, exhibiting excellent continuity in process development, and minimizing the need for additional steps. This contributes to better control of production costs and process stability.
[0094] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will arise in the mind of those skilled in the art, all of which will fall within the spirit and scope of the concept disclosed herein. More specifically, various modifications and changes may be made in terms of the arrangement and / or components of the subject matter within the scope of this disclosure, the drawings, and the appended claims. In addition to modifications and changes in the components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, The method includes: A substrate is provided on which a gate structure is formed, wherein the substrate includes at least a first region and a second region; A stop layer covering the gate structure and a patterned hard mask layer are sequentially formed on the substrate; Using the patterned hard mask layer as a mask, a portion of the stop layer, a portion of the gate structure, and a portion of the substrate are etched away to form trenches, wherein the density of the trenches in the first region is less than the density of the trenches in the second region; A dielectric layer is formed to fill the trench and cover the hard mask layer; Grinding removes the dielectric layer and the hard mask layer located on the stop layer; Remove the stop layer to expose the top surface of the gate structure.
2. The manufacturing method according to claim 1, characterized in that, The gate structure includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer; A dielectric layer is also formed between adjacent gate electrode layers, and a contact hole etch stop layer and a gate spacer layer are also formed between the dielectric layer and the gate electrode layer.
3. The manufacturing method according to claim 2, characterized in that, After removing the stop layer to expose the top surface of the gate structure, the process further includes: Remove a portion of the gate electrode layer to make the remaining gate electrode layer the thickness of a preset thickness.
4. The manufacturing method according to claim 3, characterized in that, A grinding process is performed to remove the stop layer and a portion of the gate electrode layer so that the remaining gate electrode layer has the preset thickness.
5. The manufacturing method according to claim 4, characterized in that, Before performing the grinding process, the method further includes: measuring the total thickness of the stop layer and the gate electrode layer to obtain a first thickness; and based on the first thickness and the preset thickness, obtaining the time required to grind the gate electrode layer to the preset thickness, which is denoted as the preset time. Performing the grinding process includes: The grinding process is performed for the preset duration to remove the stop layer and a portion of the gate electrode layer so that the remaining gate electrode layer has the preset thickness.
6. The manufacturing method according to claim 2, characterized in that, The material of the stop layer is the same as the material of the gate electrode layer; and / or The thickness of the stop layer ranges from 10 angstroms to 60 angstroms.
7. The manufacturing method according to claim 6, characterized in that, Both the stop layer and the gate electrode layer are made of silicon.
8. The manufacturing method according to any one of claims 1 to 7, characterized in that, A plurality of gate structures are formed on the substrate, and the plurality of gate structures extend along a first direction; The substrate is further provided with a plurality of fins extending along a second direction that intersects the first direction. The gate structure spans the fins. The regions on both sides of the gate structure of the fins are respectively formed as active and drain regions. The trench penetrates the fins.
9. The manufacturing method according to any one of claims 1 to 7, characterized in that, The dielectric layer includes a first dielectric layer, a second dielectric layer, and a third dielectric layer, forming a dielectric layer that fills the trench and covers the hard mask layer, including: A first dielectric layer is formed, which covers the bottom and sidewalls of the trench and the hard mask layer; A second dielectric layer is formed, which fills the remaining portion of the trench and covers the first dielectric layer; A third dielectric layer is formed that covers the second dielectric layer.
10. The manufacturing method according to any one of claims 1 to 7, characterized in that, Forming the patterned hard mask layer includes: Form a hard mask layer; A spin-coated carbon layer, an anti-reflective coating, and a patterned photoresist layer are sequentially formed on the hard mask layer; Using the patterned photoresist layer as a mask, the anti-reflective coating, the spin-coated carbon layer, and the hard mask layer are etched to obtain the patterned hard mask layer.