Method of manufacturing a semiconductor structure
By forming a capping layer in the semiconductor structure to fill the openings, the problem of short circuits between conductive components is solved, achieving effective isolation of the landing pad and integrity of the conductive components, thus preventing short circuits from occurring.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- WINBOND ELECTRONICS CORP
- Filing Date
- 2025-02-26
- Publication Date
- 2026-07-24
Smart Images
Figure CN122458771A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a method for manufacturing a semiconductor structure, and more particularly to a method for manufacturing a semiconductor structure that can prevent short circuits. Background Technology
[0002] In semiconductor devices, landing pads are used as components for electrical connections. However, the process of forming landing pads often results in short circuits between conductive components. For example, the process of forming landing pads often leads to short circuits between two adjacent landing pads. Summary of the Invention
[0003] The present invention provides a method for manufacturing a semiconductor structure that can prevent short circuits from forming between conductive components.
[0004] This invention proposes a method for manufacturing a semiconductor structure, comprising the following steps: Providing a substrate. Forming a plurality of stacked structures on the substrate. Separating the plurality of stacked structures from each other. Forming a plurality of first spacers on the sidewalls of the plurality of stacked structures. Forming a plurality of second spacers on the plurality of first spacers. Forming a plurality of spacer layers on the plurality of second spacers. Forming a plurality of first dielectric layers on the plurality of spacer layers. Removing a portion of the plurality of second spacers and a portion of the plurality of first dielectric layers, thereby forming a plurality of first openings above the plurality of second spacers and a plurality of second openings above the plurality of first dielectric layers. Forming a plurality of capping layers. Filling the plurality of first openings with the plurality of capping layers.
[0005] Based on the above, in the semiconductor structure manufacturing method proposed in this invention, multiple top cap layers fill multiple first openings, thus the multiple top cap layers can at least protect multiple second spacers. In this way, in the subsequent process of forming landing pads, the spacer structure located on the sidewalls of the stacked structure can have a flatter surface profile and a more complete structure. Therefore, in the subsequent process of forming landing pads, since the spacer structure can have a flatter surface profile, the material layers used to form the landing pads can be effectively patterned, forming landing pads that are separated from each other, thereby effectively preventing short circuits between adjacent landing pads. Furthermore, in the subsequent process of forming landing pads, since the spacer structure can have a more complete structure, isolation between other conductive components (e.g., between contacts and bit lines) can be effectively achieved, preventing short circuits between other conductive components (e.g., between contacts and bit lines).
[0006] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description
[0007] Figures 1A to 1IThis is a cross-sectional view of the manufacturing process of a semiconductor structure according to some embodiments of the present invention;
[0008] Figures 2A to 2D This is a cross-sectional view of the manufacturing process of a semiconductor structure according to some embodiments of the present invention.
[0009] Explanation of icon numbers:
[0010] 10, 20: Semiconductor Structure
[0011] 100: Substrate
[0012] 102: Isolation Structure
[0013] 104: Stacked Structure
[0014] 106, 146: Conductive layer
[0015] 108: Bit Line
[0016] 110: Hard mask layer
[0017] 112, 148: Barrier layer
[0018] 114, 122, 124, 134, 136, 138: Dielectric layers
[0019] 128, 130, 132b: Spacers
[0020] 132: Spacer material layer
[0021] 132a: Spacer layer
[0022] 140: Top cover material layer
[0023] 140a, 140c: Top cover layer
[0024] 140b: Oxide layer
[0025] 142: Contact element
[0026] 144: Landing pad
[0027] D1, D2: Depth
[0028] OP1, OP2, OP3: Openings
[0029] S1: Top surface
[0030] SL: Slit Detailed Implementation
[0031] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.
[0032] Figures 1A to 1I This is a cross-sectional view of the manufacturing process of a semiconductor structure according to some embodiments of the present invention.
[0033] Please refer to Figure 1A A substrate 100 is provided. The substrate 100 may be a semiconductor substrate, such as a silicon substrate. Furthermore, an isolation structure 102 may be formed in the substrate 100. The isolation structure 102 may be a shallow trench isolation structure. The material of the isolation structure 102 is, for example, silicon oxide. Additionally, although not shown in the figures, other desired components (e.g., doped regions and / or buried word line structures, etc.) may be formed in the substrate 100.
[0034] Next, a plurality of stacked structures 104 are formed on the substrate 100. The plurality of stacked structures 104 are separated from each other. The plurality of stacked structures 104 may include a plurality of bit line stacked structures. The stacked structure 104 (e.g., bit line stacked structure) may include a conductive layer 106, a bit line 108, and a hard mask layer 110. The conductive layer 106 is located on the substrate 100 and has a portion that contacts the substrate 100. The portion of the conductive layer 106 that contacts the substrate 100 can be used as a bit line contact. The material of the conductive layer 106 is, for example, a conductive material such as doped polysilicon. The bit line 108 is located on the conductive layer 106. The material of the bit line 108 is, for example, a conductive material such as tungsten. The hard mask layer 110 is located on the bit line 108. The hard mask layer 110 may be a single-layer structure or a multi-layer structure. The material of the hard mask layer 110 is, for example, silicon nitride. The stacked structure 104 (e.g., bit line stacked structure) may also include a barrier layer 112. The barrier layer 112 is located between the conductive layer 106 and the bit line 108. The material of the barrier layer 112 is, for example, titanium, titanium nitride, or a combination thereof.
[0035] The stacked structure 104 (e.g., a bit line stack) may further include a dielectric layer 114. The dielectric layer 114 is located on the substrate 100. The dielectric layer 114 may be located on the isolation structure 102. The dielectric layer 114 is located between the conductive layer 106 and the substrate 100. The dielectric layer 114 may be a single-layer structure or a multi-layer structure. In this embodiment, the dielectric layer 114 may include dielectric layers 122 and 124. The dielectric layer 122 is located on the substrate 100. The material of the dielectric layer 122 is, for example, silicon oxide. The dielectric layer 124 is located on the dielectric layer 122. The material of the dielectric layer 124 is, for example, silicon nitride.
[0036] Next, a plurality of spacers 128 are formed on the sidewalls of the plurality of stacked structures 104. The spacers 128 may be a single-layer or multi-layer structure. In some embodiments, slits SL may be provided in the spacers 128. The material of the spacers 128 is, for example, silicon carbide (SiCO), silicon nitride, or a combination thereof. Then, a plurality of spacers 130 are formed on the plurality of spacers 128. The material of the spacers 128 is, for example, silicon oxide. Next, a spacer material layer 132 may be formed on the plurality of spacers 128, the plurality of spacers 130, the plurality of stacked structures 104, and the substrate 100. The material of the spacer material layer 132 is, for example, silicon nitride.
[0037] Subsequently, a plurality of dielectric layers 134 may be formed on the spacer material layer 132. The dielectric layers 134 may be located between two adjacent stacked structures 104. The material of the dielectric layers 134 is, for example, silicon oxide. In some embodiments, a dielectric layer 136 may be formed on the spacer material layer 132 and the dielectric layers 134. The material of the dielectric layer 136 is, for example, silicon oxide. In some embodiments, a dielectric layer 138 may be formed on the dielectric layer 136. The material of the dielectric layer 138 is, for example, silicon nitride.
[0038] Please refer to Figure 1B A back-etching process is performed to remove a portion of the spacer material layer 132, forming multiple spacer layers 132a and exposing multiple spacers 130. Thus, multiple spacer layers 132a can be formed on the multiple spacers 130, and multiple dielectric layers 134 can be formed on the multiple spacer layers 132a. The cross-sectional shape of the spacer layer 132a can be U-shaped. In the above-described back-etching process, dielectric layers 138 and 136, portions of multiple spacers 128, portions of multiple spacers 130, portions of multiple stacked structures 104 (e.g., portions of hard mask layers 110), and portions of multiple dielectric layers 134 can be removed simultaneously. The back-etching process is, for example, a dry etching process.
[0039] Please refer to Figure 1C A portion of multiple spacers 130 and a portion of multiple dielectric layers 134 are removed, and multiple openings OP1 are formed above the multiple spacers 130 and multiple openings OP2 are formed above the multiple dielectric layers 134. The depth D1 of the multiple openings OP1 may be less than the depth D2 of the multiple openings OP2. The method for removing a portion of the multiple spacers 130 and a portion of the multiple dielectric layers 134 is, for example, wet etching.
[0040] Please refer to Figure 1DA capping material layer 140 is formed on multiple spacers 128, multiple spacers 130, multiple spacer layers 132a, multiple stacked structures 104, and multiple dielectric layers 134. The capping material layer 140 may fill multiple openings OP1. The capping material layer 140 may be conformally formed in multiple openings OP2. The material of the capping material layer 140 is, for example, silicon nitride. The method for forming the capping material layer 140 is, for example, atomic layer deposition (ALD).
[0041] Please refer to Figure 1E A back-etching process is performed on the top cover material layer 140 to form multiple top cover layers 140a. Multiple top cover layers 140a fill multiple openings OP1. In this embodiment, the multiple top cover layers 140a can cover the top surface S1 of multiple stacked structures 104. The back-etching process is, for example, a dry etching process.
[0042] Please refer to Figure 1F Multiple dielectric layers 134 can be removed. The removal method for multiple dielectric layers 134 is, for example, wet etching.
[0043] Please refer to Figure 1G A portion of a plurality of spacer layers 132a can be removed to form a plurality of spacers 132b, thereby exposing a plurality of openings OP2 to the substrate 100. In some embodiments, a portion of the top cap layer 140a is removed during the process of removing a portion of the plurality of spacer layers 132a. The method for removing a portion of the plurality of spacer layers 132a is, for example, dry etching. Then, a portion of the substrate 100 can be removed, thereby extending the plurality of openings OP2 into the substrate 100. The method for removing a portion of the substrate 100 is, for example, dry etching.
[0044] Please refer to Figure 1H Multiple contacts 142 can be formed in multiple openings OP2. The material of the contacts 142 is, for example, a conductive material such as doped polysilicon. In some embodiments, the method of forming the contacts 142 may include the following steps: First, a contact material layer (not shown) is formed to fill the openings OP2. Then, a portion of the contact material layer is removed to form multiple contacts 142. The method for removing a portion of the contact material layer is, for example, an etch-back method (e.g., dry etching).
[0045] Please refer to Figure 1IMultiple landing pads 144 can be formed on multiple contacts 142. An opening OP3 may be provided on one side of each landing pad 144. The landing pad 144 can be a single-layer or multi-layer structure. In this embodiment, the landing pad 144 may include a conductive layer 146 and a barrier layer 148. The conductive layer 146 is located on the contacts 142. The barrier layer 148 is located between the conductive layer 146 and the contacts 142. The material of the conductive layer 146 is, for example, a conductive material such as tungsten. The material of the barrier layer 148 is, for example, titanium, titanium nitride, or a combination thereof.
[0046] In some embodiments, the method for forming the conductive layer 146, the barrier layer 148, and the opening OP3 may include the following steps. First, a material layer (not shown) for forming the barrier layer 148 and a material layer (not shown) for forming the conductive layer 146 may be formed sequentially. Next, the material layers for forming the conductive layer 146 and the barrier layer 148 are patterned to form the conductive layer 146, the barrier layer 148, and the opening OP3. In the above patterning process, the material layers for forming the conductive layer 146 and the barrier layer 148 can be patterned by photolithography and etching processes (e.g., dry etching).
[0047] In subsequent processes, other necessary components (such as capacitors) can be formed to complete the fabrication of semiconductor devices (such as memory devices), which will be omitted here.
[0048] As can be seen from the above embodiments, in the manufacturing method of semiconductor structure 10, multiple top cap layers 140a are filled with multiple openings OP1, so the multiple top cap layers 140a can at least protect multiple spacers 130. Thus, in the subsequent process of forming landing pads 144, the spacer structures (e.g., spacers 128, 130, and 132b) located on the sidewalls of the stacked structure 104 can have a flatter surface profile and a more complete structure. Therefore, in the subsequent process of forming landing pads 144, since the spacer structures (e.g., spacers 128, 130, and 132b) can have a flatter surface profile, the material layers used to form landing pads 144 can be effectively patterned, forming landing pads 144 that are separated from each other, thereby effectively preventing short circuits between adjacent landing pads 144. Furthermore, in the subsequent process of forming the landing pad 144, since the spacer structure (e.g., spacer 128, spacer 130 and spacer 132b) can have a more complete structure, it can effectively isolate other conductive components (e.g., between contact 142 and bit line 108) to prevent short circuits from forming between other conductive components (e.g., between contact 142 and bit line 108).
[0049] Figures 2A to 2DThis is a cross-sectional view of the manufacturing process of a semiconductor structure according to some embodiments of the present invention.
[0050] Please refer to Figure 2A Provide such as Figure 1D The structure. Furthermore. Figure 1D The structure and manufacturing method of the [component] have been described in detail in the above embodiments and will not be described again here.
[0051] Please refer to Figure 2B An oxidation process is performed on the top cover material layer 140 to form an oxide layer 140b and a plurality of top cover layers 140c. In some embodiments, a portion of the spacer layer 132a is oxidized to become part of the oxide layer 140b. The plurality of top cover layers 140c fills a plurality of openings OP1. In this embodiment, the plurality of top cover layers 140c may not cover the top surface S1 of the plurality of stacked structures 104.
[0052] Please refer to Figure 2C The oxide layer 140b can be removed. In the process of removing the oxide layer 140b, multiple dielectric layers 134 can be removed simultaneously. The removal method for the oxide layer 140b and the multiple dielectric layers 134 is, for example, wet etching.
[0053] Please refer to Figure 2D It can be performed like Figures 1G to 1I The steps, and form Figure 2D The semiconductor structure 20. Furthermore, in Figure 2D Semiconductor structure 20 and Figure 1I In the semiconductor structure 10, the same or similar components are represented by the same symbols, and their descriptions are omitted.
[0054] In subsequent processes, other necessary components (such as capacitors) can be formed to complete the fabrication of semiconductor devices (such as memory devices), which will be omitted here.
[0055] In summary, in the semiconductor structure manufacturing method of the above embodiments, the spacers can be protected by a capping layer. As a result, in the subsequent process of forming landing pads, the spacer structure located on the sidewalls of the stacked structure can have a flatter surface profile and a more complete structure. Therefore, in the subsequent process of forming landing pads, short circuits between adjacent landing pads and between other conductive components (e.g., between contacts and bit lines) can be effectively prevented.
[0056] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for manufacturing a semiconductor structure, comprising: Provide substrate; Multiple stacked structures are formed on the substrate, wherein the multiple stacked structures are separated from each other; A plurality of first spacers are formed on the sidewalls of the plurality of stacked structures; A plurality of second spacers are formed on a plurality of first spacers; Multiple spacer layers are formed on multiple second spacers; A plurality of first dielectric layers are formed on the plurality of spacer layers; Remove a portion of a plurality of second spacers and a portion of a plurality of first dielectric layers, and form a plurality of first openings above the plurality of second spacers and a plurality of second openings above the plurality of first dielectric layers; as well as Multiple top cover layers are formed, wherein multiple top cover layers fill multiple first openings.
2. The method for manufacturing a semiconductor structure according to claim 1, wherein the depth of the plurality of first openings is less than the depth of the plurality of second openings.
3. The method of manufacturing a semiconductor structure according to claim 1, wherein the method of removing a portion of the plurality of second spacers and a portion of the plurality of first dielectric layers includes wet etching.
4. The method for manufacturing a semiconductor structure according to claim 1, wherein the method for forming the plurality of spacer layers includes: A spacer material layer is formed on a plurality of first spacers, a plurality of second spacers, a plurality of stacked structures and the substrate; A plurality of the first dielectric layers are formed on the spacer material layer; as well as A back etching process is performed to remove a portion of the spacer material layer, thereby forming a plurality of spacer layers and exposing a plurality of the second spacers.
5. The method for manufacturing a semiconductor structure according to claim 4, wherein... In the back-etching process, portions of multiple first spacers, portions of multiple second spacers, portions of multiple stacked structures, and portions of multiple first dielectric layers are removed simultaneously.
6. The method for manufacturing a semiconductor structure according to claim 4, wherein the etch-back process includes a dry etching process.
7. The method for manufacturing a semiconductor structure according to claim 1, wherein the method for forming the plurality of capping layers comprises: A top cover material layer is formed on a plurality of first spacers, a plurality of second spacers, a plurality of spacer layers, a plurality of stacked structures and a plurality of first dielectric layers, wherein the top cover material layer fills a plurality of first openings; as well as The top cover material layer is etched back to form multiple top cover layers.
8. The method of manufacturing a semiconductor structure according to claim 7, wherein the plurality of top cap layers cover the top surface of the plurality of stacked structures.
9. The method for manufacturing a semiconductor structure according to claim 7, wherein the etch-back process includes a dry etching process.
10. The method for manufacturing a semiconductor structure according to claim 1, wherein the method for forming the plurality of capping layers comprises: A top cover material layer is formed on a plurality of first spacers, a plurality of second spacers, a plurality of spacer layers, a plurality of stacked structures and a plurality of first dielectric layers, wherein the top cover material layer fills a plurality of first openings; as well as The top cover material layer is subjected to an oxidation process to form an oxide layer and a plurality of the top cover layers.
11. The method for manufacturing a semiconductor structure according to claim 10, further comprising: Remove the oxide layer.
12. The method for manufacturing a semiconductor structure according to claim 11, wherein... In the process of removing the oxide layer, multiple first dielectric layers are also removed simultaneously.
13. The method for manufacturing a semiconductor structure according to claim 12, wherein the method for removing the oxide layer and the plurality of first dielectric layers includes wet etching.
14. The method of manufacturing a semiconductor structure according to claim 10, wherein the plurality of top cap layers do not cover the top surface of the plurality of stacked structures.
15. The method for manufacturing a semiconductor structure according to claim 1, further comprising: Remove multiple first dielectric layers; A portion of the plurality of spacer layers is removed to form a plurality of third spacers, and the plurality of second openings are made to expose the substrate; as well as Multiple contacts are formed in the multiple second openings.
16. The method for manufacturing a semiconductor structure according to claim 15, further comprising: Before forming the plurality of contacts, a portion of the substrate is removed, such that the plurality of second openings extend into the substrate.
17. The method of manufacturing a semiconductor structure according to claim 15, wherein the method of removing a portion of the plurality of spacer layers includes dry etching.
18. The method for manufacturing a semiconductor structure according to claim 1, wherein the plurality of stacked structures comprises a plurality of bit line stacked structures.
19. The method for manufacturing a semiconductor structure according to claim 18, wherein the bit line stack structure comprises: A conductive layer is located on the substrate and has a portion in contact with the substrate; Bit lines are located on the conductive layer; as well as A hard mask layer is located on the bit line.
20. The method for manufacturing a semiconductor structure according to claim 19, wherein the bit line stack structure further comprises: The second dielectric layer is located between the conductive layer and the substrate.