An ultrathin Micro VCSEL chip structure and manufacturing method

Abstract

The application discloses an ultrathin Micro VCSEL chip structure and a manufacturing method, wherein a chip core structure is free of a GaAs growth substrate, and a transparent lens, a cutoff layer, an N-DBR layer, an MQW multi-quantum well layer, a high-aluminum AlGaAs layer, a P-DBR layer and a contact layer are sequentially arranged from bottom to top, and electric interconnection is realized in cooperation with a flip-chip electrode structure; the manufacturing method comprises the following steps: firstly, completing front device preparation; then, temporarily bonding and removing the growth substrate through wet etching; finally, preparing a lens on the surface of the cutoff layer and unbonding; the application completely eliminates light scattering loss caused by a thick substrate, greatly improves light beam collimation and coupling efficiency, and improves coupling efficiency; meanwhile, the chip is thinned, the total thickness can be controlled to be less than 20 microns, the device thermal resistance is reduced, and high-power working stability is remarkably improved; the process is compatible with an existing semiconductor production line, is easy to mass produce, and is suitable for optical communication, 3D sensing, laser radar and other fields.

Description

Technical Field

[0001] This invention relates to the fields of optoelectronics, microelectronics and power devices, specifically to an ultrathin Micro VCSEL chip structure and manufacturing method. Background Technology

[0002] VCSELs (Vertical-cavity Surface-emitting Lasers) have been widely used in optical communication modules, 3D sensing, facial recognition, lidar, medical testing and other fields due to their advantages such as low threshold current, single longitudinal mode output, circular beam, easy integration and low cost.

[0003] In practical applications, most scenarios require VCSEL devices to have high beam quality, especially to maintain a low divergence angle and high collimation at high output power to achieve higher optical coupling efficiency. However, traditional upright VCSELs suffer from problems such as light blocking by the emitting electrode and long heat dissipation paths, while existing flip-chip VCSEL solutions still have significant drawbacks.

[0004] Chinese invention patent application number 202210751501.8 discloses a flip-chip VCSEL structure and its fabrication method. The structure includes a substrate, a first Bragg mirror layer, a quantum well layer, a second Bragg mirror layer, and a dielectric film layer. A microlens structure with focusing function is formed on the first surface of the substrate. This solution simplifies the packaging process by incorporating a microlens, but it has a core drawback: after light exits through the oxide layer window, it needs to pass through a GaAs growth substrate hundreds of micrometers thick. Severe scattering and refraction losses occur during light transmission in the thick substrate, leading to a significant decrease in beam collimation and an increase in divergence angle, ultimately severely limiting the improvement of coupling efficiency. Simultaneously, the presence of a thick substrate restricts the ultra-thin development of VCSEL chips, making them unsuitable for the application requirements of miniaturized optoelectronic integrated systems. Furthermore, the thick substrate introduces higher thermal resistance, deteriorating the heat dissipation performance and long-term reliability of the device under high-power operation. Summary of the Invention

[0005] The purpose of this invention is to provide an ultra-thin Micro VCSEL chip structure and manufacturing method, overcoming the core problems of existing flip-chip VCSELs, such as high light transmission and scattering loss, low beam collimation, and insufficient coupling efficiency due to the retention of a thick GaAs growth substrate; achieving an ultra-thin design for the MicroVCSEL chip, while further improving beam focusing capability to meet the integration requirements of miniaturized optoelectronic systems; being compatible with mature III-V semiconductor wafer manufacturing processes to ensure device fabrication yield and long-term operational reliability; and optimizing the chip heat dissipation path to reduce device thermal resistance and improve operational stability under high-power conditions.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: An ultrathin Micro VCSEL chip structure includes, from bottom to top, a transparent lens, a cutoff layer, an N-DBR layer, an MQW multi-quantum well layer, a high-aluminum AlGaAs layer, a P-DBR layer, and a contact layer; The sides of the high-aluminum AlGaAs layer are oxidized to form a high-aluminum AlGaAs oxide layer, and a conductive window is formed on the high-aluminum AlGaAs oxide layer. The upper surface of the contact layer is provided with a P-contact metal; The chip structure is provided with a stepped structure that is etched downward from the upper surface of the contact layer to the N-DBR layer, and the upper surface of the N-DBR layer exposed by the stepped structure is provided with N contact metal; The upper surface of the N-DBR layer and the upper surface of the contact layer are covered with an insulating dielectric layer. The insulating dielectric layer has interconnect windows at the positions corresponding to the P contact metal and N contact metal. The P contact metal and N contact metal make ohmic contact with the contact layer and N-DBR layer respectively through the interconnect windows. The upper surfaces of the insulating dielectric layer, the upper surfaces of the P contact metal, and the upper surfaces of the N contact metal are covered with an insulating compound layer. Electrode windows are opened in the insulating compound layer at the positions corresponding to the P contact metal and the N contact metal. P / N electrodes are disposed on the upper surface of the insulating compound layer. The P / N electrodes are electrically connected to the P contact metal and the N contact metal respectively through the electrode windows. The cutoff layer is a wet-etched cutoff layer, the chip structure has no GaAs growth substrate, and the transparent lens is directly fabricated on the lower surface of the cutoff layer.

[0007] In a preferred embodiment, the material of the stop layer is any one of GaInP, GaAs, or AlGaAs, and the thickness of the stop layer is 20nm~500nm, which is used to precisely control the endpoint of wet etching and avoid damage to the epitaxial functional layer.

[0008] In a preferred embodiment, the transparent lens is made of any one of the organic transparent materials selected from PI, PMMA, PMGI, or SU-8, and the thickness of the transparent lens is 2μm to 50μm. The transparent lens is a spherical lens prepared by nanoimprinting or dry etching processes, and is symmetrically arranged with the central axis of the conductive window to achieve precise beam focusing.

[0009] In a preferred embodiment, both the N-DBR layer and the P-DBR layer are periodic Bragg reflection structures formed by alternating stacks of semiconductor materials with an optical thickness of 1 / 4 of the central reflection wavelength; the periodic logarithm of the P-DBR layer is greater than that of the N-DBR layer, and the reflectivity of the P-DBR layer is higher than that of the N-DBR layer, so that the light emission direction of the chip is to the N-DBR layer side.

[0010] In a preferred embodiment, the high-alumina AlGaAs oxide layer is prepared by wet oxidation or plasma oxidation processes, the conductive window is circular, and the conductive window is symmetrically arranged with respect to the central axis of the transparent lens.

[0011] In a preferred embodiment, the contact layer is a heavily doped GaAs layer with a thickness of 30 nm to 300 nm; the N-contact metal is an AuGe / Ni / Au stacked structure, and the P-contact metal is a Ti / Pt / Au stacked structure.

[0012] In a preferred embodiment, the insulating dielectric layer is made of any one of SiO2, Si3N4, or Al2O3, with a thickness of 50nm to 300nm; the insulating compound layer is made of any one of SiO2, Si3N4, TiO2, or MgF2, an inorganic insulating material, with a thickness of 1μm to 5μm; the electrode window is a through-hole extending from the upper surface to the lower surface of the insulating compound layer, and the aperture of the electrode window gradually increases from the bottom surface to the top surface, thereby improving the electrode step coverage and interconnection reliability.

[0013] In a preferred embodiment, the P / N electrode is a stacked structure formed by any one or more metals selected from Cr, Ni, Pt, Ti, Au, and Al, and the top layer material of the P / N electrode is any one of Ti, Cr, and Ni or an alloy thereof, with a thickness of 0.8 μm to 2.3 μm.

[0014] This application also provides a method for manufacturing an ultrathin Micro VCSEL chip, comprising the following steps: S1. Epitaxial wafer fabrication: A VCSEL epitaxial structure is provided, wherein the epitaxial structure comprises, from bottom to top, a GaAs growth substrate, a cutoff layer, an N-DBR layer, an MQW multiple quantum well layer, a high-aluminum AlGaAs layer, a P-DBR layer and a contact layer. S2. Mesa etching: Through photolithography, dry etching, and resist removal processes, the contact layer, P-DBR layer, high-aluminum AlGaAs layer, MQW multiple quantum well layer and part of the N-DBR layer in some areas are etched away to form a stepped structure that exposes the N-DBR layer. S3. Dielectric layer deposition and patterning: An insulating dielectric layer is deposited on the upper surface of the contact layer and the upper surface of the N-DBR layer exposed by the step structure. The insulating dielectric layer on the side of the high-aluminum AlGaAs layer is removed by photolithography, etching and resist removal processes to expose the side of the high-aluminum AlGaAs layer. S4. Oxidation confinement layer preparation: The wafer is placed in a wet oxidation furnace, and the exposed high-alumina AlGaAs layer side is wet oxidized to form a high-alumina AlGaAs oxide layer on the side of the high-alumina AlGaAs layer, while forming a conductive window. S5. Cut-through etching: Through photolithography, etching, and resist removal processes, the insulating dielectric layer, N-DBR layer, and cut-off layer in the cut-through area are etched away to expose the GaAs growth substrate. S6, N contact metal fabrication: Interconnect windows are fabricated at the positions of the insulating dielectric layer corresponding to the N-DBR layer through photolithography, etching, evaporation, and lift-off processes. N contact metal is then deposited in the interconnect windows and alloyed to form an ohmic contact between the N contact metal and the N-DBR layer. S7, P contact metal preparation: Through photolithography, etching, evaporation and stripping processes, interconnect windows are made at the positions of the contact layers corresponding to the insulating dielectric layer. P contact metal is evaporated in the interconnect windows and alloyed to form an ohmic contact between the P contact metal and the contact layer. S8. Deposition and patterning of insulating compound layer: An insulating compound layer is deposited on the upper surface of the insulating dielectric layer, P contact metal, and N contact metal. The insulating compound on the upper surface of the P contact metal and N contact metal is removed by photolithography, etching, and resist removal processes to form electrode windows. S9, P / N electrode fabrication: P / N electrodes are fabricated on the upper surface of the insulating compound layer through photolithography, evaporation, and lift-off processes. The P electrode and N electrode are electrically connected to the P contact metal and N contact metal respectively through the electrode window to complete the fabrication of the wafer front-side device. S10, Temporary Bonding: Through a hot-press bonding process, the wafer with the completed front-side device fabrication is bonded to a temporary substrate using bonding material, so that the electrode surface of the wafer is attached to the temporary substrate. S11, Substrate Removal: The GaAs growth substrate is removed by a wet etching process to expose the lower surface of the cutoff layer; S12, Lens fabrication: A transparent lens is fabricated on the exposed lower surface of the stop layer using nanoimprinting or dry etching processes; S13. Debonding and Chip Transfer: The temporary substrate is removed by laser debonding process, and the prepared chip is transferred to the carrier film to complete the manufacturing of the ultrathin Micro VCSEL chip.

[0015] In a preferred embodiment, in step S4, the process parameters for wet oxidation are: oxidation temperature 400℃~450℃, water bath temperature 90℃~95℃, N2 carrier gas flow rate 1L / min~1.5L / min, and oxidation time 20min~30min.

[0016] Alternatively, in step S4, a high-alumina AlGaAs oxide layer is prepared using a plasma oxidation process with the following parameters: O2 to N2O flow rate ratio of 1.2 to 1.5:1, total gas flow rate of 20 sccm to 100 sccm, reaction chamber pressure of 5 Pa to 20 Pa, ICP power of 200 W to 500 W, RF power of 100 W to 200 W, substrate temperature of 300 °C to 400 °C, and oxidation time of 10 min to 30 min.

[0017] Due to the application of the above technical solution, the beneficial effects of this application compared with the prior art are as follows: 1. Significantly improved coupling efficiency: Completely removing the GaAs growth substrate fundamentally eliminates the transmission, scattering, and refraction losses of light in the thick substrate, significantly improving the collimation of the emitted beam and greatly reducing the divergence angle; at the same time, the transparent lens is directly fabricated on the surface of the cutoff layer adjacent to the light-emitting surface, greatly shortening the optical path and further enhancing the beam focusing effect. Compared with the existing substrate surface lens scheme, the optical coupling efficiency can be improved by more than 30%.

[0018] 2. Ultra-thin chip and high integration: The substrate-free design allows the total chip thickness to be controlled within 20μm, realizing the ultra-thin design of Micro VCSEL, which is perfectly suited for integrated application scenarios with strict requirements for device size, such as consumer electronics and micro optical modules.

[0019] 3. High yield and high reliability: By precisely controlling the wet etching endpoint through the cutoff layer, damage to the epitaxial functional layer is avoided during the etching process, and the wafer fabrication yield can be improved to over 95%; The flip-chip structure combined with the substrate-free design makes the active area closer to the package heat dissipation path, reducing the device thermal resistance by more than 40%, which greatly improves the heat dissipation performance and long-term reliability under high power operation.

[0020] 4. Easy to scale up mass production: The manufacturing process of this invention is fully compatible with existing III-V semiconductor wafer manufacturing lines, requiring no additional special equipment. It has a wide process window, making it easy to achieve large-scale mass production and possessing extremely high industrial application value. Attached Figure Description

[0021] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0022] Figure 1 This is a cross-sectional schematic diagram of the ultrathin Micro VCSEL chip structure described in Embodiment 1 of the present invention; Figure 2 This is a cross-sectional schematic diagram of an ultrathin MicroVCSEL chip structure without an insulating dielectric layer according to another embodiment of the present invention; Figure 3 This is a schematic cross-sectional view of the process flow of the ultrathin MicroVCSEL chip manufacturing method described in Embodiment 2 of the present invention. Figure 4 This is a cross-sectional schematic diagram of the extensional structure in step S1; Figure 5 This is a schematic diagram of the cross-section after the mesa is etched in step S2; Figure 6 This is a schematic diagram of the cross-section after the deposition and patterning of the dielectric layer in step S3; Figure 7 This is a schematic cross-sectional view of the oxide confinement layer after preparation in step S4; Figure 8 This is a schematic diagram of the cross-section after etching the cutting path in step S5; Figure 9 This is a schematic cross-sectional view of the N-contact metal after preparation in step S6; Figure 10 This is a schematic cross-sectional view of the P-contact metal after preparation in step S7. Figure 11 This is a schematic cross-sectional view of the insulating compound layer after deposition and patterning in step S8; Figure 12 This is a schematic cross-sectional view of the surface electrode after fabrication in step S9; Figure 13 This is a schematic cross-sectional view of the temporary bonding after step S10; Figure 14 This is a schematic cross-sectional view after substrate removal in step S11; Figure 15 This is a schematic cross-sectional view of the lens after preparation in step S12; Figure 16 This is a schematic diagram of the chip cross-section after debonding in step S13; Among them, 1. Growth substrate; 2. Cut-off layer; 3. N-DBR layer; 4. MQW multiple quantum well; 5. High-aluminum AlGaAs; 6. P-DBR layer; 7. Contact layer; 8. Dielectric layer; 9. High-aluminum AlGaAs oxide layer; 10. N contact metal; 11. P contact metal; 12. Insulating compound; 13. P / N electrode; 14. Bonding material; 15. Temporary substrate; 16. Transparent lens. Detailed Implementation

[0023] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0024] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0025] In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing the invention and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0026] Furthermore, in addition to indicating direction or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in certain situations to indicate a dependency or connection. Those skilled in the art can understand the specific meaning of these terms in this invention based on the specific circumstances.

[0027] Furthermore, the terms "installation," "setup," "equipped with," "connection," "linking," and "socketing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this invention based on the specific circumstances.

[0028] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The present invention will be further described in detail below with reference to detailed embodiments and comparative examples. Those skilled in the art will understand that the following embodiments are for illustrative purposes only and should not be considered as limiting the scope of protection of the present invention. Where specific techniques or conditions are not specified in the embodiments, they are performed according to conventional semiconductor process techniques or conditions described in the literature in the art. Materials, reagents, and equipment used, where the manufacturer is not specified, are all conventional products that can be purchased through legitimate channels.

[0029] Example 1 This embodiment provides an ultrathin MicroVCSEL chip structure, the cross-sectional structure of which is as follows: Figure 1 As shown, the specific structure and parameters are as follows: The chip structure in this embodiment has no GaAs growth substrate 1, and from bottom to top, it is sequentially arranged with a transparent lens 16, a cutoff layer 2, an N-DBR layer 3, an MQW multi-quantum well layer 4, a high-aluminum AlGaAs layer 5, a P-DBR layer 6, and a contact layer 7.

[0030] Among them, the cutoff layer 2 is made of GaInP material with a thickness of 180nm. It has a high selectivity for GaAs etching solution and serves as the cutoff layer 2 for wet etching, protecting the upper epitaxial functional layer from corrosion damage. The cutoff layer 2 includes a second surface (lower surface) facing the light-emitting side and a first surface (upper surface) facing the N-DBR layer. The transparent lens 16 is directly fabricated on the second surface of the cutoff layer 2.

[0031] The transparent lens 16 is made of PMMA organic transparent material with a thickness of 15μm. It is formed into a spherical structure with a radius of curvature of 25μm through nanoimprinting process and is used to focus the emitted light beam.

[0032] N-DBR layer 3 is Al 0.12 Ga 0.88 The Bragg reflector structure consists of alternating As / AlAs layers with 23.5 periods. The optical thickness of each layer is 1 / 4 of the 940nm center reflection wavelength. The P-DBR layer 6 is made of Al. 0.12 Ga 0.88The As / AlAs alternating stacked structure has 40 pairs of periods, and the optical thickness is also 1 / 4 of the center wavelength. The reflectivity of the P-DBR layer 6 is higher than that of the N-DBR layer 3, which allows the light emitted from the MQW multi-quantum well layer 4 to exit from the N-DBR layer 3 side.

[0033] The MQW multi-quantum-well layer 4 is an InGaAs / GaAs strained quantum well structure with a total of 3 quantum well periods, serving as the active light-emitting region of the device.

[0034] High-aluminum AlGaAs layer 5 is Al 0.98 Ga 0.02 The material is As, with a thickness of 30nm, located between the MQW multi-quantum well layer 4 and the P-DBR layer 6; its side is formed by wet oxidation to form a high-alumina AlGaAs oxide layer 9, and a circular conductive window with a diameter of 12μm is formed on the high-alumina AlGaAs oxide layer 9. The conductive window is symmetrically arranged with the transparent lens 16 along the central axis to ensure that the light beam is perpendicularly incident to the center of the lens.

[0035] Contact layer 7 is a heavily doped p-type GaAs layer with a doping concentration ≥ 5 × 10⁻⁶. 19 cm -3 It has a thickness of 120 nm and is used to form a good ohmic contact with P-contact metal.

[0036] The chip structure features a stepped structure etched downwards from the upper surface of the contact layer 7 to the N-DBR layer 3, with a step depth of 3.2 μm. An N-contact metal 10 is disposed on the exposed upper surface of the N-DBR layer 3; a P-contact metal 11 is disposed on the upper surface of the contact layer 7. The N-contact metal 10 is an AuGe / Ni / Au stacked structure with a total thickness of 350 nm; the P-contact metal 11 is a Ti / Pt / Au stacked structure with a total thickness of 300 nm.

[0037] The upper surface of the N-DBR layer 3 and the upper surface of the contact layer 7 are covered with an insulating dielectric layer 8. The insulating dielectric layer 8 is made of SiO2 material with a thickness of 130nm and is used for device sidewall passivation and interlayer insulation. Interconnect windows are opened in the insulating dielectric layer 8 at the positions corresponding to the P contact metal 11 and N contact metal 10. The P contact metal 11 and N contact metal 10 achieve ohmic contact with the contact layer 7 and N-DBR layer 3 respectively through the interconnect windows.

[0038] An insulating compound layer 12 is covered on the upper surface of the insulating dielectric layer 8, the upper surface of the P contact metal 11, and the upper surface of the N contact metal 10. The insulating compound layer 12 is made of Si3N4 material with a thickness of 2.8μm and is used for surface passivation and planarization of the device. Electrode windows are provided in the insulating compound layer 12 at the positions corresponding to the P contact metal 11 and the N contact metal 10. The electrode windows are tapered through holes that extend from the upper surface to the lower surface. The diameter of the holes gradually increases from the bottom surface to the top surface, and the cone angle is 60° to improve the step coverage of the electrodes.

[0039] The upper surface of the insulating compound layer 12 is provided with P electrodes and N electrodes (collectively referred to as P / N electrodes 13). The P / N electrodes 13 are Ti / Pt / Au / Cr stacked structures with a total thickness of 1.8μm. The top layer is made of Cr material, which is used to improve the welding reliability with the packaging substrate. The P electrodes and N electrodes are connected to the P contact metal 11 and N contact metal 10 through electrode windows to achieve low resistance electrical connection.

[0040] Another optional embodiment of this invention can remove the insulating dielectric layer 8, with the structure as follows: Figure 2 As shown, the insulating compound layer 12 directly covers the surfaces of the N-DBR layer 3, contact layer 7, P contact metal 11, and N contact metal 10, further simplifying the process steps and making it suitable for application scenarios with stringent requirements on process costs.

[0041] Example 2 This embodiment provides a method for manufacturing an ultrathin MicroVCSEL chip, the process flow of which is as follows: Figure 3 As shown, the specific steps and process parameters are as follows: S1. Epitaxial wafer preparation: Provides a 6-inch VCSEL epitaxial structure, such as Figure 4 As shown, the epitaxial structure, from bottom to top, includes: a GaAs growth substrate with a thickness of 350 μm 1, a GaInP cutoff layer with a thickness of 180 nm 2, an N-DBR layer with 23.5 periods 3, a MQW multiple quantum well layer with 3 periods of InGaAs / GaAs 4, a high-aluminum AlGaAs layer with a thickness of 30 nm 5, a P-DBR layer with 40 periods 6, and a heavily doped p-type GaAs contact layer with a thickness of 120 nm 7.

[0042] S2, Mesh etching: Through photolithography, ICP dry etching, and resist stripping processes, partial areas of the contact layer 7, P-DBR layer 6, high-aluminum AlGaAs layer 5, MQW multiple quantum well layer 4, and part of the N-DBR layer 3 were etched away to a depth of 3.2 μm, forming a stepped structure that exposes the N-DBR layer 3. Figure 5 As shown.

[0043] S3, Dielectric Layer Deposition and Patterning: A 130nm thick SiO2 insulating dielectric layer 8 was deposited on the upper surface of the contact layer 7 and the upper surface of the N-DBR layer 3 exposed by the stepped structure using PECVD. The insulating dielectric layer on the sides of the high-aluminum AlGaAs layer 5 was removed by photolithography, BOE wet etching, and resist removal processes, fully exposing the sides of the high-aluminum AlGaAs layer 5. Figure 6 As shown.

[0044] S4. Preparation of the oxide confinement layer: The wafer was placed in a wet oxidation furnace, and the exposed high-alumina AlGaAs layer 5 was subjected to wet oxidation. The process parameters were: oxidation temperature 420℃, water bath temperature 92℃, N2 carrier gas flow rate 1.2L / min, and oxidation time 25min. A high-alumina AlGaAs oxide layer 9 was formed on the side of the high-alumina AlGaAs layer 5, and a circular conductive window with a diameter of 12μm was formed in the high-alumina AlGaAs oxide layer 9. Figure 7 As shown.

[0045] S5, Cutting surface etching: Through photolithography, ICP dry etching, and resist stripping processes, the insulating dielectric layer 8, N-DBR layer 3, and stop layer 2 in the dicing area are etched away, extending to the GaAs growth substrate 1 and exposing its surface to provide an etching path for subsequent wet etching. Figure 8 As shown.

[0046] Preparation of S6 and N contact metals: Interconnect windows were fabricated on the insulating dielectric layer 8 at the position corresponding to the N-DBR layer 3 using photolithography and BOE wet etching processes. AuGe / Ni / Au multilayer metal was deposited using electron beam evaporation, and excess metal was removed by a lift-off process to form the N-contact metal 10. Rapid thermal annealing at 380℃ for 30 seconds under an N2 atmosphere ensured good ohmic contact between the N-contact metal 10 and the N-DBR layer 3. Figure 9 As shown.

[0047] Preparation of S7 and P contact metals: Interconnect windows are fabricated on the insulating dielectric layer 8 at the positions corresponding to the contact layer 7 using photolithography and BOE wet etching processes. A Ti / Pt / Au multilayer metal is deposited using electron beam evaporation, followed by removal of excess metal to form the P-contact metal 11. Rapid thermal annealing at 360°C for 30 seconds in an N2 atmosphere ensures good ohmic contact between the P-contact metal 11 and the contact layer 7. Figure 10 As shown.

[0048] S8. Deposition and patterning of insulating compound layers: A 2.8 μm thick Si3N4 insulating compound layer 12 is deposited on the upper surfaces of the insulating dielectric layer 8, P-contact metal 11, and N-contact metal 10 using PECVD. The insulating compound on the upper surfaces of the P-contact metal 11 and N-contact metal 10 is then removed using photolithography, ICP dry etching, and resist stripping processes, forming a tapered electrode window that is wider at the top and narrower at the bottom. Figure 11 As shown.

[0049] S9. Fabrication of surface electrodes: A Ti / Pt / Au / Cr multilayer metal is deposited on the upper surface of the insulating compound layer 12 using photolithography and electron beam evaporation processes. A P / N electrode 13 is then formed through a lift-off process. The P / N electrode 13 is then connected to the P contact metal 11 and N contact metal 10 through electrode windows, respectively, achieving low-resistance electrical connections and completing the fabrication of the front-side device on the wafer. Figure 12 As shown.

[0050] S10, Temporary Bonding: Using a thermo-press bonding process, the wafer with the front-side device fabricated is bonded to a glass temporary substrate 15 using bonding material 14, which is a pyrolytic tape. The bonding temperature is 180°C and the pressure is 0.2 MPa, ensuring complete adhesion between the electrode surface of the wafer and the temporary substrate 15. Figure 13 As shown.

[0051] S11, Substrate removal: Using an etchant solution with a ratio of NH4OH:H2O2:H2O = 1:2:20, a wet etching process was employed to remove the GaAs growth substrate 1. During the etching process, the cutoff layer 2 exhibited high selectivity for the etchant solution, and etching automatically stopped upon reaching the cutoff layer 2, completely exposing the lower surface of the cutoff layer 2. Figure 14 As shown.

[0052] S12, Lens fabrication: PMMA photoresist was spin-coated onto the exposed lower surface of the stop layer 2 using a nanoimprinting process. A spherical transparent lens 16 with a thickness of 15 μm was then formed through imprinting with a spherical lens mold, UV curing, and demolding. The alignment deviation between the lens and the central axis of the conductive window was ≤1 μm. Figure 15 As shown.

[0053] S13. Debonding and chip transfer: A temporary substrate 15 was irradiated with a 308nm ultraviolet laser to decompose the pyrolytic tape and cause it to lose its adhesiveness. The temporary substrate 15 was then removed using a laser dissociation process. The fabricated ultrathin chip was then transferred onto a blue film carrier film, completing the fabrication of the ultrathin MicroVCSEL chip. Figure 16 As shown.

[0054] In another optional embodiment, step S4 can be prepared using plasma oxidation process to prepare a high-alumina AlGaAs oxide layer 9. The process parameters are: O2 to N2O flow rate ratio of 1.3:1, total gas flow rate of 60 sccm, reaction chamber pressure of 12 Pa, ICP power of 350 W, RF power of 150 W, substrate temperature of 350 °C, and oxidation time of 20 min. This can achieve more uniform oxide layer thickness control and is suitable for the batch preparation of large-size wafers.

[0055] Comparison and performance verification To verify the technical effect of the present invention, a comparative example was set up. The comparative example adopted the existing technical solution: a 350μm thick GaAs growth substrate 1 was retained, and a microlens was prepared on the light-emitting surface of the substrate. The rest of the epitaxial structure, device size, and oxidation window parameters were completely consistent with those of Example 1.

[0056] The devices of Example 1 and Comparative Example 1 were subjected to performance tests, and the test results are shown in the table below: Far-field divergence angle (full angle) 12° 18° Reduced by 33.3% Fiber coupling efficiency 78% 59% An increase of 32.2% Total chip thickness 18μm 355μm Reduced by 94.9% Device thermal resistance 32℃ / W 55℃ / W Reduced by 41.8% Wavelength drift at 10mW operation 0.8nm 1.5nm Reduced by 46.7%

[0057] Test results show that, compared with the prior art, the present invention significantly reduces the beam divergence angle and device thermal resistance, greatly improves optical coupling efficiency, and achieves ultra-thin chip design.

[0058] Finally, it should be noted that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An ultrathin Micro VCSEL chip structure, characterized in that, It includes, from bottom to top, a transparent lens, a cutoff layer, an N-DBR layer, an MQW multi-quantum well layer, a high-aluminum AlGaAs layer, a P-DBR layer, and a contact layer; The sides of the high-aluminum AlGaAs layer are oxidized to form a high-aluminum AlGaAs oxide layer, and a conductive window is formed on the high-aluminum AlGaAs oxide layer. The upper surface of the contact layer is provided with a P-contact metal; The chip structure is provided with a stepped structure that is etched downward from the upper surface of the contact layer to the N-DBR layer, and the upper surface of the N-DBR layer exposed by the stepped structure is provided with N contact metal; The upper surface of the N-DBR layer and the upper surface of the contact layer are covered with an insulating dielectric layer. The insulating dielectric layer has interconnect windows at the positions corresponding to the P contact metal and N contact metal. The P contact metal and N contact metal make ohmic contact with the contact layer and N-DBR layer respectively through the interconnect windows. The upper surfaces of the insulating dielectric layer, the upper surfaces of the P contact metal, and the upper surfaces of the N contact metal are covered with an insulating compound layer. Electrode windows are opened in the insulating compound layer at the positions corresponding to the P contact metal and the N contact metal. P / N electrodes are disposed on the upper surface of the insulating compound layer. The P / N electrodes are electrically connected to the P contact metal and the N contact metal respectively through the electrode windows. The cutoff layer is a wet-etched cutoff layer, the chip structure has no GaAs growth substrate, and the transparent lens is directly fabricated on the lower surface of the cutoff layer.

2. The ultra-thin Micro VCSEL chip structure according to claim 1, characterized in that, The material of the stop layer is any one of GaInP, GaAs, or AlGaAs, and the thickness of the stop layer is 20nm~500nm.

3. The ultra-thin Micro VCSEL chip structure according to claim 1, characterized in that, The transparent lens is made of any one of the organic transparent materials selected from PI, PMMA, PMGI, or SU-8. The thickness of the transparent lens is 2μm to 50μm. The transparent lens is a spherical lens prepared by nanoimprinting or dry etching processes.

4. The ultra-thin Micro VCSEL chip structure according to claim 1, characterized in that, Both the N-DBR layer and the P-DBR layer are periodic Bragg reflection structures formed by alternating stacks of semiconductor materials with an optical thickness of 1 / 4 of the central reflection wavelength. The periodic logarithm of the P-DBR layer is greater than that of the N-DBR layer, and the reflectivity of the P-DBR layer is higher than that of the N-DBR layer, so that the light emission direction of the chip is to the N-DBR layer side.

5. The ultrathin Micro VCSEL chip structure according to claim 1, characterized in that, The high-alumina AlGaAs oxide layer is prepared by wet oxidation or plasma oxidation process. The conductive window is circular and is symmetrical about the central axis with the transparent lens.

6. The ultra-thin Micro VCSEL chip structure according to claim 1, characterized in that, The contact layer is a heavily doped GaAs layer with a thickness of 30nm~300nm; the N contact metal is an AuGe / Ni / Au stacked structure, and the P contact metal is a Ti / Pt / Au stacked structure.

7. The ultra-thin Micro VCSEL chip structure according to claim 1, characterized in that, The insulating dielectric layer is made of any one of SiO2, Si3N4, or Al2O3, with a thickness of 50nm to 300nm; the insulating compound layer is made of any one of SiO2, Si3N4, TiO2, or MgF2, an inorganic insulating material, with a thickness of 1μm to 5μm; the electrode window is a through-hole extending from the upper surface to the lower surface of the insulating compound layer, and the aperture of the electrode window gradually increases from the bottom surface to the top surface.

8. The ultra-thin Micro VCSEL chip structure according to claim 1, characterized in that, The P / N electrode is a stacked structure formed by any one or more metals selected from Cr, Ni, Pt, Ti, Au, and Al. The top layer material of the P / N electrode is any one of Ti, Cr, and Ni or their alloys, with a thickness of 0.8 μm to 2.3 μm.

9. A method for manufacturing an ultrathin Micro VCSEL chip, characterized in that, Includes the following steps: S1. Epitaxial wafer fabrication: A VCSEL epitaxial structure is provided, wherein the epitaxial structure comprises, from bottom to top, a GaAs growth substrate, a cutoff layer, an N-DBR layer, an MQW multiple quantum well layer, a high-aluminum AlGaAs layer, a P-DBR layer and a contact layer. S2. Mesa etching: Through photolithography, dry etching, and resist removal processes, the contact layer, P-DBR layer, high-aluminum AlGaAs layer, MQW multiple quantum well layer and part of the N-DBR layer in some areas are etched away to form a stepped structure that exposes the N-DBR layer. S3. Dielectric layer deposition and patterning: An insulating dielectric layer is deposited on the upper surface of the contact layer and the upper surface of the N-DBR layer exposed by the step structure. The insulating dielectric layer on the side of the high-aluminum AlGaAs layer is removed by photolithography, etching and resist removal processes to expose the side of the high-aluminum AlGaAs layer. S4. Oxidation confinement layer preparation: The wafer is placed in a wet oxidation furnace, and the exposed high-alumina AlGaAs layer side is wet oxidized to form a high-alumina AlGaAs oxide layer on the side of the high-alumina AlGaAs layer, while forming a conductive window. S5. Cut-through etching: Through photolithography, etching, and resist removal processes, the insulating dielectric layer, N-DBR layer, and cut-off layer in the cut-through area are etched away to expose the GaAs growth substrate. S6, N contact metal fabrication: Interconnect windows are fabricated at the positions of the insulating dielectric layer corresponding to the N-DBR layer through photolithography, etching, evaporation, and lift-off processes. N contact metal is then deposited in the interconnect windows and alloyed to form an ohmic contact between the N contact metal and the N-DBR layer. S7, P contact metal preparation: Through photolithography, etching, evaporation and stripping processes, interconnect windows are made at the positions of the contact layers corresponding to the insulating dielectric layer. P contact metal is evaporated in the interconnect windows and alloyed to form an ohmic contact between the P contact metal and the contact layer. S8. Deposition and patterning of insulating compound layer: An insulating compound layer is deposited on the upper surface of the insulating dielectric layer, P contact metal, and N contact metal. The insulating compound on the upper surface of the P contact metal and N contact metal is removed by photolithography, etching, and resist removal processes to form electrode windows. S9, P / N electrode fabrication: P / N electrodes are fabricated on the upper surface of the insulating compound layer through photolithography, evaporation, and lift-off processes. The P electrode and N electrode are electrically connected to the P contact metal and N contact metal respectively through the electrode window to complete the fabrication of the wafer front-side device. S10, Temporary Bonding: Through a hot-press bonding process, the wafer with the completed front-side device fabrication is bonded to a temporary substrate using bonding material, so that the electrode surface of the wafer is attached to the temporary substrate. S11, Substrate Removal: The GaAs growth substrate is removed by a wet etching process to expose the lower surface of the cutoff layer; S12, Lens fabrication: A transparent lens is fabricated on the exposed lower surface of the stop layer using nanoimprinting or dry etching processes; S13. Debonding and Chip Transfer: The temporary substrate is removed by laser debonding process, and the prepared chip is transferred to the carrier film to complete the manufacturing of the ultrathin Micro VCSEL chip.

10. The method for manufacturing an ultrathin Micro VCSEL chip according to claim 9, characterized in that, In step S4, the process parameters for wet oxidation are: oxidation temperature 400℃~450℃, water bath temperature 90℃~95℃, N2 carrier gas flow rate 1L / min~1.5L / min, and oxidation time 20min~30min. Alternatively, in step S4, a high-alumina AlGaAs oxide layer is prepared using a plasma oxidation process with the following parameters: O2 to N2O flow rate ratio of 1.2 to 1.5:1, total gas flow rate of 20 sccm to 100 sccm, reaction chamber pressure of 5 Pa to 20 Pa, ICP power of 200 W to 500 W, RF power of 100 W to 200 W, substrate temperature of 300 °C to 400 °C, and oxidation time of 10 min to 30 min.

Images