Display panel and electronic device
By setting up same-layer blocking electrodes on the demultiplexing circuit, the performance degradation and display inhomogeneity of OLED display products caused by illumination are solved, achieving higher display consistency and reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- KUNSHAN GO VISIONOX OPTO ELECTRONICS CO LTD
- Filing Date
- 2026-04-08
- Publication Date
- 2026-07-28
AI Technical Summary
Existing OLED display products are susceptible to light exposure at the demultiplexing circuit, leading to performance degradation and display inhomogeneity, especially when touch signal traces are present.
A first blocking electrode is set on the demultiplexing circuit at the same layer as the first pixel electrode. The demultiplexing circuit is blocked by the blocking electrode to reduce the influence of light. The reflectivity difference is reduced by designing the blocking electrodes with a stepped distribution and spacing.
It effectively reduces the impact of illumination on the multiplexing circuit, improves the reflectivity consistency of different areas of the display panel, reduces the appearance of bright lines or large bright areas, and enhances display uniformity.
Smart Images
Figure CN122476789A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and more specifically, to a display panel and an electronic device. Background Technology
[0002] Organic light-emitting diodes (OLEDs) and flat panel displays based on light-emitting diodes (LEDs) are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body and wide range of applications, becoming the mainstream of display devices.
[0003] However, the performance of current OLED display products needs to be improved. Summary of the Invention
[0004] To overcome the aforementioned shortcomings in the prior art, the present application aims to provide a display panel, the display panel including a display area and a non-display area located on at least one side of the display area; the display panel includes:
[0005] substrate; An array functional layer located on one side of the substrate, the array functional layer including multiple demultiplexing circuits located in the non-display area; The light-emitting device layer is located on the side of the array functional layer away from the substrate. The light-emitting device layer includes a plurality of first pixel electrodes located in the display area and a plurality of first blocking electrodes located in the non-display area. The first pixel electrodes and the first blocking electrodes are disposed in the same layer. The orthogonal projection of the demultiplexing electrode on the substrate at least partially overlaps with the orthogonal projection of the corresponding first blocking electrode on the substrate.
[0006] In some possible implementations, the demultiplexing circuit includes a demultiplexing transistor whose orthographic projection on the substrate is located within the orthographic projection of the corresponding first shielding electrode on the substrate; Preferably, the first shielding electrode corresponds one-to-one with the demultiplexing circuit.
[0007] In some possible implementations, the array functional layer further includes a plurality of gate driving circuits located in the non-display area, at least a portion of which are located on the side of the demultiplexing circuit away from the display area; The light-emitting device layer further includes a second shielding electrode, which is disposed on the same layer as the first pixel electrode, and the orthographic projection of the gate driving circuit on the substrate is located within the orthographic projection of the second shielding electrode on the substrate; The second shielding electrode is spaced apart from the first shielding electrode; Preferably, the orthographic projections of the plurality of gate driving circuits on the substrate are located within the orthographic projection of the same second shielding electrode on the substrate.
[0008] In some possible implementations, the light-emitting device layer further includes a plurality of dummy electrodes, which are disposed on the same layer as the first pixel electrode; At least a portion of the dummy electrode is located between the first blocking electrode and the first pixel electrode; Preferably, the shape of the orthographic projection of the dummy electrode on the substrate is the same as the shape of the orthographic projection of the corresponding first pixel electrode on the substrate; Preferably, the orthographic projections of the plurality of dummy electrodes on the substrate surround the display area.
[0009] In some possible implementations, the array functional layer further includes a first power trace located in the non-display area and at least partially surrounding the display area, and at least partially the first shielding electrode and / or the dummy electrode are connected to the first power trace; The first power supply trace includes a drive voltage trace, a common voltage trace, or an initialization voltage trace; Preferably, the first shielding electrode and / or the dummy electrode includes a first part electrode and a second part electrode; The orthographic projection of the first portion of the electrode on the substrate at least partially coincides with the orthographic projection of the first power line on the substrate, and the orthographic projection of the second portion of the electrode on the substrate at least partially offsets from the orthographic projection of the first power line on the substrate; At least a portion of the first portion of electrodes is electrically connected to the first power supply trace through a through-hole; at least a portion of the second portion of electrodes is electrically connected to the first portion of electrodes through an electrode connection wire. Preferably, the electrode line is disposed in the same layer as the first pixel electrode.
[0010] In some possible implementations, the display panel further includes a touch function layer located on the side of the light-emitting device layer away from the substrate, the touch function layer including touch signal traces located in the non-display area; at least a portion of the first blocking electrode and / or at least a portion of the dummy electrode's orthographic projection on the substrate at least partially coincide with the orthographic projection of the touch signal traces on the substrate; Preferably, the edge of the display area has a rounded corner, and the orthographic projection of the touch signal trace near the rounded corner on the substrate extends along the contour of the rounded corner.
[0011] In some possible implementations, the display panel further includes an ink layer located in the non-display area, the orthographic projection of the ink layer on the substrate at least partially surrounding the display area; the orthographic projection of the first shielding electrode on the substrate is located between the display area and the orthographic projection of the ink layer on the substrate.
[0012] In some possible implementations, the edge of the display area has an arc angle, and a plurality of first pixel electrodes are distributed in a stepped manner along the arc angle; a plurality of first occlusion electrodes are distributed in a stepped manner along the arc angle.
[0013] In some possible implementations, the light-emitting device layer further includes a plurality of light-emitting functional layers and a second pixel electrode, wherein the light-emitting functional layer is located on the side of the corresponding first pixel electrode away from the substrate, and the second pixel electrode is located on the side of the light-emitting functional layer away from the substrate.
[0014] Another object of this application is to provide an electronic device, which includes the display panel provided in this application.
[0015] Compared with the prior art, this application has the following beneficial effects: This application provides a display panel and an electronic device. For each demultiplexing circuit, by setting a first blocking electrode on the same layer as the first pixel electrode above the demultiplexing circuit to block the demultiplexing circuit, the reflection difference between the first blocking electrode and the first pixel electrode can be reduced while reducing the influence of light on the demultiplexing circuit, thereby improving the reflection consistency of different areas of the display panel. Attached Figure Description
[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 A schematic diagram of the wiring in the curved corner area of an existing display panel; Figure 2 This is a schematic diagram of the display panel provided in this embodiment; Figure 3 This is one of the cross-sectional schematic diagrams of the display panel provided in this embodiment; Figure 4 This is an equivalent circuit diagram of the pixel driving circuit provided in this embodiment; Figure 5 This is a second cross-sectional schematic diagram of the display panel provided in this embodiment; Figure 6 This is one of the circuit diagrams of the curved corner area of the display panel provided in this embodiment; Figure 7 This is the third cross-sectional schematic diagram of the display panel provided in this embodiment; Figure 8 This is the second schematic diagram of the circuit of the arc corner area of the display panel provided in this embodiment; Figure 9 This is the third schematic diagram of the circuit of the arc corner area of the display panel provided in this embodiment.
[0018] Reference numerals: 100-substrate; 110-array functional layer; 310-pixel driving circuit; 320-demultiplexing circuit; 330-gate driving circuit; 810-light-emitting device; 120-first pixel electrode; 130-pixel defining layer; 150-light-emitting functional layer; 160-second pixel electrode; 210-first blocking electrode; 220-second blocking electrode; 230-dummy electrode; 240-electrode connection line; 410-demultiplexing signal trace; 420-first power supply trace; 510-touch signal trace; AA-display area; NA-non-display area; NA1-border area; NA2-bonding area. Detailed Implementation
[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0020] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0021] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. It should be noted that, unless otherwise specified, different features in the embodiments of this application can be combined with each other.
[0022] For certain elements, terms like "above" or "overhead" are sometimes used when describing the position of an element in the Z direction, and "below" or "under" are used when describing the position of an element in the opposite direction. Furthermore, when using terms like "above," "overhead," "below," "under," or "relative" to define the positional relationship between two elements, this includes not only the state where the two elements are directly adjacent, but also the state where the two elements are separated by gaps or other elements. Additionally, terms like "first," "second," and "third" are used only for distinguishing descriptions and should not be interpreted as indicating or implying relative importance.
[0023] Please see Figure 1 In some related display panels, the four corners of the rectangular display area AA are set as rounded corners. The light-emitting devices 810 and their corresponding pixel driving circuits 310 located in the display area AA are distributed in a stepped manner along the contour of the rounded corners. The non-display area NA at the bottom bezel of the display panel typically also contains multiple demultiplexing circuits 320 arranged along the bottom bezel. To reduce the bezel width of the non-display area NA corresponding to the rounded corner area, the demultiplexing circuits 320 and their traces in the rounded corner area of the bottom bezel are distributed in a stepped manner similar to that of the pixel driving circuits 310 along the contour of the rounded corner.
[0024] The inventors discovered that in the aforementioned display panel, due to the close proximity of the demultiplexing circuit 320 to the display area AA, it is impossible to precisely set the ink layer to block the demultiplexing circuit 320. This results in light emitted by the light-emitting device 810 in the display area AA being reflected onto the demultiplexing circuit 320, or external light shining onto the demultiplexing circuit 320. Consequently, the devices (e.g., thin-film transistors) in the demultiplexing circuit 320 are affected by the light, leading to performance degradation. Particularly when touch signal traces 510 are present above some demultiplexing circuits 320, the degree of blocking by these traces varies, causing different demultiplexing circuits 320 to be affected by light degradation to varying degrees, thus impacting the display uniformity of the display panel.
[0025] In view of this, this embodiment provides a solution that can reduce the impact of light on the demultiplexing circuit 320. The solution provided in this embodiment will be described in detail below.
[0026] Please see Figure 2 , Figure 2This is a schematic diagram of a display panel provided in this embodiment. The display panel can be an organic light-emitting diode (OLED) display panel or a quantum dot light-emitting diode (QLED) display panel. The display panel includes a display area AA with display function and a non-display area NA.
[0027] The display area AA of the display panel can be rectangular, square, or other shapes; no specific limitation is made in this embodiment. The display panel provided in this embodiment includes at least one arc-corner area, in which the outer contour of the display area AA and the corresponding non-display area NA are both arc-shaped (e.g., ...). Figure 2 (As shown in the circular dashed box).
[0028] The display area AA includes multiple pixels arranged in the first direction D1 and the second direction D2. Each pixel includes multiple sub-pixels that display different colors. Each sub-pixel includes a pixel driving circuit 310 and a light-emitting device 810 driven by the pixel driving circuit 310 to emit light of the corresponding color.
[0029] Please see Figure 3 , Figure 3 It shows Figure 2 This is a schematic diagram of a partial film layer cross-section of a display panel, which may include a substrate 100, an array functional layer 110, and a light-emitting device layer.
[0030] In this embodiment, the material of the substrate 100 may include a rigid material, such as glass; or the material of the substrate 100 may include a flexible material, such as polyimide (Pi).
[0031] Optionally, an array functional layer 110 may also be disposed on one side of the substrate 100. The array functional layer 110 may include multiple film layer structures, such as a buffer layer, an active layer, multiple conductive layers, and multiple insulating layers. Please refer to [link to relevant documentation]. Figure 3 The array functional layer 110 can form multiple transistors at different locations using multiple film layer structures. These transistors can be thin film transistors (TFTs). The multiple transistors can cooperate to form a pixel driving circuit 310 and multiple demultiplexing circuits 320.
[0032] In addition, the array functional layer 110 also includes at least one of the following traces: a trace for transmitting the data signal Data, a trace for transmitting the scan signal Scan, a trace for transmitting the drive voltage VDD, and a trace for transmitting the common voltage VSS.
[0033] Please see Figure 4The pixel driving circuit 310 includes a driving transistor T1 and a data transistor T2. The source of the data transistor T2 is connected to the data line that provides the data signal Data, the gate of the data transistor T2 is connected to the scan line that provides the scan signal Scan, and the drain of the data transistor T2 is connected to the gate of the driving transistor T1. The two ends of the storage capacitor Cst are respectively connected to the gate and the source of the driving transistor T1, and the drain of the driving transistor T1 is connected to the light-emitting device 810.
[0034] It should be noted that, Figure 4 This is one embodiment of the pixel driving circuit 310, but the pixel driving circuit 310110D of this application is not limited to... Figure 4 The pixel driving circuit 310 shown in the 2T1C diagram can also be other pixel driving circuits 310, such as 7T1C, 8T1C pixel driving circuits 310, etc.
[0035] In this embodiment, the pixel driving circuit 310110 may be located in the display area AAAA. The array functional layer 110110, which is at least partially located in the non-display area NANA, may also include other driving circuits or traces composed of thin film transistors, such as the gate driving circuit 330 (Gate In Panel, GIP), traces for transmitting the driving voltage VDD and traces for transmitting the common voltage VSS, etc., provided around the display area AA.
[0036] Optionally, please see again Figure 3 The array functional layer 110 may include multiple film layer structures, such as a buffer layer 1101, a first active layer 1102, a first gate insulating layer 1103, a first metal layer 1104, a first capacitor dielectric layer 1105, a second metal layer 1106, an interlayer insulating layer 1111, a third metal layer 1112, a first planarization layer 1113, a fourth metal layer 1114, and a second planarization layer 1115, which are stacked on one side of the substrate 100 and in a direction away from the substrate 100.
[0037] The buffer layer 1101 can be formed from inorganic materials, such as silicon oxide, silicon nitride, and silicon oxynitride. The buffer layer 1101 can be a single-layer structure, or it can be a two-layer structure consisting of silicon oxide and silicon nitride layers.
[0038] The first active layer 1102 is located on the side of the buffer layer 1101 away from the substrate 100. The material of the first active layer 1102 may include semiconductor materials, such as amorphous silicon or polycrystalline silicon. The semiconductor traces in the first active layer 1102 may be doped to form the source and drain regions of a transistor device, and the channel region of the transistor device is formed between the source and drain regions.
[0039] The first gate insulating layer 1103 is located on the side of the first active layer 1102 away from the substrate 100. The first gate insulating layer 1103 covers the semiconductor traces in the first active layer 1102 and covers the portion of the buffer layer 1101 not covered by the first active layer 1102. The material of the first gate insulating layer 1103 may include silicon oxide.
[0040] The first metal layer 1104 is located on the side of the first gate insulating layer 1103 away from the substrate 100. At least a portion of the traces in the first metal layer 1104 are located on the side of the semiconductor trace segment in the first active layer 1102 away from the substrate 100, forming the gate of the transistor. At least another portion of the traces in the first metal layer 1104 can also cooperate with traces or electrodes in the second metal layer 1106 to form a capacitor. The material of the first metal layer 1104 may include molybdenum.
[0041] The first capacitor dielectric layer 1105 is located on the side of the first metal layer 1104 away from the substrate 100. The first capacitor dielectric layer 1105 covers the metal traces in the first metal layer 1104 and covers the portion of the first gate insulating layer 1103 not covered by the first metal layer 1104. The material of the first capacitor dielectric layer 1105 may include silicon nitride.
[0042] The second metal layer 1106 is located on the side of the first capacitor dielectric layer 1105 away from the substrate 100. Some traces in the second metal layer 1106 may overlap with some traces or electrodes in the first metal layer 1104 to form a capacitor; other traces in the second metal layer 1106 may form other connection traces in the pixel driving circuit 110D. The material of the second metal layer 1106 may include molybdenum.
[0043] The interlayer insulating layer 1111 is located on the side of the second metal layer 1106 away from the substrate 100, and the material of the interlayer insulating layer 1111 may include silicon oxide and / or silicon nitride.
[0044] The third metal layer 1112 is located on the side of the interlayer insulating layer 1111 away from the substrate 100. At least a portion of the traces in the third metal layer 1112 can be electrically connected to the source or drain region of the semiconductor trace segment in the first active layer 1102 through vias penetrating the interlayer insulating layer 1111, the first capacitor dielectric layer 1105, and the first gate insulating layer 1103, forming the source and drain of a transistor device. The remaining traces in the third metal layer 1112 can form other connection traces in the pixel driving circuit 110D. The material of the third metal layer 1112 may include a titanium-aluminum-titanium three-layer composite.
[0045] The first planarization layer 1113 is located on the side of the third metal layer 1112 away from the substrate 100. The first planarization layer 1113 can achieve a certain degree of planarization while achieving insulation. The material of the first planarization layer 1113 may include organic materials.
[0046] The fourth metal layer 1114 is located on the side of the first planarization layer 1113 away from the substrate 100. Some traces in the fourth metal layer 1114 can be electrically connected to traces in the third metal layer 1112 through vias penetrating the first planarization layer 1113. Other traces in the fourth metal layer 1114 can form other connection traces in the pixel driving circuit 110D. The material of the fourth metal layer 1114 may include a titanium-aluminum-titanium three-layer composite.
[0047] The second planarization layer 1115 is located on the side of the fourth metal layer 1114 away from the substrate 100. The second planarization layer 1115 can achieve a certain degree of planarization while achieving insulation. The material of the second planarization layer 1115 may include organic materials.
[0048] Please see Figure 5 , Figure 5 for Figure 2 The diagram shows a cross-sectional view of a portion of the film layer in position II of the display panel. The pixel driving circuit 310 can be located in the display area AA, and the demultiplexing circuit 320 can be located in the non-display area NA.
[0049] The pixel driving circuit 310 is used to provide driving current to the corresponding light-emitting device 810 according to the data signal DATA, the scan signal SCAN and the light emission control signal EM, etc. The demultiplexing circuit 320 is used to demultiplex the originally multiplexed data signal into a data signal DATA according to the demultiplexing control signal and transmit it to the corresponding data signal trace.
[0050] For example, please see again Figure 2 The display panel provided in this embodiment can be a roughly rectangular display area AA, with at least one rounded corner. The non-display area NA can include a border area NA1 surrounding the display area AA, and a bonding area NA2 located on one side of the border area NA1 (as shown in the lower border) away from the display area AA. The bonding area NA2 can be used to house a driver chip, or it can be provided with bonding contacts (gold fingers) for connection with other circuit boards.
[0051] The demultiplexing circuit 320 may be disposed in the border area NA1 near the bonding area NA2, and at least some of the demultiplexing circuits 320 are arranged along the edge of the display area AA near the bonding area NA2 (along the first direction D1). For example, multiple demultiplexing circuits 320 located on the lower border are arranged along the D1 direction.
[0052] The trace for transmitting the multiplexed data signal extends from the bonding area NA2 to the border area NA1 and is connected to the demultiplexing circuit 320. The demultiplexing circuit 320 demultiplexes the multiplexed data signal according to the demultiplexing control signal and transmits it to the pixel driving circuit 310 located in the display area AA through the data signal trace extending from the border area NA1 to the display area AA (extending along the second direction D2).
[0053] Please see again Figure 1 The edge of the display area AA may have an arc angle, and at least part of the pixel driving circuit 310 is distributed in a stepped manner along the arc angle. Correspondingly, at least part of the demultiplexing circuit 320 is distributed in a stepped manner along the arc angle.
[0054] The array functional layer 110 may also include demultiplexing signal traces 410 connected to the demultiplexing circuit 320, such as traces for transmitting demultiplexing control signals and traces for transmitting multiplexed data signals.
[0055] Optionally, in this embodiment, please refer again to Figure 1 Multiple demultiplexed signal traces 410 and other traces located on the side of the demultiplexed circuit 320 away from the display area AA also extend in a stepped zigzag pattern along the arc angle.
[0056] Please see Figure 3 The light-emitting device layer is located on the side of the array functional layer 110 away from the substrate 100. The light-emitting device layer includes a plurality of first pixel electrodes 120 located in the display area AA and a plurality of first blocking electrodes 210 located in the non-display area NA. See also... Figure 5 The first pixel electrode 120 and the first occlusion electrode 210 are disposed on the same layer.
[0057] Optionally, the light-emitting device layer includes a plurality of light-emitting devices 810 located in the display area AA. Each light-emitting device 810 includes a first pixel electrode 120, a light-emitting functional layer 150, and a second pixel electrode 160 stacked in a direction away from the substrate 100.
[0058] Optionally, the display panel provided in this embodiment may further include a pixel defining layer 130, which surrounds and forms a plurality of pixel openings. The pixel openings expose corresponding first pixel electrodes 120. The light-emitting functional layer 150 is at least partially located within the corresponding pixel openings and is in contact with the first pixel electrodes 120. The second pixel electrode 160 is located on the side of the light-emitting functional layer 150 away from the substrate 100 and is in contact with the light-emitting functional layer 150.
[0059] Optionally, the first pixel electrode 120 can be an anode, and the first pixel electrode 120 can be connected to the pixel driving circuit 310 in the array functional layer 110 through a via. The second pixel electrode 160 can be a cathode, and the second pixel electrode 160 can be connected to a common voltage supply circuit through an isolation structure. When there is a potential difference between the first pixel electrode 120 and the second pixel electrode 160, the light-emitting functional layer 150 located between the first pixel electrode 120 and the second pixel electrode 160 is driven to emit light.
[0060] The first pixel electrode 120 may include a multilayer structure, such as a reflective layer and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer, respectively. The reflective layer can be formed, for example, using silver, a metal with excellent light reflectivity. Each conductive oxide layer can be formed, for example, from a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide). The second pixel electrode 160 is formed, for example, from a metallic material such as an alloy of magnesium and silver (MgAg).
[0061] The light-emitting device layer also includes a plurality of first blocking electrodes 210 located in the non-display area NA, and the first pixel electrode 120 is disposed in the same layer as the first blocking electrodes 210.
[0062] The orthographic projection of the demultiplexing circuit 320 on the substrate 100 at least partially overlaps with the orthographic projection of the corresponding first shielding electrode 210 on the substrate 100.
[0063] For example, in this embodiment, the orthographic projections of the plurality of first shielding electrodes 210 on the substrate 100 are arranged in a block shape with intervals, and the first shielding electrodes 210 correspond one-to-one with the demultiplexing circuit 320.
[0064] Based on the above design, for each demultiplexing circuit 320, by setting a first blocking electrode 210 on the same layer as the first pixel electrode 120 above the demultiplexing circuit 320 to block the demultiplexing circuit 320, the influence of light on the demultiplexing circuit 320 can be reduced, thereby reducing the risk of device degradation of the demultiplexing circuit 320. In addition, the multiple first blocking electrodes 210 are distributed in small blocks at intervals, which can reduce the reflection difference between the first blocking electrodes 210 and the first pixel electrode 120, avoid the generation of bright lines or large bright areas, and improve the reflection consistency of different areas of the display panel.
[0065] The area of the orthographic projection of a single first blocking electrode 210 onto the substrate 100 can be substantially the same as the total area of the orthographic projections of the first pixel electrodes 120 corresponding to each sub-pixel SPX in a pixel PX onto the substrate 100. For example, the area of the orthographic projection of a single first blocking electrode 210 onto the substrate 100 is 0.8 to 1.2 times the total area of the orthographic projections of the first pixel electrodes 120 corresponding to each sub-pixel SPX in a pixel PX onto the substrate 100.
[0066] In some possible implementations, the edge of the display area AA has an arc angle, and at least a portion of the pixel driving circuits 310 are distributed in a stepped manner along the arc angle, thus correspondingly at least a portion of the first pixel electrodes 120 are distributed in a stepped manner along the arc angle. At least a portion of the demultiplexing circuits 320 are distributed in a stepped manner along the arc angle, thus correspondingly at least a portion of the first blocking electrodes 210 are distributed in a stepped manner along the arc angle.
[0067] In some possible implementations, the demultiplexing circuit 320 includes a demultiplexing transistor, the orthographic projection of which onto the substrate 100 lies within the orthographic projection of the corresponding first blocking electrode 210 onto the substrate 100. Specifically, the orthographic projection of the channel region of the demultiplexing transistor in the demultiplexing circuit 320 onto the substrate 100 lies within the orthographic projection of the corresponding first blocking electrode 210 onto the substrate 100. This ensures the effective shielding of the demultiplexing transistor by the first blocking electrode 210, which is susceptible to light exposure, reducing the risk of device performance degradation due to light exposure.
[0068] For some possible implementations, please refer again. Figure 1 , Figure 2 and Figure 5 The array functional layer 110 also includes a plurality of gate driving circuits 330 located in the non-display area NA, at least some of which are located on the side of the demultiplexing circuit 320 away from the display area AA. The gate driving circuits 330 can be used to provide scanning signals and / or light emission control signals to the pixel driving circuits 310 located in the display area AA.
[0069] For example, at least part of the gate driving circuit 330 can provide scanning signals or light emission control signals to the pixel driving circuit 310 located in the display area AA through a scanning signal trace or a light emission control signal trace extending along the first direction D1.
[0070] In this case, at least part of the gate drive circuit 330 located in the arc corner region is located on the side of at least part of the demultiplexing circuit 320 away from the display area AA.
[0071] In this embodiment, please refer to Figure 5 and Figure 6The light-emitting device layer also includes a second blocking electrode 220, which is disposed on the same layer as the first pixel electrode 120. The orthographic projection of the gate driving circuit 330 on the substrate 100 is located within the orthographic projection of the second blocking electrode 220 on the substrate 100. Optionally, the orthographic projections of multiple gate driving circuits 330 on the substrate 100 are located within the orthographic projection of the same second blocking electrode 220 on the substrate 100.
[0072] In this embodiment, the second blocking electrode 220 is spaced apart from the first blocking electrode 210. For example, neither the first blocking electrode 210 nor the second blocking electrode 220 will cover the traces used to transmit demultiplexing control signals and / or multiplexed data signals located between the gate drive circuit 330 and the demultiplexing circuit 320. Thus, the first blocking electrode 210 and the second blocking electrode 220 will not overlap with these traces to form capacitance, and will not increase the impedance of these traces.
[0073] See also: [Information on possible implementations] Figure 7 and Figure 8 The light-emitting device layer also includes multiple dummy electrodes 230, which are disposed on the same layer as the first pixel electrode 120. At least some of the dummy electrodes 230 are located between the first blocking electrode 210 and the first pixel electrode 120. The first pixel electrode 120 is connected to the pixel driving circuit 310 in the array functional layer 110, while the dummy electrodes 230 may not be connected to the pixel driving circuit 310 in the array functional layer 110.
[0074] Optionally, the shape of the orthographic projection of the dummy electrode 230 on the substrate 100 is the same as the shape of the orthographic projection of the corresponding first pixel electrode 120 on the substrate 100.
[0075] For example, in the same pixel, the size of the first pixel electrode 120 corresponding to sub-pixels of different colors is different. Each pixel corresponds to a set of dummy electrodes 230. The size of multiple dummy electrodes 230 in a set of dummy electrodes 230 is the same as the size and arrangement of the first pixel electrode 120 corresponding to multiple sub-pixels in a pixel.
[0076] In this embodiment, setting a dummy electrode 230 can balance the etching load of the first pixel electrode 120 at the edge of the display area AA during the etching process, ensuring the uniformity of the etching environment of the first pixel electrode 120 at different positions, thereby ensuring the consistency of the light emission effect of each light-emitting device 810.
[0077] Furthermore, the dummy electrode 230 can form a transition zone between the first pixel electrode 120 and the first occlusion electrode 210, thereby mitigating the light emission difference between the first pixel electrode 120 and the first occlusion electrode 210 with different shapes and making the reflective boundary of the arc corner area smoother.
[0078] Optionally, in this embodiment, the orthographic projections of multiple dummy electrodes 230 on the substrate 100 surround the display area AA. Specifically, the orthographic projections of multiple sets of dummy electrodes 230 on the substrate 100 surround the display area AA.
[0079] That is, except for the arc corner area of the border area NA1 near the bonding area NA2, the dummy electrode 230 located in the border area NA1 can surround the display area AA. In this way, on the one hand, the edge reflection effect at different positions of the display area AA can be balanced, and on the other hand, the etching environment of each first pixel electrode 120 at different edge positions of the display area AA can be kept consistent, thereby ensuring the uniformity of the display effect.
[0080] For some possible implementations, please refer again. Figure 1 The array functional layer 110 also includes a first power supply trace 420 located in the non-display area NA and at least partially surrounding the display area AA, with at least a portion of the first shielding electrode 210 and / or dummy electrode 230 connected to the first power supply trace 420. The first power supply trace 420 includes a drive voltage trace, a common voltage trace, or an initialization voltage trace.
[0081] Thus, at least part of the first shielding electrode 210 and / or the dummy electrode 230 is connected to the first power supply line 420 with a constant voltage. On the one hand, this can give the first shielding electrode 210 and / or the dummy electrode 230 a certain electrostatic shielding capability, forming electrostatic protection for the light-emitting device 810 located in the display area AA. On the other hand, it can prevent strong signal coupling between other circuits or lines (such as the demultiplexing circuit 320) and the first shielding electrode 210 and / or the dummy electrode 230, thus avoiding signal crosstalk and fluctuations.
[0082] Optionally, the first shielding electrode 210 and / or the dummy electrode 230 include a first partial electrode and a second partial electrode. The orthographic projection of the first partial electrode on the substrate 100 at least partially coincides with the orthographic projection of the first power line 420 on the substrate 100, and the orthographic projection of the second partial electrode on the substrate 100 is offset from the orthographic projection of the first power line 420 on the substrate 100.
[0083] At least a portion of the first part of the electrode is electrically connected to the first power supply line 420 through a through-hole; at least a portion of the second part of the electrode is electrically connected to the first part of the electrode through an electrode connection line 240.
[0084] For example, the first part of the first shielding electrode 210 and / or the dummy electrode 230 may overlap with the first power line 420. Therefore, the first part of the electrode can be directly connected to the first power line 420 through a via. However, the second part of the first shielding electrode 210 and / or the dummy electrode 230 may not overlap with the first power line 420. Therefore, the second part of the electrode needs to be connected to the first part of the electrode, thereby connecting to the first power line 420 through the first part of the electrode.
[0085] The electrode connection line 240 is disposed on the same layer as the first pixel electrode 120, that is, the first pixel electrode 120, the first occlusion electrode 210, the dummy electrode 230 and the electrode connection line 240 are all disposed on the same layer.
[0086] In some possible implementations, this embodiment provides a display panel that further includes a touch function layer located on the side of the light-emitting device layer away from the substrate 100. The touch function layer includes touch signal traces 510 located in the non-display area NA. See also... Figure 9 The orthographic projections of at least a portion of the first shielding electrode 210 and / or at least a portion of the dummy electrode 230 on the substrate 100 at least partially coincide with the orthographic projection of the touch signal trace 510 on the substrate 100. Specifically, the orthographic projection of the touch signal trace 510 near the arc corner on the substrate 100 extends along the arc corner profile.
[0087] That is, in this embodiment, the touch signal trace 510 located in the arc corner area does not extend in a stepped manner, but extends in an arc shape along the outer contour of the arc corner. In this way, the gap between adjacent touch signal traces 510 partially contains the first shielding electrode 210 and / or at least partially the dummy electrode 230. Under the shielding of the touch signal trace 510, the reflective jaggedness caused by the stepped distribution of the first shielding electrode 210 can be further weakened, making the reflective effect in the arc corner area smoother.
[0088] In some possible implementations, the display panel further includes an ink layer located in the non-display area NA, the orthographic projection of which on the substrate 100 at least partially surrounds the display area AA. The orthographic projection of the first blocking electrode 210 on the substrate 100 lies between the display area AA and the orthographic projection of the ink layer on the substrate 100. The ink layer can be made of an opaque organic material.
[0089] That is, in this embodiment, even if the ink layer does not cover the demultiplexing circuit 320, the first shielding electrode 210 can still shield and protect the demultiplexing circuit 320, reducing the risk of the demultiplexing circuit 320 being degraded by light.
[0090] This embodiment also provides an electronic device, which includes the display panel described in this application. The electronic device may include devices with image processing capabilities, such as mobile phones, desktop computers, laptops, tablets, in-vehicle displays, wearable devices, etc. Because this electronic device includes the display panel described in this application, its reliability is higher.
[0091] In summary, this application provides a display panel and an electronic device. For each demultiplexing circuit, by setting a first blocking electrode on the same layer as the first pixel electrode above the demultiplexing circuit to block the demultiplexing circuit, the reflection difference between the first blocking electrode and the first pixel electrode can be reduced while reducing the influence of light on the demultiplexing circuit, thereby improving the reflection consistency of different areas of the display panel.
[0092] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0093] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A display panel, characterized in that, The display panel includes a display area and a non-display area located on at least one side of the display area; the display panel includes: substrate; An array functional layer located on one side of the substrate, the array functional layer including multiple demultiplexing circuits located in the non-display area; The light-emitting device layer is located on the side of the array functional layer away from the substrate. The light-emitting device layer includes a plurality of first pixel electrodes located in the display area and a plurality of first blocking electrodes located in the non-display area. The first pixel electrodes and the first blocking electrodes are disposed in the same layer. The orthogonal projection of the demultiplexing electrode on the substrate at least partially overlaps with the orthogonal projection of the corresponding first blocking electrode on the substrate.
2. The display panel according to claim 1, characterized in that, The demultiplexing circuit includes a demultiplexing transistor, the orthographic projection of which is located on the substrate within the orthographic projection of the corresponding first shielding electrode on the substrate; Preferably, the first shielding electrode corresponds one-to-one with the demultiplexing circuit.
3. The display panel according to claim 1, characterized in that, The array functional layer also includes a plurality of gate driving circuits located in the non-display area, and at least some of the gate driving circuits are located on the side of the demultiplexing circuit away from the display area; The light-emitting device layer further includes a second shielding electrode, which is disposed on the same layer as the first pixel electrode, and the orthographic projection of the gate driving circuit on the substrate is located within the orthographic projection of the second shielding electrode on the substrate; The second shielding electrode is spaced apart from the first shielding electrode; Preferably, the orthographic projections of the plurality of gate driving circuits on the substrate are located within the orthographic projection of the same second shielding electrode on the substrate.
4. The display panel according to claim 1, characterized in that, The light-emitting device layer also includes a plurality of dummy electrodes, which are disposed on the same layer as the first pixel electrode; At least a portion of the dummy electrode is located between the first blocking electrode and the first pixel electrode; Preferably, the shape of the orthographic projection of the dummy electrode on the substrate is the same as the shape of the orthographic projection of the corresponding first pixel electrode on the substrate; Preferably, the orthographic projections of the plurality of dummy electrodes on the substrate surround the display area.
5. The display panel according to claim 4, characterized in that, The array functional layer further includes a first power trace located in the non-display area and at least partially surrounding the display area, and at least a portion of the first shielding electrode and / or the dummy electrode is connected to the first power trace; The first power supply trace includes a drive voltage trace, a common voltage trace, or an initialization voltage trace; Preferably, the first shielding electrode and / or the dummy electrode includes a first part electrode and a second part electrode; The orthographic projection of the first portion of the electrode on the substrate at least partially coincides with the orthographic projection of the first power line on the substrate, and the orthographic projection of the second portion of the electrode on the substrate at least partially offsets from the orthographic projection of the first power line on the substrate; At least a portion of the first portion of the electrodes is electrically connected to the first power supply trace through a through-hole; At least a portion of the second portion of the electrode is electrically connected to the first portion of the electrode via an electrode connection wire; Preferably, the electrode line is disposed in the same layer as the first pixel electrode.
6. The display panel according to claim 4, characterized in that, The display panel further includes a touch function layer located on the side of the light-emitting device layer away from the substrate, the touch function layer including touch signal traces located in the non-display area; at least a portion of the first shielding electrode and / or at least a portion of the dummy electrode's orthographic projection on the substrate at least partially coincide with the orthographic projection of the touch signal traces on the substrate; Preferably, the edge of the display area has a rounded corner, and the orthographic projection of the touch signal trace near the rounded corner on the substrate extends along the contour of the rounded corner.
7. The display panel according to claim 3, characterized in that, The display panel further includes an ink layer located in the non-display area, the orthographic projection of the ink layer on the substrate at least partially surrounding the display area; the orthographic projection of the first shielding electrode on the substrate is located between the display area and the orthographic projection of the ink layer on the substrate.
8. The display panel according to claim 1, characterized in that, The edge of the display area has an arc angle, and a plurality of first pixel electrodes are distributed in a stepped manner along the arc angle; a plurality of first occlusion electrodes are distributed in a stepped manner along the arc angle.
9. The display panel according to claim 1, characterized in that, The light-emitting device layer further includes multiple light-emitting functional layers and second pixel electrodes. The light-emitting functional layers are located on the side of the corresponding first pixel electrode away from the substrate, and the second pixel electrodes are located on the side of the light-emitting functional layers away from the substrate.
10. An electronic device, characterized in that, The electronic device includes the display panel as described in any one of claims 1-9.